TB5T1LDW

TB5T1 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

Features

down. Third-State Logic Low Output All devices are characterized for operation from -40 C ESD Protection HBM kV, CDM kV to No Line Loading when Vcc The logic inputs of this device include internal pull-up Capable of Driving 50- Ω loads resistors of approximately k Ω that are connected to V CC to ensure a logical high level input if the inputs 2.0-ns Maximum Propagation Delay are open circuited. 0.2-ns Output Skew (typical) PIN ASSIGNMENTS Receiver k Ω 4.0-ns Maximum Propagation Delay 50-mV Hysteresis Slew Rate Limited ns min 80% to 20%) ESD Protection HBM kV, CDM kV -1.1-V to 7.1-V Input Voltage Range Common Device Range: -40 C to C Single 5.0 V 10% Supply Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package The TB5T1 device is a dual differential driver/receiver circuit that transmits and receives digital data over balanced transmission lines. The dual drivers trans- late input TTL logic levels to differential pseudo-ECL output levels. The dual receivers convert differen- tial-input logic levels to TTL output levels. Each driver or receiver pair has its own common enable control allowing serial data and a control clock to be transmitted and received on a single integrated cir- cuit. The TB5T1 requires the customer to supply ED ER termination resistors on the circuit board. Active Active Active Active The power-down loading characteristics of the re- Disabled Disabled Active Active ceiver input circuit are approximately k Ω relative to Active Active Disabled Disabled the power supplies; hence, it does not load the Disabled Disabled Disabled Disabled transmission line when the circuit is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 2003 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com POWER DISSIPATION RATINGS THERMAL CHARACTERISTICS TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER PART MARKING PACKAGE LEAD FINISH STATUS TB5T1DW TB5T1 Gull-Wing SOIC NiPdAu Production TB5T1D TB5T1 SOIC NiPdAu Production TB5T1LDW TB5T1L Gull-Wing SOIC SnPb Production TB5T1LD TB5T1L SOIC SnPb Production PACK- CIRCUIT POWER RATING THERMAL RESISTANCE, JUNCTION- DERATING FACTOR (1) POWER RATING AGE BOARD MODEL T A C TO-AMBIENT WITH NO AIR FLOW T A C T A C Low-K (2) 752 mW 132.8 C/W 7.5 mW/ C 301 mW D High-K (3) 1160 mW 85.8 C/W 11.7 mW/ C 466 mW Low-K (2) 814 mW 122.7 C/W 8.2 mW/ C 325 mW DW High-K (3) 1200 mW 83.1 C/W mW/ C 481 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no airflow. (2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3. (3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7. PARAMETER PACKAGE VALUE UNIT D 48.4 C/W Junction-to-board θ JB thermal resistance DW 55.2 C/W D 45.1 C/W Junction-to-case θ JC thermal resistance DW 48.1 C/W

www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 over operating free-air temperature range unless otherwise noted (1) UNIT Supply voltage, V CC V to V Magnitude of differential bus (input) voltage, RI1 V RI1 RI2 V RI2 8.4 V Human Body Model (2) All pins kV ESD Charged-Device Model (3) All pins kV Continuous power dissipation See Dissipation Rating Table Storage temperature, T stg -65 C to 150 C (1) Stresses beyond those listed under "absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (3) Tested in accordance with JEDEC Standard 22, Test Method C101. MIN NOM MAX UNIT Supply voltage, V CC 4.5 5.5 V Bus pin input voltage, V RI1 V RI1 V RI2 or V RI2 -1.2 (1) 7.2 V Magnitude of differential input voltage, RI1 V RI1 RI2 V RI2 0.1 V Operating free-air temperature, T A -40 C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise noted. over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Outputs disabled mA I CC Supply current Outputs enabled mA

www.ti.com THIRD STATE DRIVER ELECTRICAL CHARACTERISTICS TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 A TB5T1 driver produces pseudo-ECL levels and has a third state mode, which is different from a conventional TTL device. When a TB5T1 driver is placed in the third state, the base of the output transistors are pulled low, bringing the outputs below the active-low level of standard PECL devices. (For example: The TB5T1 low output level is typically 2.7 while the third state noninverting output level is typically 1.2 V.) In a bidirectional, multipoint bus application, the driver of one device, which is in its third state, can be back driven by another driver on the bus whose voltage in the low state is lower than the 3-stated device. This could be due to differences between individual driver's power supplies. In this case, the device in the third state controls the line, thus clamping the line and reducing the signal swing. If the difference between the driver power supplies is small, this consideration can be ignored. Again using the TB5T1 driver as an example, a typical supply voltage difference between separate drivers of V can exist without significantly affecting the amplitude of the signal. over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OH Output high voltage (1) V CC 1.8 V CC 1.3 V CC 0.8 V V OL Output low voltage (1) V OH 1.4 V OH 1.2 V OH 0.7 V V OD Differential output voltage, OH V OL 0.7 1.1 1.4 V V OH Output high voltage (1) V CC 1.8 V CC 1.3 V CC 0.8 V V OL Output low voltage (1) T A C to C V OH 1.4 V OH 1.1 V OH 0.5 V V OD Differential output voltage, OH V OL 0.5 1.1 1.4 V V OC(PP) Peak-to-peak common-mode output voltage C L pF, See Figure 230 600 mV V OZH Third state output high voltage (1) DO1 DO2 1.4 1.8 2.2 V CC 4.5 V V V OZD Third state diferential output voltage (1) V DOn V DOn -0.47 (2) -0.6 V IL Input low voltage (3) V CC 5.5 V 0.8 V V IH Input high voltage V CC 4.5 V V V IK Input clamp voltage V CC 4.5 I I mA (2) V V CC 5.5 V O V -250 (2) mA I OS Short-circuit output current (4) V CC 5.5 V OD V (2) mA I IL Input low current V CC 5.5 V I 0.4 V -400 (2) µ A I IH Input high current V CC 5.5 V I 2.7 V µ A I IH Input reverse current V CC 5.5 V I 5.5 V 100 µ A C IN Input Capacitance pF (1) Values are with terminations as per Figure (2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. (3) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment. (4) Test must be performed one lead at a time to prevent damage to the device. No test circuit attached.

www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS DRIVER SWITCHING CHARACTERISTICS TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OL Output low voltage V CC 4.5 I OL 8.0 mA 0.4 V V OH Output high voltage V CC 4.5 I OH -400 µ A 2.4 V V IL Enable input low voltage (1) V CC 5.5 V 0.8 V V IH Enable input high voltage (1) V CC 4.5 V V V IK Enable input clamp voltage V CC 4.5 I I mA (2) V V TH+ Positive-going differential input threshold voltage (1) Rin V Rin n or 100 mV V TH- Negative-going differential input threshold voltage (1) Rin V Rin n or -100 (2) mV V HYST Differential input threshold voltage hysteresis TH+ V TH- mV I OZL Off-state output low current (high V CC 5.5 V O 0.4 V -20 (2) µ A I OZH Off-state output high current (high V CC 5.5 V O 2.4 V µ A I OS Short circuit output current (3) V CC 5.5 V -100 (2) mA I IL Enable input low current V CC 5.5 V IN 0.4 V -400 (2) µ A I IH Enable input high current V CC 5.5 V IN 2.7 V µ A I IH Enable input reverse current V CC 5.5 V IN 5.5 V 100 µ A II L Differential input low current V CC 5.5V, V IN -1.2 V (2) mA I IH Differential input high current V CC 5.5V, V IN 7.2 V mA R O Output resistance Ω (1) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment. (2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. (3) Test must be performed one lead at a time to prevent damage to the device. over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t Propagation delay time, input high to output (1) C L pF, See Figure and Figure 1.2 ns t Propagation delay time, input low to output (1) 1.2 ns Δ t P Capacitive delay 0.01 0.03 ns/pF t PHZ Propagation delay time, C L pF, See Figure and Figure ns high-level-to-high-impedance output t PLZ Propagation delay time, ns low-level-to-high-impedance output t PZH Propagation delay time, ns high-impedance-to-high-level output t PZL Propagation delay time, ns high-impedance-to-low-level output t skew1 Output skew, t C L pF, See Figure and Figure 0.15 0.3 ns t skew2 Output skew, PHH t PHL PLH t PLL 0.15 1.1 ns t skew(pp) Part-to-part skew (2) 0.1 ns Δ t skew Output skew, difference between drivers 0.3 ns t TLH Rise time (20%-80%) 0.7 ns t THL Fall time (80%-20%) 0.7 ns (1) Parameters t and t are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure (2) t skew(pp) is the magnitude of the difference in propagation delay times between any specified outputs of two devices when both devices operate with the same supply voltage, at the same temperature, and have identical packages and test circuits.

www.ti.com RECEIVER SWITCHING CHARACTERISTICS 0 50 100 150 200 tpd − Propagation Delay Time − ns CL − Load Capacitance − pF tPLH tPHL TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH Propagation delay time, low-to-high-level output 2.5 C L pF (1) See Figure and Figure ns t PHL Propagation delay time, high-to-low-level output 2.5 t PLH Propagation delay time, low-to-high-level output 5.5 C L pF, See Figure and Figure ns t PHL Propagation delay time, high-to-low-level output 5.5 Propagation delay time, t PHZ ns high-level-to-high-impedance output C L pF, See Figure and Figure Propagation delay time, t PLZ ns low-level-to-high-impedance output Load capacitance L pF, See 0.7 ns Figure and Figure t skew1 Pulse width distortion, PHL t PLH Load capacitance L 150 pF, See ns Figure and Figure C L pF, T A See Figure 0.8 1.4 ns and Figure Δ t skew1p-p Part-to-part output waveform skew (2) C L pF, T A -40 C to See 1.5 ns Figure and Figure Δ t skew Same part output waveform skew (2) C L pF, See Figure and Figure 0.3 ns Propagation delay time, t PZH ns high-impedance-to-high-level output C L pF, See Figure and Figure Propagation delay time, t PZL ns high-impedance-to-low-level output t TLH Rise time (20% 80%) ns C L pF, See Figure and Figure t THL Fall time (80% 20%) ns (1) The propagation delay values with a pF load are based on design and simulation. (2) Output waveform skews are when devices operate with the same supply voltage, same temperature, have the same packages and the same test circuits. NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above as the pF load condition. The incremental increase in delay between the pF load condition and the actual total load capacitance represents the extrinsic, or external delay contributed by the load. Figure Typical Propagation Delay vs Load Capacitance at C

www.ti.com PARAMETER MEASUREMENT INFORMATION 2.4 V 0.4 V 1.5 V tTHLtTLH 80% 20% 80% 20% VOH VOL VOH VOL VOH VOL (VOH + VOL)/2 VOH VOL (VOH + VOL)/2 t P1 t P2 tPHH t PHL t PLL t PLH INPUT OUTPUTS OUTPUT OUTPUT OUTPUT ED OUTPUT OUTPUT tPHZ tPZH 2.4 V 1.5 V 0.4 V VOH VOL +0.2 V VOL VOL −0.1 V OUTPUT −0.47 V VOL VOL −0.1 V tPLZ tPZL TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 Figure Driver Propagation Delay TImes NOTE In the third state, OUTPUT is 0.47 V (minimum) more negative than OUTPUT Figure Driver Enable and Disable Delay Times for a High Input

www.ti.com OUTPUT 3.7 V 2.7 V 3.2 V VOH VOL 1.5 V tTHL tPHL tPLH tTLH 20% 80% 20% 80% INPUT INPUT ER OUTPUT 2.4 V 0.4 V 1.5 V VOH VOL tPHZ tPZH tPLZ tPZL 0.2 V0.2 V 0.2 V 0.2 V 100 200 200 CLCL CL includes test−fixture and probe capacitance. TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION (continued) Figure Receiver Propagation Delay Times Figure Receiver Enable and Disable Timing Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits. Figure Driver Test Circuit

www.ti.com OUTPUTS VOC(PP) VOC VOH VOL VOC 200 200 CLCL CP = 2 pF CL includes test−fixture and probe capacitance. TO OUTPUT OF DEVICE UNDER TEST 5 V 5 k DIODES TYPE 458E, 1N4148, OR EQUIVALENT 2 k CL TO OUTPUT OF DEVICE UNDER TEST CL 500 1.5 V TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION (continued) NOTE: All input pulses are supplied by a generator having the following characteristics: t r or t f ns, pulse repetition rate (PRR) 0.25 Mbps, pulse width 500 ns. C P includes the instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of V OS(PP) is made on test equipment with a dB bandwidth of at least GHz. Figure Test Circuit and Definitions for the Driver Common-Mode Output Voltage Figure Receiver Propagation Delay Time and Enable Time PZH t PZL Test Circuit Figure Receiver Disable Time PHZ t PLZ Test Circuit

www.ti.com TYPICAL CHARACTERISTICS −2.5 −1.5 −0.5 −50 0 50 100 150 TA − Free-Air Temperature − C VOH OLVAND EXTREMES FOR DRIVERS VCC = 4.5 V to 5.5 V, Load = 100 VOH Max VOH Min VOL Max VOL Min −3.5 −2.5 −1.5 −0.5 VOH VOL Voltage Characteristics − V TA = 25C IO − Output Current − mA 0.8 1.2 1.4 1.6 −50 0 50 100 150 VOD − Differential Output V oltage − V TA − Free−Air T emperature − °C VCC = 4.5 V to 5.5 V Load = 100 VDD Max VDD Nom VDD Min 0.5 1.5 2.5 3.5 −50 0 50 100 150 VCC = 4.5 V VOH Min VOL Min − Output Voltage − VVO TA − Free-Air Temperature − ° C TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 OUTPUT-VOLTAGE V OL AND V OH EXTREMES vs vs OUTPUT CURRENT, DRIVER FREE-AIR TEMPERATURE, DRIVER Figure 10. Figure 11. DIFFERENTIAL OUTPUT VOLTAGE MINIMUM V OH AND V OL vs vs FREE-AIR TEMPERATURE, DRIVER FREE-AIR TEMPERATURE, RECEIVER Figure 12. Figure 13.

www.ti.com Max −50 0 50 100 150 Nom Min − Low-to-High Propagation Delay − nstPLH TA − Free−Air Temperature − C VCC = 5 V 0.8 1.2 1.4 1.6 −50 0 50 100 150 Max Delay Min Delay VCC = 4.5 V to 5.5 V Load = 100 tpd − Propagation Delay Time − ns T − Temperature For Driver− C −50 0 50 100 150 − High-to-Low Propagation Delay − nst PHL VCC = 5 V Nom Min Max TA − Free−Air Temperature − C TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY TIME t or t LOW-TO-HIGH PROPAGATION DELAY vs vs FREE-AIR TEMPERATURE, DRIVER FREE-AIR TEMPERATURE, RECEIVER Figure 14. Figure 15. HIGH-TO-LOW PROPAGATION DELAY vs FREE-AIR TEMPERATURE, RECEIVER Figure 16.

www.ti.com APPLICATION INFORMATION Power Dissipation 100 120 140 0 100 200 300 400 500 D, Low−K DW, Low−K D, High−K DW, High−K Thermal Impedance − C/W Air Flow − LFM VSn ISn (VLn ILn) TJ TA PD JA TJ TA PD JA(S) JA(S) JCCA JBBA JCCAJBBA TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 The power dissipation rating, often listed as the package dissipation rating, is a function of the ambi- ent temperature, T A and the airflow around the device. This rating correlates with the device's maxi- mum junction temperature, sometimes listed in the absolute maximum ratings tables. The maximum junction temperature accounts for the processes and materials used to fabricate and package the device, in addition to the desired life expectancy. There are two common approaches to estimating the internal die junction temperature, T J In both of these methods, the device internal power dissipation P D needs to be calculated This is done by totaling the supply power(s) to arrive at the system power dissispation: Figure 17. Thermal Impedance vs Air Flow and then subtracting the total power dissipation of the external load(s): The standardized θ JA values may not accurately represent the conditions under which the device is used. This can be due to adjacent devices acting as heat sources or heat sinks, to nonuniform airflow, or The first T J calculation uses the power dissipation to the system PCB having significantly different ther- and ambient temperature, along with one parameter: mal characteristics than the standardized test PCBs. θ JA the junction-to-ambient thermal resistance, in The second method of system thermal analysis is degrees Celsius per watt. more accurate. This calculation uses the power The product of P D and θ JA is the junction temperature dissipation and ambient temperature, along with two rise above the ambient temperature. Therefore: device and two system-level parameters: θ JC the junction-to-case thermal resistance, in degrees Celsius per watt θ JB the junction-to-board thermal resistance, in Note that θ JA is highly dependent on the PCB on degrees Celsius per watt which the device is mounted and on the airflow over the device and PCB. JEDEC/EIA has defined θ CA the case-to-ambient thermal resistance, in standardized test conditions for measuring θ JA Two degrees Celsius per watt commonly used conditions are the low-K and the θ BA the board-to-ambient thermal resistance, in high-K boards, covered by EIA/JESD51-3 and degrees Celsius per watt. EIA/JESD51-7 respectively. Figure shows the In this analysis, there are two parallel paths, one low-K and high-K values of θ JA versus air flow for this through the case (package) to the ambient, and device and its package options. another through the device to the PCB to the ambi- ent. The system-level junction-to-ambient thermal im- pedance, θ JA(S) is the equivalent parallel impedance of the two parallel paths: where

www.ti.com Load Circuits Recommended Resistor Values: For 5 V Nom Supplies, RS = 200 Ω. For 3.3 V Nom Supplies, RS = 75 Ω. RSRS RT = 100 Ω Transmission Line OUTPUTINPUT Recommended Resistor Values: For 5 V Nom Supplies, RT = 200 Ω , RS = 90 Ω For 3.3 V Nom Supplies, RT = 100 Ω , RS = 30 Ω RT/2 Transmission Line OUTPUTINPUT RS RT/2 Recommended Resistor Values: For 5 V and 3.3 V Nom Supplies, RT = 100 Ω , VT = VCC − 2.55 V RT/2 Transmission Line OUTPUTINPUT VT RT/2 TB5T1 SLLS589B NOVEMBER 2003 REVISED MAY 2004 The test load circuits shown in Figure and Figure are based on a recommended pi type of load circuit shown in Figure The 100- Ω differential load resistor R T at the receiver provide proper termination for the interconnecting transmission line, assuming it has a 100- Ω characteristic impedance. The two resistors R S to ground at the driver end of the transmission line link provide dc current paths for the emitter follower output transistors. The two resistors to ground normally should not be placed at the receiver end, as they shunt the termination resistor, potentially creating an impedance mismatch with undesirable reflections. Figure 18. A Recommended pi Load Circuit Another common load circuit, a Y load, is shown in Figure The receiver-end line termination of R T is provided by the series combination of the two R T/2 resistors, while the dc current path to ground is provided by the single resistor R S Recommended values, as a function of the nominal supply voltage range, are indicated in the figure. Figure 19. A Recommended Y Load Circuit An additional load circuit, similar to one commonly used with ECL and PECL, is shown in Figure Figure 20. A Recommended PECL-Style Load Circuit An important feature of all of these recommended load circuits is that they ensure that both of the emitter follower output transistors remain active (conducting current) at all times. When deviating from these recommended values, it is important to make sure that the low-side output transistor does not turn off. Failure to do so increases the t skew2 and V OC(PP) values, increasing the potential for electromagnetic radiation.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TB5T1D ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5T1DR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5T1DW ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM TB5T1DWR ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2005, Texas Instruments Incorporated