TB5R2LD

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(TOP VIEW) ENABLE TRUTH TABLE TB5R1, TB5R2 SLLS588B NOVEMBER 2003 REVISED MAY 2004 QUAD DIFFERENTIAL PECL RECEIVERS Functional Replacements for the Agere These quad differential receivers accept digital data BRF1A, BRF2A, BRS2A, and BRS2B over balanced transmission lines. They translate differential input logic levels to TTL output logic Pin Equivalent to General Trade 26LS32 levels. High Input Impedance Approximately k Ω The TB5R1 is a pin- and function-compatible replace- 4-ns Maximum Propagation Delay ment for the Agere systems BRF1A and BRF2A; it TB5R1 Provides 50-mV Hysteresis includes 3-kV HBM and 2-kV CDM ESD protection. TB5R2 With -125-mV Threshold Offset for The TB5R2 is a pin- and function-compatible replace- Preferred State Output ment for the Agere systems BRS2A and BRS2B and -1.1-V to 7.1-V Common Mode Range incorporates a 125-mV receiver input offset, preferred state output, 3-kV HBM and 2-kV CDM ESD protec- Single 5-V 10% Supply tion. The TB5R2 preferred state feature places the Slew Rate Limited ns min 80% to 20%) high state when the inputs are open, shorted to TB5R2 Output Defaults to Logic When In- ground, or shorted to the power supply. puts Left Open or Shorted to V CC or GND The power-down loading characteristics of the re- ESD Protection HBM kV, CDM kV ceiver input circuit are approximately k Ω relative to Operating Temperature Range: -40 C to C the power supplies; hence they do not load the transmission line when the circuit is powered down. Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package The packaging for these differential line receivers include a 16-pin gull wing SOIC (DW) and SOIC (D). The enable inputs of this device include internal Digital Data or Clock Transmission Over Bal- pullup resistors of approximately k Ω that are anced Lines connected to V CC to ensure a logical high level input if the inputs are open circuited. FUNCTIONAL BLOCK DIAGRAM CONDITION Active Active Disabled Active Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2003 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com POWER DISSIPATION RATINGS ABSOLUTE MAXIMUM RATINGS TB5R1, TB5R2 SLLS588B NOVEMBER 2003 REVISED MAY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER PART MARKING Package LEAD FINISH STATUS TB5R1DW TB5R1 Gull-Wing SOIC NiPdAu Production TB5R1D TB5R1 SOIC NiPdAu Production TB5R2DW TB5R2 Gull-Wing SOIC NiPdAu Production TB5R2D TB5R2 SOIC NiPdAu Production TB5R1LDW TB5R1 Gull-Wing SOIC SnPb Production TB5R1LD TB5R1 SOIC SnPb Production TB5R2LDW TB5R2 Gull-Wing SOIC SnPb Production TB5R2LD TB5R2 SOIC SnPb Production THERMAL RESIST- CIRCUIT BOARD POWER RATINGT A ANCE,JUNCTION-TO- DERATINGFACT POWER RATINGT A PACKAGE MODEL C AMBIENTWITH NO AIR OR (1) T A C C FLOW Low-K (2) 763 mW 131.1 C/W 7.6 mW/ C 305 mW D High-K (3) 1190 mW 84.1 C/W 11.9 mW/ C 475 mW Low-K (2) 831 mW 120.3 C/W 8.3 mW/ C 332 mW DW High-K (3) 1240 mW 80.8 C/W 12.4 mW/ C 494 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow. (2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3. (3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICS PARAMETER PACKAGE VALUE UNIT D 47.5 C/W Junction-to-Board θ JB Thermal Resistance DW 53.7 C/W D 44.2 C/W Junction-to-Case θ JC Thermal Resistance DW 47.1 C/W over operating free-air temperature range unless otherwise noted (1) UNIT Supply voltage, V CC V to V Magnitude of differential bus (input) voltage, AI V|, BI V|, CI V|, DI 8.4 V Human Body Model (2) All pins kV ESD Charged-Device Model (3) All pins kV Continuous power dissipation See Dissipation Rating Table Storage temperature, T stg -65 C to 150 C (1) Stresses beyond those listed under, absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under, recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (3) Tested in accordance with JEDEC Standard 22, Test Method C101.

www.ti.com RECOMMENDED OPERATING CONDITIONS DEVICE ELECTRICAL CHARACTERISTICS RECEIVER ELECTRICAL CHARACTERISTICS TB5R1, TB5R2 SLLS588B NOVEMBER 2003 REVISED MAY 2004 MIN Nom MAX UNIT Supply voltage, V CC 4.5 5.5 V Bus pin input voltage, V AI V BI V CI V DI V -1.2 (1) 7.2 V Magnitude of differential input voltage, AI V|, BI V|, CI V|, DI 0.1 V Operating free-air temperature, T A -40 C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise noted. over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Outputs disabled mA I CC Supply current (1) Outputs enabled mA (1) Current is dc power draw as measured through GND pin and does not include power delivered to load. over operating free-air temperature range unless otherwise noted parameter test conditions min typ max unit V OL Output low voltage V CC 4.5 I OL mA 0.4 V V OH Output high voltage V CC 4.5 I OH -400 µ A 2.4 V V IL Low level enable input voltage (1) V CC 5.5 V 0.8 V V IH High level enable input voltage (1) V CC 5.5 V V V IK Enable input clamp voltage V CC 4.5 I I mA (2) V TB5R1 100 mV V TH+ Positive-going differential input threshold voltage (1) xl x or D TB5R2 (3) -50 mV TB5R1 -100 (2) mV V TH- Negative-going differential input threshold voltage (1) xl x or D TB5R2 (3) -200 (2) mV V HYST Differential input threshold voltage hysteresis, TH+ V TH_ TB5R1 mV I OZL V O 0.4 V -20 (2) µ A Output off-state current, (High-Z) V CC 5.5 V I OZH V O 2.4 V µ A I OS Output short circuit current (4) V CC 5.5 V -100 (2) mA I IL Enable input low current V CC 5.5 V IN 0.4 V -400 (2) µ A Enable input high current V IN 2.7 V µ A I IH V CC 5.5 V Enable input reverse current V IN 5.5 V 100 µ A II L Differential input low current V CC 5.5V, V IN -1.2 V (2) mA I IH Differential input high current V CC 5.5V, V IN 7.2 V mA R O Output resistance Ω (1) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment. (2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. (3) Outputs of unused receivers assume a logic level when the inputs are left open. (It is recomended that all unused positive inputs be tied to the positive power supply. No external series resistor is required.) (4) Test must be performed one lead at a time to prevent damage to the device.

www.ti.com SWITCHING CHARACTERISTICS TB5R1, TB5R2 SLLS588B NOVEMBER 2003 REVISED MAY 2004 over operating free-air temperature range unless otherwise noted parameter test conditions min typ max unit t PLH Propagation delay time, low-to-high-level output 2.5 C L pF (1) See Figure and Figure ns t PHL Propagation delay time, high-to-low-level output 2.5 t PLH Propagation delay time, low-to-high-level output C L pF, See Figure and Figure ns t PHL Propagation delay time, high-to-low-level output Output disable time, high-level-to-high-impedance out- t PHZ 4.1 ns put (2) C L pF, See Figure and Figure t PLZ Output disable time, low-level-to-high-impedance output (2) 2.8 ns C L pF, See Figure and Figure 0.7 ns t skew1 Pulse width distortion, PHL t PLH C L 150 pF, See Figure and Figure ns C L pF, T A See Figure and 0.8 1.4 ns Figure Δ t skew1p- Part-to-part output waveform skew (3) p C L pF, T A -40 C to See 1.5 ns Figure and Figure Δ t skew Same part output waveform skew (3) C L pF, See Figure and Figure 0.3 ns Output enable time, high-impedance-to-high-level out- t PZH ns put (4) C L pF, See Figure and Figure t PZL Output enable time, high-impedance-to-low-level output (4) ns t TLH Rise time (20%-80%) 3.5 ns C L pF, See Figure and Figure t THL Fall time (80%-20%) 3.5 ns (1) The propagation delay values with a pF load are based on design and simulation. (2) See Table (3) Output waveform skews are when devices operate with the same supply voltage at the same temperature and have the same packages and the same test circuits. (4) See Table

www.ti.com TYPICAL CHARACTERISTICS 0 50 100 150 200 tpd - Propagation Delay Time - ns CL - Load Capacitance - pF tPLH tPHL OUTPUT 3.7 V 2.7 V 3.2 V VOH V OL 1.5 V tTHL tPHL tPLH tTLH 20% 80% 20% 80% INPUT INPUT TB5R1, TB5R2 SLLS588B NOVEMBER 2003 REVISED MAY 2004 TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE NOTE This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above as the pF load condition. The incremental increase in delay between the pF load condition and the actual total load capacitance represents the extrinsic, or external delay contributed by the load. Figure Typical Propagation Delay vs Load Capacitance at C Figure Receiver Propagation Delay Times

www.ti.com OUTPUT 2.4 V 0.4 V 1.5 V tPHZ tPZH tPLZ tPZL 0.2 V 0.2 V 0.2 V 0.2 V 0.4 V 2.4 V 1.5 V E1(1) E1(2) VOH VOL TO OUTPUT OF DEVICE UNDER TEST 5 V 5 k DIODES TYPE 458E, 1N4148, OR EQUIVALENT 2 k CL CL includes test-fixture and probe capacitance. TO OUTPUT OF DEVICE UNDER TEST CL 500 1.5 V CL includes test-fixture and probe capacitance. TB5R1, TB5R2 SLLS588B NOVEMBER 2003 REVISED MAY 2004 TYPICAL CHARACTERISTICS (continued) while changes states. while changes states. Figure Receiver Enable and Disable Timing Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits. Figure Receiver Propagation Delay Time and Enable Time PZH t PZL Test Circuit Figure Receiver Disable Time PHZ t PLZ Test Circuit

www.ti.com Max -50 0 50 100 150 Nom Min - Low-to-High Propagation Delay - nstPLH TA - Free-Air Temperature - C VCC = 5 V -50 0 50 100 150 - High-to-Low Propagation Delay - nst PHL VCC = 5 V Nom Min Max TA - Free-Air Temperature - C -50 0 50 100 150 TA - Free-Air Temperature - C ICC - Supply Current - mA ICC max at VCC = 5.5 V ICC Typical at VCC = 5 V 0.5 1.5 2.5 3.5 -50 0 50 100 150 VCC = 4.5 V VOH min VOL min - Output Voltage - VVO TA - Free-Air Temperature - ° C TB5R1, TB5R2 SLLS588B NOVEMBER 2003 REVISED MAY 2004 TYPICAL CHARACTERISTICS (continued) LOW-TO-HIGH PROPAGATION DELAY HIGH-TO-LOW PROPAGATION DELAY vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Figure Figure MINIMUM V OH AND MAXIMUM V OL TYPICAL AND MAXIMUM I CC vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Figure Figure

www.ti.com APPLICATION INFORMATION Power Dissipation VSn ISn (1) (VLn ILn) (2) TJ TA PD JA (3) TJ TA PD JA(S) (4) JA(S) JCCA JBBA JCCAJBBA (5) 100 120 140 0 100 200 300 400 500 Thermal Impedance − C/W D, Low−K DW, Low−K DW, High−K D, High−K TB5R1, TB5R2 SLLS588B NOVEMBER 2003 REVISED MAY 2004 Note that θ JA is highly dependent on the PCB on which the device is mounted and on the airflow over The power dissipation rating, often listed as the the device and PCB. JEDEC/EIA has defined package dissipation rating, is a function of the ambi- standardized test conditions for measuring θ JA Two ent temperature, T A and the airflow around the commonly used conditions are the low-K and the device. This rating correlates with the device's maxi- high-K boards, covered by EIA/JESD51-3 and mum junction temperature, sometimes listed in the EIA/JESD51-7 respectively. Figure shows the absolute maximum ratings tables. The maximum low-K and high-K values of θ JA versus air flow for this junction temperature accounts for the processes and device and its package options. materials used to fabricate and package the device, in addition to the desired life expectancy. The standardized θ JA values may not accurately represent the conditions under which the device is There are two common approaches to estimating the used. This can be due to adjacent devices acting as internal die junction temperature, T J In both of these heat sources or heat sinks, to nonuniform airflow, or methods, the device internal power dissipation P D to the system PCB having significantly different ther- needs to be calculated This is done by totaling the mal characteristics than the standardized test PCBs. supply power(s) to arrive at the system power The second method of system thermal analysis is dissispation: more accurate. This calculation uses the power dissipation and ambient temperature, along with two device and two system-level parameters: and then subtracting the total power dissipation of the θ JC the junction-to-case thermal resistance, in external load(s): degrees Celsius per watt θ JB the junction-to-board thermal resistance, in degrees Celsius per watt The first T J calculation uses the power dissipation θ CA the case-to-ambient thermal resistance, in and ambient temperature, along with one parameter: degrees Celsius per watt θ JA the junction-to-ambient thermal resistance, in θ BA the board-to-ambient thermal resistance, in degrees Celsius per watt. degrees Celsius per watt. The product of P D and θ JA is the junction temperature In this analysis, there are two parallel paths, one rise above the ambient temperature. Therefore: through the case (package) to the ambient, and another through the device to the PCB to the ambi- ent. The system-level junction-to-ambient thermal im- pedance, θ JA(S) is the equivalent parallel impedance of the two parallel paths: where The device parameters θ JC and θ JB account for the internal structure of the device. The system-level parameters θ CA and θ BA take into account details of the PCB construction, adjacent electrical and mech- anical components, and the environmental conditions including airflow. Finite element (FE), finite difference (FD), or computational fluid dynamics (CFD) pro- grams can determine θ CA and θ BA Details on using these programs are beyond the scope of this data sheet, but are available from the software manufac- Figure 10. Thermal Impedance vs Air Flow turers.

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