TB5R2D1G4.B

TB5R2 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 18

Technical content

FEATURES

DESCRIPTION

APPLICATIONS

(TOP VIEW) Enable Truth Table TB5R1 TB5R2 SLLS588C NOVEMBER 2003 REVISED JANUARY 2008 www.ti.com QUAD DIFFERENTIAL PECL RECEIVERS Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B These quad differential receivers accept digital data over balanced transmission lines. They translate Pin Equivalent to General Trade 26LS32 differential input logic levels to TTL output logic High Input Impedance Approximately k Ω levels. 4-ns Maximum Propagation Delay The TB5R1 is a pin- and function-compatible TB5R1 Provides 50-mV Hysteresis replacement for the Agere systems BRF1A and TB5R2 With -125-mV Threshold Offset for BRF2A; it includes 3-kV HBM and 2-kV CDM ESD Preferred State Output protection. -1.1-V to 7.1-V Common Mode Range The TB5R2 is a pin- and function-compatible Single 5-V 10% Supply replacement for the Agere systems BRS2A and BRS2B and incorporates a 125-mV receiver input Slew Rate Limited ns min 80% to 20%) offset, preferred state output, 3-kV HBM and 2-kV TB5R2 Output Defaults to Logic When Inputs CDM ESD protection. The TB5R2 preferred state Left Open or Shorted to V CC or GND feature places the high state when the inputs are ESD Protection HBM kV, CDM kV open, shorted to ground, or shorted to the power supply. Operating Temperature Range: -40C to 85C The power-down loading characteristics of the Available in Gull-Wing SOIC (JEDEC MS-013, receiver input circuit are approximately k Ω relative DW) and SOIC (D) Package to the power supplies; hence they do not load the transmission line when the circuit is powered down. Digital Data or Clock Transmission Over The packaging for these differential line receivers Balanced Lines include a 16-pin gull wing SOIC (DW) and SOIC (D). The enable inputs of this device include internal pullup resistors of approximately k Ω that are connected to V CC to ensure a logical high level input if the inputs are open circuited. FUNCTIONAL BLOCK DIAGRAM CONDITION Active Active Disabled Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2003 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com POWER DISSIPATION RATINGS ABSOLUTE MAXIMUM RATINGS TB5R1 TB5R2 SLLS588C NOVEMBER 2003 REVISED JANUARY 2008 Enable Truth Table (continued) CONDITION Active These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER PART MARKING Package LEAD FINISH STATUS TB5R1DW TB5R1 Gull-Wing SOIC NiPdAu Production TB5R1D TB5R1 SOIC NiPdAu Production TB5R2DW TB5R2 Gull-Wing SOIC NiPdAu Production TB5R2D TB5R2 SOIC NiPdAu Production THERMAL RESISTANCE, DERATING CIRCUIT BOARD POWER RATING POWER RATING PACKAGE JUNCTION-TO-AMBIENT FACTOR (1) T A MODEL T A C T A C WITH NO AIR FLOW C Low-K (2) 763 mW 131.1 C/W 7.6 mW/ C 305 mW D High-K (3) 1190 mW 84.1 C/W 11.9 mW/ C 475 mW Low-K (2) 831 mW 120.3 C/W 8.3 mW/ C 332 mW DW High-K (3) 1240 mW 80.8 C/W 12.4 mW/ C 494 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow. (2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3. (3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICs PARAMETER PACKAGE VALUE UNIT D 47.5 C/W θ JB Junction-to-Board Thermal Resistance DW 53.7 C/W D 44.2 C/W θ JC Junction-to-Case Thermal Resistance DW 47.1 C/W over operating free-air temperature range unless otherwise noted (1) UNIT Supply voltage, V CC V to V Magnitude of differential bus (input) voltage, AI V|, BI V|, CI V|, DI 8.4 V Human Body Model (2) All pins kV ESD Charged-Device Model (3) All pins kV Continuous power dissipation See Dissipation Rating Table Storage temperature, T stg C to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (3) Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback Copyright 2003 2008, Texas Instruments Incorporated Product Folder Link(s): TB5R1 TB5R2

www.ti.com RECOMMENDED OPERATING CONDITIONS DEVICE ELECTRICAL CHARACTERISTICS RECEIVER ELECTRICAL CHARACTERISTICS TB5R1 TB5R2 SLLS588C NOVEMBER 2003 REVISED JANUARY 2008 MIN Nom MAX UNIT Supply voltage, V CC 4.5 5.5 V Bus pin input voltage, V AI V BI V CI V DI V 1.2 (1) 7.2 V Magnitude of differential input voltage, AI V|, BI V|, CI V|, DI 0.1 V Operating free-air temperature, T A -40 C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise noted. over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Outputs disabled mA I CC Supply current (1) Outputs enabled mA (1) Current is dc power draw as measured through GND pin and does not include power delivered to load. over operating free-air temperature range unless otherwise noted parameter test conditions min typ max unit V OL Output low voltage V CC 4.5 I OL mA 0.4 V V OH Output high voltage V CC 4.5 I OH -400 A 2.4 V V IL Low level enable input voltage (1) V CC 5.5 V 0.8 V V IH High level enable input voltage (1) V CC 5.5 V V V IK Enable input clamp voltage V CC 4.5 I I mA (2) V TB5R1 100 mV V TH+ Positive-going differential input threshold voltage (1) xl x or D TB5R2 (3) -50 mV TB5R1 -100 (2) mV V TH- Negative-going differential input threshold voltage (1) xl x or D TB5R2 (3) -200 (2) mV V HYST Differential input threshold voltage hysteresis, TH+ V TH_ TB5R1 mV I OZL V O 0.4 V -20 (2) A Output off-state current, (High-Z) V CC 5.5 V I OZH V O 2.4 V A I OS Output short circuit current (4) V CC 5.5 V -100 (2) mA I IL Enable input low current V CC 5.5 V IN 0.4 V -400 (2) A Enable input high current V IN 2.7 V A I IH V CC 5.5 V Enable input reverse current V IN 5.5 V 100 A II L Differential input low current V CC 5.5V, V IN -1.2 V (2) mA I IH Differential input high current V CC 5.5V, V IN 7.2 V mA R O Output resistance Ω (1) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment. (2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. (3) Outputs of unused receivers assume a logic level when the inputs are left open. (It is recomended that all unused positive inputs be tied to the positive power supply. No external series resistor is required.) (4) Test must be performed one lead at a time to prevent damage to the device. Copyright 2003 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TB5R1 TB5R2

www.ti.com SWITCHING CHARACTERISTICS TYPICAL CHARACTERISTICS 0 50 100 150 200 tpd - Propagation Delay Time - ns C L - Load Capacitance - pF tPLH tPHL TB5R1 TB5R2 SLLS588C NOVEMBER 2003 REVISED JANUARY 2008 over operating free-air temperature range unless otherwise noted parameter test conditions min typ max unit t PLH Propagation delay time, low-to-high-level output 2.5 C L pF (1) See Figure and Figure ns t PHL Propagation delay time, high-to-low-level output 2.5 t PLH Propagation delay time, low-to-high-level output C L pF, See Figure and Figure ns t PHL Propagation delay time, high-to-low-level output Output disable time, high-level-to-high-impedance t PHZ 4.1 ns output (2) C L pF, See Figure and Figure t PLZ Output disable time, low-level-to-high-impedance output (2) 2.8 ns C L pF, See Figure and Figure 0.7 ns t skew1 Pulse width distortion, PHL t PLH C L 150 pF, See Figure and Figure ns C L pF, T A 75C, See Figure and 0.8 1.4 ns Figure Δ t skew1p Part-to-part output waveform skew (3) C L pF, T A -40C to 85C, See Figure 1.5 ns and Figure Δ t skew Same part output waveform skew (3) C L pF, See Figure and Figure 0.3 ns Output enable time, high-impedance-to-high-level t PZH ns output (2) C L pF, See Figure and Figure t PZL Output enable time, high-impedance-to-low-level output (2) ns t TLH Rise time (20%-80%) 3.5 ns C L pF, See Figure and Figure t THL Fall time (80%-20%) 3.5 ns (1) The propagation delay values with a pF load are based on design and simulation. (2) See Table (3) Output waveform skews are when devices operate with the same supply voltage at the same temperature and have the same packages and the same test circuits. TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE NOTE This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above as the pF load condition. The incremental increase in delay between the pF load condition and the actual total load capacitance represents the extrinsic, or external delay contributed by the load. Figure Typical Propagation Delay Submit Documentation Feedback Copyright 2003 2008, Texas Instruments Incorporated Product Folder Link(s): TB5R1 TB5R2

www.ti.com OUTPUT 3.7 V 2.7 V 3.2 V V OH V OL 1.5 V tTHL tPHL tPLH tTLH 20% 80% 20% 80% INPUT INPUT OUTPUT 2.4 V 0.4 V 1.5 V tPHZ tPZH tPLZ tPZL 0.2 V 0.2 V 0.2 V 0.2 V 0.4 V 2.4 V 1.5 V E1(A) E1(B) VOH VOL TO OUTPUT OF DEVICE UNDER TEST 5 V 5 k DIODES TYPE 458E, 1N4148, OR EQUIV ALENT 2 k C L C L includes test-fixture and probe capacitance. TB5R1 TB5R2 SLLS588C NOVEMBER 2003 REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) vs Load Capacitance at 25C Figure Receiver Propagation Delay Times while changes states. while changes states. Figure Receiver Enable and Disable Timing Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits. Figure Receiver Propagation Delay Time and Enable Time PZH t PZL Test Circuit Copyright 2003 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TB5R1 TB5R2

www.ti.com TO OUTPUT OF DEVICE UNDER TEST C L 500 /C0087 1.5 V C L includes test-fixture and probe capacitance. Max -50 0 50 100 150 Nom Min - Low-to-High Propagation Delay - nstPLH TA - Free-Air Temperature - /C0053C VCC = 5 V -50 0 50 100 150 - High-to-Low Propagation Delay - nstPHL VCC = 5 V Nom Min Max TA - Free-Air Temperature - /C0053C -50 0 50 100 150 TA - Free-Air Temperature - /C0053C ICC - Supply Current - mA ICC max at VCC = 5.5 V ICC Typical at VCC = 5 V 0.5 1.5 2.5 3.5 -50 0 50 100 150 VCC = 4.5 V VOH min VOL min - Output Voltage - VVO TA - Free-Air Temperature - °C TB5R1 TB5R2 SLLS588C NOVEMBER 2003 REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) Figure Receiver Disable Time PHZ t PLZ Test Circuit LOW-TO-HIGH PROPAGATION DELAY HIGH-TO-LOW PROPAGATION DELAY vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Figure Figure MINIMUM V OH AND MAXIMUM V OL TYPICAL AND MAXIMUM I CC vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Figure Figure Submit Documentation Feedback Copyright 2003 2008, Texas Instruments Incorporated Product Folder Link(s): TB5R1 TB5R2

www.ti.com APPLICATION INFORMATION Power Dissipation /C0525/C0466V Sn /C0032ISn/C0467 (1) /C0525(V Ln /C0032ILn) (2) TJ /C0043TA /C0041/C0466P D /C0032/C0113JA/C0467 (3) TJ /C0043TA /C0041/C0466P D /C0032/C0113JA(S)/C0467 (4) /C0113JA(S) /C0043 /C0426/C0466/C0113JC/C0041/C0113CA /C0467/C0032/C0466/C0113JB/C0041/C0113BA /C0467/C0427 /C0466/C0113JC/C0041/C0113CA /C0041/C0113JB/C0041/C0113BA /C0467 (5) 100 120 140 0 100 200 300 400 500 Thermal Impedance − C/W D, Low−K DW , Low−K DW , High−K D, High−K TB5R1 TB5R2 SLLS588C NOVEMBER 2003 REVISED JANUARY 2008 which the device is mounted and on the airflow over the device and PCB. JEDEC/EIA has defined standardized test conditions for measuring θ JA Two The power dissipation rating, often listed as the commonly used conditions are the low-K and the package dissipation rating, is a function of the high-K boards, covered by EIA/JESD51-3 and ambient temperature, T A and the airflow around the EIA/JESD51-7 respectively. Figure shows the device. This rating correlates with the device's low-K and high-K values of θ JA versus air flow for this maximum junction temperature, sometimes listed in device and its package options. the absolute maximum ratings tables. The maximum The standardized θ JA values may not accurately junction temperature accounts for the processes and represent the conditions under which the device is materials used to fabricate and package the device, used. This can be due to adjacent devices acting as in addition to the desired life expectancy. heat sources or heat sinks, to nonuniform airflow, or There are two common approaches to estimating the to the system PCB having significantly different internal die junction temperature, T J In both of these thermal characteristics than the standardized test methods, the device internal power dissipation P D PCBs. The second method of system thermal needs to be calculated This is done by totaling the analysis is more accurate. This calculation uses the supply power(s) to arrive at the system power power dissipation and ambient temperature, along dissispation: with two device and two system-level parameters: θ JC the junction-to-case thermal resistance, in degrees Celsius per watt and then subtracting the total power dissipation of the θ JB the junction-to-board thermal resistance, in external load(s): degrees Celsius per watt θ CA the case-to-ambient thermal resistance, in degrees Celsius per watt The first T J calculation uses the power dissipation θ BA the board-to-ambient thermal resistance, in and ambient temperature, along with one parameter: degrees Celsius per watt. θ JA the junction-to-ambient thermal resistance, in In this analysis, there are two parallel paths, one degrees Celsius per watt. through the case (package) to the ambient, and The product of P D and θ JA is the junction temperature another through the device to the PCB to the rise above the ambient temperature. Therefore: ambient. The system-level junction-to-ambient thermal impedance, θ JA(S) is the equivalent parallel impedance of the two parallel paths: where The device parameters θ JC and θ JB account for the internal structure of the device. The system-level parameters θ CA and θ BA take into account details of the PCB construction, adjacent electrical and mechanical components, and the environmental conditions including airflow. Finite element (FE), finite difference (FD), or computational fluid dynamics (CFD) programs can determine θ CA and θ BA Details on using these programs are beyond the scope of this data sheet, but are available from the software manufacturers. Figure 10. Thermal Impedance vs Air Flow Note that θ JA is highly dependent on the PCB on Copyright 2003 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TB5R1 TB5R2

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TB5R1D Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5R1 TB5R1D.B Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5R1 TB5R1DW Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5R1 TB5R1DW.B Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5R1 TB5R2D Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5R2 TB5R2D.B Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5R2 TB5R2D1G4.B Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5R2 TB5R2DWR Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5R2 TB5R2DWR.B Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5R2 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 1

www.ti.com 23-May-2025 (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TB5R2DWR SOIC DW 16 2000 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TB5R1D D SOIC 16 40 505.46 6.76 3810 4 TB5R1D.B D SOIC 16 40 505.46 6.76 3810 4 TB5R1DW DW SOIC 16 40 506.98 12.7 4826 6.6 TB5R1DW.B DW SOIC 16 40 506.98 12.7 4826 6.6 TB5R2D D SOIC 16 40 505.46 6.76 3810 4 TB5R2D.B D SOIC 16 40 505.46 6.76 3810 4 TB5R2D1G4.B D SOIC 16 40 505.46 6.76 3810 4 Pack Materials-Page 3

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. SOIC - 2.65 mm max heightDW 16 SMALL OUTLINE INTEGRATED CIRCUIT7.5 x 10.3, 1.27 mm pitch 4224780/A

www.ti.com PACKAGE OUTLINE C TYP10.63 9.97

2.65 MAX

14X 1.27 16X 0.51 0.31 8.89 TYP0.33 0.10 0 - 8 0.3 0.1 (1.4) 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 10.5 10.1 B NOTE 4 7.6 7.4 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. 1 16

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

(9.3) 14X (1.27) R0.05 TYP 16X (2) 16X (0.6) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:7X SYMM 8 9 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN R0.05 TYP 16X (2) 16X (0.6) 14X (1.27) (9.3) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X SYMM SYMM 8 9

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated