TB5D2HDW

TB5D1M TI | Alldatasheet

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(TOP VIEW) CO DO BO AO AI BI CI DI AO AO BO BO CO CO DO DO FUNCTIONAL DIAGRAM E1 E2 Condition 0 0 Active 1 0 Active 0 1 Disabled 1 1 Active ENABLE TRUTH T ABLE TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 www.ti.com QUAD DIFFERENTIAL PECL DRIVERS The TB5D1M device is a pin and functional replacement for the Agere systems BDG1A and Functional Replacements for the Agere BPNGA quad differential drivers. The TB5D1M has a BDG1A, BPNGA and BDGLA built-in lightning protection circuit to absorb large Pin-Equivalent to the General-Trade 26LS31 transitions on the transmission lines without Device destroying the device. When the circuit is powered down it loads the transmission line, because of the 2.0 ns Maximum Propagation Delays protection circuit. 0.15 ns Output Skew Typical Between Pairs The TB5D2H device is a pin and functional Capable of Driving 50- Ω Loads replacement for the Agere systems BDG1A and 5.0-V or 3.3-V Supply Operation BDGLA quad differential drivers. Upon power down TB5D1M Includes Surge Protection on the TB5D2H output circuit appears as an open circuit Differential Outputs and does not load the transmission line. TB5D2H No Line Loading When V CC Both drivers feature a 3-state output with a third-state level of less than 0.1 Third State Output Capability -40C to 85C Operating Temp Range The packaging options available for these quad differential line drivers include a 16-pin SOIC ESD Protection HBM kV and CDM kV gull-wing (DW) and a 16-pin SOIC (D) package. Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Packages Both drivers are characterized for operation from -40C to 85C The logic inputs of this device include internal pull-up Digital Data or Clock Transmission Over resistors of approximately k Ω that are connected Balanced Transmission Lines to V CC to ensure a logical high level input if the inputs are open circuited. These quad differential drivers are TTL input to pseudo-ECL differential output used for digital data transmission over balanced transmission lines. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2003 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com PACKAGE DISSIPATION RATINGS THERMAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER PART MARKING PACKAGE LEAD FINISH STATUS TB5D1MDW TB5D1M Gull-wing SOIC NiPdAu Production TB5D1MD TB5D1M SOIC NiPdAu Production TB5D2HDW TB5D2H Gull-wing SOIC NiPdAu Production TB5D2HD TB5D2H SOIC NiPdAu Production CIRCUIT T A C THERMAL RESISTANCE, DERATING FACTOR (1) T A 85C POWER PACKAGE BOARD POWER JUNCTION-TO-AMBIENT ABOVE T A 25C RATING MODEL RATING WITH NO AIR FLOW Low-K (2) 754 mW 132.6 C/W 7.54 mW/C 301 mW D High-K (3) 1166 mW 85.8 C/W 11.7 mW/C 466 mW Low-K (2) 816 mW 122.5 C/W 8.17 mW/C 326 mW DW High-K (3) 1206 mW 82.9 C/W 12.1 mW/C 482 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow. (2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3. (3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7. PARAMETER PACKAGE VALUE UNITS D 51.4 C/W θ JB Junction-to-board thermal resistance DW 56.6 C/W D 45.7 C/W θ JC Junction-to-case thermal resistance DW 49.2 C/W over operating free-air temperature range unless otherwise noted (1) TB5D1M, TB5D2H Supply voltage, V CC V to V Input voltage 0.3 V to CC 0.3 Human Body Model (2) All Pins kV ESD Charged-Device Model (3) All Pins kV Continuous power dissipation See Dissipation Rating Table Storage temperature, T stg -65C to 130C Junction temperature, T J 130C D Package -80 V to 100 V Lightning surge, TB5D1M only, see Figure DW Package -100 V to 100 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (3) Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback Copyright 2003 2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H

www.ti.com RECOMMENDED OPERATING CONDITIONS (1) ELECTRICAL CHARACTERISTICS TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 MIN NOM MAX UNIT Supply voltage, V CC 5.0-V nominal supply 4.5 5.5 V 3.3-V nominal supply 3.0 3.3 3.6 V Operating free-air temperature, T A -40 C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise stated. over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit V CC 4.5 V to 5.5 no loads I CC Supply current mA V CC 3.0 V to 3.6 no loads V CC 4.5 V to 5.5 290 360 Figure loads all outputs P D Power dissipation mW V CC 3.0 V to 3.6 280 360 Figure loads all outputs V OH Output high voltage V CC 1.8 V CC 1.3 V CC 0.8 V V CC 4.5 V to 5.5 V OL Output low voltage V OH 1.4 V OH 1.2 V OH 0.7 V Figure V OD Differential output voltage OH V OL 0.7 1.2 1.4 V V OH Output high voltage V CC 1.8 V CC 1.3 V CC 0.8 V V CC 3.0 V to 3.6 V OL Output low voltage V OH 1.4 V OH 1.1 V OH 0.5 V Figure V OD Differential output voltage OH V OL 0.5 1.1 1.4 V Peak-to-peak common-mode output V OC(PP) C L pF, Figure 230 600 mV voltage V OZ Third-state output voltage Figure or Figure load 0.1 V V IL Low level input voltage (2) 0.8 V V IH High level input voltage V V IK Enable input clamp voltage V CC 4.5 I I mA (3) V V CC 5.5 V O V -250 (3) I OS Output short-circuit current (4) mA V CC 5.5 V OD V (3) I IL Input low current, enable or data V CC 5.5 V I 0.4 V -400 (3) A Input high current, enable or data V CC 5.5 V I =2.7 V A I IH Input reverse current, enable or data V CC 5.5 V I =5.5 V 100 A C IN Input capacitance pF (1) All typical values are at 25C and with a 3.3-V or 5-V supply. (2) The input level provides no noise immunity and should be tested only in a static, noise-free environment. (3) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. (4) Test must be performed one output at a time to prevent damage to the device. No test circuit attached. Copyright 2003 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TB5D1M TB5D2H

www.ti.com SWITCHING CHARACTERISTICS, 5-V NOMINAL SUPPLY TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 THIRD STATE A TB5D1M (or TB5D2H) driver produces pseudo-ECL levels, and has a third-state mode, which is different than a conventional TTL device. When a TB5D1M (or TB5D2H) driver is placed in the third state, the base of the output transistors is pulled low, bringing the outputs below the active-low level of standard PECL devices. [For example: The TB5D1M low output level is typically 2.7 while the third state output level is less than 0.1 V.] In a bidirectional, multipoint, bus application, the driver of one device, which is in its third state, may be back driven by another driver on the bus whose voltage in the low state is lower than the third-stated device. This could come about due to differences in the driver's independent power supplies. In this case, the device in the third state controls the line, thus clamping the line and reducing the signal swing. If the difference voltage between the independent driver power supplies is small, this consideration can be ignored. Again using the TB5D1M driver as an example, a typical supply voltage difference between separate drivers of V can exist without significantly affecting the amplitude of the signal. over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit t Propagation delay time, input high to output (2) 1.2 C L pF, See Figure and ns Figure t Propagation delay time, input low to output (2) 1.2 Δ t P Capacitive delay 0.01 0.03 ns/pF Propagation delay time, t PHZ high-level-to-high-impedance output Propagation delay time, t PLZ low-level-to-high-impedance output C L pF, See Figure and ns Figure Propagation delay time, t PZH high-impedance-to-high-level output Propagation delay time, t PZL high-impedance-to-low-level output t skew1 Output skew, t 0.15 0.3 t shew2 Output skew, PHH t PHL PLH t PLL 0.15 1.1 C L pF, See Figure and ns Figure t skew(pp) Part-to-part skew (3) 0.1 Δ t skew Output skew, difference between drivers (4) 0.3 t TLH Rise time (20% 80%) 0.7 C L pF, See Figure and ns Figure t THL Fall time (80% 20%) 0.7 (1) All typical values are at 25C and with a 5-V supply. (2) Parameters t and t are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure (3) t skew(pp) is the magnitude of the difference in differential propagation delay times, t or t between any specified outputs of two devices when both devices operate with the same supply voltage, at the same temperature, and have identical packages and test circuits. (4) Δ t skew is the magnitude of the difference in differential skew t skew1 between any specified outputs of a single device. Submit Documentation Feedback Copyright 2003 2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H

www.ti.com SWITCHING CHARACTERISTICS, 3.3-V NOMINAL SUPPLY TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 over recommended operating conditions unless otherwise noted typ parameter test conditions min max unit t Propagation delay time, input high to output (2) 1.2 3.5 C L pF, See Figure and ns Figure t Propagation delay time, input low to output (2) 1.2 3.5 Δ t P Capacitive delay 0.01 0.03 ns/pF t PHZ Propagation delay time, high-level-to-high-impedance output t PLZ Propagation delay time, low-level-to-high-impedance output C L pF, See Figure and ns Figure t PZH Propagation delay time, high-impedance-to-high-level output t PZL Propagation delay time, high-impedance-to-low-level output t skew1 Output skew, t 0.15 0.3 t shew2 Output skew, PHH t PHL PLH t PLL 0.15 1.2 C L pF, See Figure and ns Figure t skew(pp) Part-to-part skew (3) 0.1 Δ t skew Output skew, difference between drivers (4) 0.3 t TLH Rise time (20% 80%) 0.7 C L pF, See Figure and ns Figure t THL Fall time (80% 20%) 0.7 (1) All typical values are at 25C and with a 3.3-V supply. (2) Parameters t and t are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure (3) t skew(pp) is the magnitude of the difference in differential propagation delay times, t or t between any specified outputs of two devices when both devices operate with the same supply voltage, at the same temperature, and have identical packages and test circuits. (4) Δ t skew is the magnitude of the difference in differential skew t skew1 between any specified outputs of a single device. Copyright 2003 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TB5D1M TB5D2H

www.ti.com tP1 tPHH tPHL tP2 tPLL tPLH ttLH 80% 20% ttHL 80% 20% 2.4 V 1.5 V 0.4 V VOH VOL VOH (VOH + VOL )/2 VOL VOH (VOH + VOL )/2 VOL VOH VOL INPUT OUTPUTS OUTPUT OUTPUT OUTPUT (1) E2 = 1 while E1 changes state (2) E1 = 0 while E2 changes state NOTE: In the third state, both outputs (OUTPUT and OUTPUT) are 0.1 V (max). 2.4 V 1.5 V 0.4 V 2.4 V 1.5 V 0.4 V VOH VOL + 0.2 V VOL VOL − 0.1 V VOL VOL − 0.1 V tPHZ tPZH tPLZ tPZL E1(1) E2(2) OUTPUT OUTPUT TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 Figure Propagation Delay Time Waveforms Figure Enable and Disable Delay Time Waveforms Submit Documentation Feedback Copyright 2003 2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H

www.ti.com TEST CONDITIONS C L 200 Ω 200 Ω 100 Ω C L OUTPUT OUTPUT C L 75 Ω 75 Ω 100 Ω C L OUTPUT OUTPUT Note: All input pulses are supplied by a generator having the following characteristics: tr or tf = 1 ns, pulse repetition rate The measurement of VOC(PP) is made on test equipment with a ±3 dB bandwidth of at least 1 GHz. C L

200 W 200 W

C LC P = 2 pF 50 W VOC VOC(PP) VOH VOL OUTPUT VOC C L

75 W 75 W

C LC P = 2 pF 50 W VOC Note: VOC(PP) load circuit for 5-V nominal supplies. Note: VOC(PP) load circuit for 3.3-V nominal supplies. OUTPUT OUTPUT OUTPUT OUTPUT TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 Parametric values specified under the Electrical Characteristics and Switching Characteristics sections are measured with the following output load circuit. Figure Driver Test Circuits, 5-V Nominal Supplies Figure Driver Test Circuits, 3.3-V Nominal Supplies Figure Test Circuits and Definitions for the Driver Common-Mode Output Voltage Copyright 2003 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TB5D1M TB5D2H

www.ti.com Note: Surges may be applied simultaneously, but never in opposite polarities. Surge test pulses have tr = tf = 2 µs, pulse width = 7 µs (50% points), and period = 250 ms. 110 Ω 110 Ω Lightning Surge Test Generators _+ VCC DUT TYPICAL CHARACTERISTICS -2.5 -1.5 -0.5 -50 0 50 100 150 TA - Free-Air Temperature - °C VOH Max VOH Min VOL Max VOL Min VCC = 4.5 V to 5.5 V, Figure 3 Load - Output Voltage Relative To VCCVO - V -3.5 -2.5 -1.5 -0.5 -50 -40 -30 -20 -10 0 VOH VOL - Output Voltage Relative To VCCVO - V IO - Output Current - mA TA = 25/C0053C TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 Figure Lightning-Surge Testing Configuration for TB5D1M OUTPUT VOLTAGE RELATIVE TO V CC OUTPUT VOLTAGE RELATIVE TO V CC vs vs OUTPUT CURRENT FREE-AIR TEMPERATURE Figure Figure Submit Documentation Feedback Copyright 2003 2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H

www.ti.com 0.5 1.5 2.5 3.5 −50 0 50 100 150 − Propagation Delay Time − nstP TA - Free-Air Temperature - /C0053C Max Delay VCC = 3 V to 3.6 V, Figure 4 Load Min Delay TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY TIME t or t vs FREE-AIR TEMPERATURE Figure 13. Submit Documentation Feedback Copyright 2003 2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H

www.ti.com APPLICATION INFORMATION Power Dissipation /C0083(VSn /C0032ISn ) (1) /C0083(VLn /C0032ILn) (2) TJ /C0043TA /C0041(PD /C0032/C0113JA ) (3) TJ /C0043TA /C0041(PD /C0032/C0113JA(S)) (4) /C0113JA(S) /C0043 (/C0113JC /C0041/C0113CA )/C0032(/C0113JB /C0041/C0113BA ) (/C0113JC /C0041/C0113CA /C0041/C0113JB /C0041/C0113BA ) 100 120 140 0 100 200 300 400 500 D, Low−K DW , Low−K D, High−K DW , High−K Thermal Impedance − C/W Air Flow − LFM TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 the device and PCB. JEDEC/EIA has defined standardized test conditions for measuring θ JA Two commonly used conditions are the low-K and the The power dissipation rating, often listed as the high-K boards, covered by EIA/JESD51-3 and package dissipation rating, is a function of the EIA/JESD51-7 respectively. Figure shows the ambient temperature, T A and the airflow around the low-K and high-K values of θ JA versus air flow for this device. This rating correlates with the device's device and its package options. maximum junction temperature, sometimes listed in The standardized θ JA values may not accurately the absolute maximum ratings tables. The maximum represent the conditions under which the device is junction temperature accounts for the processes and used. This can be due to adjacent devices acting as materials used to fabricate and package the device, heat sources or heat sinks, to nonuniform airflow, or in addition to the desired life expectancy. to the system PCB having significantly different There are two common approaches to estimating the thermal characteristics than the standardized test internal die junction temperature, T J In both of these PCBs. The second method of system thermal methods, the device s internal power dissipation, P D analysis is more accurate. This calculation uses the needs to be calculated. This is done by totaling the power dissipation and ambient temperature, along supply power(s) to arrive at the system power with two device and two system-level parameters: dissipation: θ JC the junction-to-case thermal resistance, in degrees Celsius per watt θ JB the junction-to-board thermal resistance, in and then subtracting the total power dissipation of the degrees Celsius per watt external load(s): θ CA the case-to-ambient thermal resistance, in degrees Celsius per watt θ BA the board-to-ambient thermal resistance, in The first T J calculation uses the power dissipation degrees Celsius per watt. and ambient temperature, along with one parameter: θ JA the junction-to-ambient thermal resistance, in In this analysis, there are two parallel paths, one degrees Celsius per watt. through the case (package) to the ambient, and another through the device to the PCB to the The product of P D and θ JA is the junction temperature ambient. The system-level junction-to-ambient rise above the ambient temperature. Therefore: thermal impedance, θ JA(S) is the equivalent parallel impedance of the two parallel paths: where The device parameters θ JC and θ JB account for the internal structure of the device. The system-level parameters θ CA and θ BA take into account details of the PCB construction, adjacent electrical and mechanical components, and the environmental conditions including airflow. Finite element (FE), finite difference (FD), or computational fluid dynamics (CFD) programs can determine θ CA and θ BA Details on using these programs are beyond the scope of this data sheet, but are available from the software manufacturers. Figure 14. Thermal Impedance vs Air Flow Note that θ JA is highly dependent on the PCB on which the device is mounted, and on the airflow over Copyright 2003 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TB5D1M TB5D2H

www.ti.com Load Circuits Recommended Resistor Values: For 5 V Nom Supplies, RT = 200 Ω , RS = 90 Ω For 3.3 V Nom Supplies, RT = 100 Ω , RS = 30 Ω R T/2 Transmission Line OUTPUTINPUT R S R T/2 Recommended Resistor Values: For 5 V and 3.3 V Nom Supplies, RT = 100 Ω , VT = VCC - 2.55 V R T/2 Transmission Line OUTPUTINPUT VT R T/2 INPUT RT = 100/C0087 OUTPUT R SR S Transmission Line Recommended Resistor Values: For 5-V Nominal Supplies, RS = 200 /C0087 For 3.3-V Nominal Supplies, RS = 75 /C0087 TB5D1M TB5D2H SLLS579C SEPTEMBER 2003 REVISED JANUARY 2008 The test load circuits shown in Figure and Figure are based on a recommended pi type of load circuit shown in Figure The 100- Ω differential load resistor R T at the receiver provide proper termination for the interconnecting transmission line, assuming it has a 100- Ω characteristic impedance. The two resistors R S to ground at the driver end of the Figure 16. A Recommended Y Load Circuit transmission line link provide dc current paths for the emitter follower output transistors. The two resistors An additional load circuit, similar to one commonly to ground normally should not be placed at the used with ECL and PECL, is shown in Figure receiver end, as they shunt the termination resistor, potentially creating an impedance mismatch with undesirable reflections. Figure 17. A Recommended PECL-Style Load Circuit Figure 15. A Recommended pi Load Circuit An important feature of all of these recommended load circuits is that they ensure that both of the Another common load circuit, a Y load, is shown in emitter follower output transistors remain active Figure The receiver-end line termination of R T is (conducting current) at all times. When deviating from provided by the series combination of the two RT/2 these recommended values, it is important to make resistors, while the dc current path to ground is sure that the low-side output transistor does not turn provided by the single resistor R S Recommended off. Failure to do so increases the t skew2 and V OC(PP) values, as a function of the nominal supply voltage values, increasing the potential for electromagnetic range, are indicated in the figure. radiation. Submit Documentation Feedback Copyright 2003 2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TB5D1MD Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D1M TB5D1MD.B Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D1M TB5D1MDE4 Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D1M TB5D1MDW Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D1M TB5D1MDW.B Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D1M TB5D1MDWR Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D1M TB5D1MDWR.B Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D1M TB5D2HD Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H TB5D2HD.B Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H TB5D2HD1G4 Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H TB5D2HD1G4.B Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H TB5D2HDR Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H TB5D2HDR.B Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H TB5D2HDW Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H TB5D2HDW.B Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H TB5D2HDW1G4 Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H Addendum-Page 1

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TB5D2HDW1G4.B Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB5D2H (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TB5D1MDWR SOIC DW 16 2000 350.0 350.0 43.0 TB5D2HDR SOIC D 16 2500 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TB5D1MD D SOIC 16 40 505.46 6.76 3810 4 TB5D1MD.B D SOIC 16 40 505.46 6.76 3810 4 TB5D1MDE4 D SOIC 16 40 505.46 6.76 3810 4 TB5D1MDW DW SOIC 16 40 506.98 12.7 4826 6.6 TB5D1MDW.B DW SOIC 16 40 506.98 12.7 4826 6.6 TB5D2HD D SOIC 16 40 505.46 6.76 3810 4 TB5D2HD.B D SOIC 16 40 505.46 6.76 3810 4 TB5D2HD1G4 D SOIC 16 40 505.46 6.76 3810 4 TB5D2HD1G4.B D SOIC 16 40 505.46 6.76 3810 4 TB5D2HDW DW SOIC 16 40 506.98 12.7 4826 6.6 TB5D2HDW.B DW SOIC 16 40 506.98 12.7 4826 6.6 TB5D2HDW1G4 DW SOIC 16 40 506.98 12.7 4826 6.6 TB5D2HDW1G4.B DW SOIC 16 40 506.98 12.7 4826 6.6 Pack Materials-Page 3

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. SOIC - 2.65 mm max heightDW 16 SMALL OUTLINE INTEGRATED CIRCUIT7.5 x 10.3, 1.27 mm pitch 4224780/A

www.ti.com PACKAGE OUTLINE C TYP10.63 9.97

2.65 MAX

14X 1.27 16X 0.51 0.31 8.89 TYP0.33 0.10 0 - 8 0.3 0.1 (1.4) 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 10.5 10.1 B NOTE 4 7.6 7.4 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. 1 16

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

(9.3) 14X (1.27) R0.05 TYP 16X (2) 16X (0.6) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:7X SYMM 8 9 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN R0.05 TYP 16X (2) 16X (0.6) 14X (1.27) (9.3) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X SYMM SYMM 8 9

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Summary

QUAD DIFFERENTIAL PECL DRIVERS REVISED JANUARY 2008

Description