TB423 INTERSIL | Alldatasheet

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. Using the EL7562 Demo Board The EL7562 is a Buck (Step Down) DC:DC controller with integrated synchronous MOSFETs in a 16-pin QSOP package. With very few external components, a 2A step-down DC:DC converter can be very easily built, resulting in saved board space (0.5in2), minimal design effort, and improved design time. There are 2 demo boards, one for nominal 5V input and another for 3.3V input. This document outlines the design consideration and lists the bill of materials and the layout. Please also refer to the advanced data sheet of EL7562 for detailed applications of the features. EL7562 Demo Board Circuit Schematic for VIN = 5V Application EL7562 SGND COSC VDD PGND PGND VIN VIN EN PGND VREF FB VDRV LX LX VHI PGND VO VIN VO 0.985 EL7562 Demo Board Bill of Material VIN = 5V, VOUT = 3.3V REFERENCE DESIGNATION VALUE MANUFACTURER MANUFACTURER’S PHONE NUMBER PART NUMBER 100µF Sprague 207-324-4140 293D107X0010D2 C2, C3, C5, C6 0.1µF, 0603 Any 270pF, 5%, 0603 Any 100µF Sprague 207-324-4140 293D107X0010D2 4.7µH Coilcraft 847-639-6400 D01813472HC 1kΩ, 0603 Any 2370Ω, 0603 Any 39Ω, 0603 Any Technical Brief June 20, 2002 NOT RECOMMENDED FOR NEW DESIGNS SEE EL7532

EL7562 Demo Board Circuit Schematic for VIN = 3.3V Application SGND COSC VDD PGND PGND VIN VIN EN PGND VREF FB VDRV LX LX VHI PGND VO (2.5V, 2A) VIN (3V-3.6V) 0.1µF 270pF 39Ω 100µF 0.1µF 0.1µF 0.1µF 4.7µF 100µF 1.54kΩ 1kΩ 0.1µF 0.1µF VO 0.975 EL7562 Demo Board Bill of Material VIN = 3.3V, VOUT = 2.5V REFERENCE DESIGNATION VALUE MANUFACTURER MANUFACTURER’S PHONE NUMBER PART NUMBER 100µF Sprague 207-324-4140 293D107X0010D2 C2, C3, C5, C6, C8, C9 0.1µF, 0603 Any 270pF, 5%, 0603 Any 100µF Sprague 207-324-4140 293D107X0010D2 4.7µH Coilcraft 847-639-6400 D01813472HC 1kΩ, 0603 Any 1.54kΩ, 0603 Any 39Ω, 0603 Any D2, D3/4 Bat54S Vishay Telefunken 402-563-6863 Bat54S Technical Brief 423

Choosing the Component Values The following requirements are specified for a DC:DC converter:

  • Input voltage range: VIN = 4.5V-5.5V
  • Output voltage: VO = 3.3V
  • Max output voltage ripple: ∆VO = 50mV
  • Output max current: IO = 2A The following steps briefly outline the steps to choose components. 1. Choose the feedback resister divider. The output voltage is decided by: 2. Choose the converter switching frequency FS. FS, inductor L1, output capacitor C7, and EL7562’s switching loss are closely related. many iterations (or thermal measurements) may be required before a final value can be decided. Please refer to the EL7562 data sheet for the FS vs COSC curve. 3. Inductor L1. The EL7562 is internally ramp-compensated. For optimal operation, the inductor current ripple should be less than 0.6A. If ∆IL = 0.5A, then: where: Choosing L1 = 4.7µH yields ∆ILMAX = 0.56A. L1 should also be able to handle DC current of 2A and peak current of 2.3A at temperature range. 4. Output capacitor C7. ∆VO and ∆IL normally decide C7 value. ∆VO requires ESR of C7 be less than: Double-check the RMS current requirement of the output capacitor: which is 0.16A. For a capacitor or combination of capacitors with 89mΩ parallel ESR, it is more than enough to handle this current. 5. Input capacitors C1 and C2. If all the AC current is handled by the input capacitors its RMS current is calculated as: This gives almost 0.99A when D = DMAX. Therefore a cap with 0.99A current handling capability should be chosen. However, in case some other capacitor is sharing current with it, this current requirement can be reduced. Layout Considerations The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground ( ) should be separated to ensure that the high pulse current in the Power Ground never interferes with the sensitive signals connected to Signal Ground. They should only be connected at one point (normally at the negative side of either the input or output capacitor.) The trace connected to pin 14 (FB) is the most sensitive trace. It needs to be as short as possible and in a “quiet” place, preferably between the PGND and SGND traces. In addition, the bypass capacitor C3 should be as close to pins 1 and 3 as possible. The heat of the chip is mainly dissipated through the PGND pins. Maximizing the copper area around these pins is preferable. In addition, a solid ground plane is always helpful for the EMI performance. VOUT 0.985 For VIN = 5V VOUT 0.975 For VIN = 3.3V L VO ∆IL FS D VO VIN ESR ∆VO ∆ILMAX 89mΩ ∆IC7 ∆ILMAX IIN,rms D D)] IO Technical Brief 423