TB3R1 TI | Alldatasheet

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(TOP VIEW) TB3R1, TB3R2 SLLS587C – NOVEMBER 2003– REVISED JANUARY 2008 QUADDIFFERENTIALPECLRECEIVERS Check for Samples: TB3R1, TB3R2 The power-down loading characteristics of the1FEATURES receiver input circuit are approximately 8 kΩ relative• Low-Voltage Functional Replacements for the to the power supplies; hence they do not load theAgere BRF1A, BRF2A, BRS2A, and BRS2B transmission line when the circuit is powered down.

  • Pin-Equivalent to General Trade 26LS32 The package for these differential line receivers is theDevices 16-pin SOIC (D) package.
  • High-Input Impedance Approximately 8 kΩ The enable inputs of this device include internal• 3.5-ns Maximum Propagation Delay pullup resistors of approximately 40 kΩ that are
  • TB3R1 Provides 50-mV Hysteresis connected to VCC to ensure a logical high level input if the inputs are open circuited.• TB3R2 With -125-mV Threshold Offset for Preferred State Output PIN ASSIGNMENTS• -0.5-V to 5.2-V Common Mode Range
  • Single 3.3 V ±10% Supply
  • Slew Rate Limited (0.5 ns min 80% to 20%)
  • TB3R2 Output Defaults to Logic 1 When Inputs Left Open or Shorted to VCC or GND
  • ESD Protection HBM > 3 kV, CDM > 2 kV
  • Operating Temperature Range: -40°C to 85°C
  • Available SOIC (D) Package

APPLICATIONS

  • Digital Data or Clock Transmission Over Balanced Lines FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels. The TB3R1 is a pin- and function-compatible replacement for the Agere Systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD protection. The TB3R2 is a pin- and function-compatible replacement for the Agere Systems BRS2A and Enable Truth TableBRS2B and incorporates a -125-mV receiver input E1 E2 CONDITIONoffset, preferred state output, 3-kV HBM and 2-kV 0 0 ActiveCDM ESD protection. The TB3R2 preferred state feature places the output in the high state when the 1 0 Active inputs are open, shorted to ground, or shorted to the 0 1 Disabled power supply. 1 1 Active PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TB3R1, TB3R2 SLLS587C – NOVEMBER 2003– REVISED JANUARY 2008 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

TB3R1D TB3R1 SOIC NiPdAu Production TB3R2D TB3R2 SOIC NiPdAu Production POWER DISSIPATION RATINGS THERMAL RESISTANCE, DERATINGCIRCUIT BOARD POWER RATING POWER RATINGPACKAGE JUNCTION-TO-AMBIENT FACTOR(1) MODEL TA≤ 25°C TA = 85°CWITH NO AIR FLOW TA≥ 25°C Low-K(1) 763 mW 131.1°C/W 7.6 mW/°C 305 mW D High-K(2) 1190 mW 84.1°C/W 11.9 mW/°C 475 mW Low-K(1) 831 mW 120.3°C/W 8.3 mW/°C 332 mW DW High-K(2) 1240 mW 80.8°C/W 12.4 mW/°C 494 mW (1) In accordance with the low-K thermal metric definitions of EIA/JESD51-3. (2) In accordance with the high-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICs PARAMETER PACKAGE VALUE UNIT D 47.5 °C/W θJB Junction-to-Board Thermal Resistance DW 53.7 °C/W D 44.2 °C/W θJC Junction-to-Case Thermal Resistance DW 47.1 °C/W ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Supply voltage, VCC 0 V to 6 V Magnitude of differential bus (input) voltage, |VAI - V|, |VBI - V|, |VCI - V|, |VDI - V| 6.5 V Human Body Model(2) All pins ±3 kV ESD Charged-Device Model(3) All pins ±2 kV Continuous power dissipation See Dissipation Rating Table Storage temperature, Tstg -65°C to 150°C (1) Stresses beyond those listed under„absolute maximum ratings”may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under„recommended operating conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (3) Tested in accordance with JEDEC Standard 22, Test Method C101.

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Product Folder Links: TB3R1 TB3R2

TB3R1, TB3R2 www.ti.com SLLS587C – NOVEMBER 2003– REVISED JANUARY 2008 RECOMMENDED OPERATING CONDITIONS MIN Nom MAX UNIT Supply voltage, VCC 3 3.3 3.6 V Bus pin input voltage, VAI, V, VBI, V, VCI, V, VDI, V -0.6(1) 5.3 V Magnitude of differential input voltage, |VAI - V|, |VBI - V|, |VCI - V|, |VDI - V| 0.1 5 V Operating free-air temperature, TA -40 85 °C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise noted. DEVICE ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Outputs disabled 34 mA ICC Supply current(1) Outputs enabled 32 mA (1) Current is dc power draw as measured through GND pin and does not include power delivered to load.

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted parameter test conditions min typ max unit VOL Output low voltage VCC = 3 V, IOL = 8 mA 0.4 V VOH Output high voltage VCC = 3 V, IOH = -400 µA 2.4 V VIL Low level enable input voltage(1) VCC = 3.6 V 0.8 V VIH High level enable input voltage(1) VCC = 3.6 V 2 V VIK Enable input clamp voltage VCC = 3 V, II = -5 mA -1(2) V TB3R1 100 mV VTH+ Positive-going differential input threshold voltage(1), (Vxl - V) x = A, B, C, or D TB3R2(3) -50 mV TB3R1 -100(2) mV VTH- Negative-going differential input threshold voltage(1), (Vxl - V) x = A, B, C, or D TB3R2(3) -200(2) mV VHYST Differential input threshold voltage hysteresis, (VTH+ - VTH_) TB3R1 50 mV IOZL VO = 0.4 V -20(2) µA Output off-state current, (High-Z) VCC = 3.6 V IOZH VO = 2.4 V 20 µA IOS Output short circuit current(4) VCC = 3.6 V -100(2) mA IIL Enable input low current VCC = 3.6 V, VIN = 0.4 V -400(2) µA Enable input high current VIN = 2.7 V 20 µA IIH VCC = 3.6 V Enable input reverse current VIN = 3.6 V 100 µA IIL Differential input low current VCC = 3.6 V, VIN = -1.2 V -2(2) mA IIH Differential input high current VCC= 3.6 V, VIN = 5.3 V 1 mA RO Output resistance 20 Ω (1) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment. (2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. (3) Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recomended that all unused positive inputs be tied to the positive power supply. No external series resistor is required.) (4) Test must be performed one lead at a time to prevent damage to the device. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TB3R1 TB3R2

(1) The propagation delay values with a 0 pF load are based on design and simulation. transmission driver devices are measured with the following output load circuits. Figure 6. Figure 7.

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Figure 8. Figure 9.

D, Low−K DW , Low−K D, High−K DW , High−K Thermal Impedance − C/W Air Flow − LFM /C0113JA(S) /C0043 /C0426/C0466/C0113JC/C0041/C0113CA /C0467/C0032/C0466/C0113JB/C0041/C0113BA /C0467/C0427 /C0466/C0113JC/C0041/C0113CA /C0041/C0113JB/C0041/C0113BA /C0467 TJ /C0043TA /C0041/C0466P D /C0032/C0113JA(S)/C0467 TJ /C0043TA /C0041/C0466P D /C0032/C0113JA/C0467 /C0525(V Ln /C0032ILn) /C0525/C0466V Sn /C0032ISn/C0467 TB3R1, TB3R2 SLLS587C – NOVEMBER 2003– REVISED JANUARY 2008 www.ti.com

APPLICATION INFORMATION

Power Dissipation Note that θJA is highly dependent on the PCB on in addition to the desired life expectancy. The standardized θJA values may not accurately represent the conditions under which the device isThere are two common approaches to estimating the used. This can be due to adjacent devices acting asinternal die junction temperature, TJ. In both of these heat sources or heat sinks, to nonuniform airflow, ormethods, the device internal power dissipation PD to the system PCB having significantly differentneeds to be calculated This is done by totaling the thermal characteristics than the standardized testsupply power(s) to arrive at the system power PCBs. The second method of system thermaldissispation: analysis is more accurate. This calculation uses the power dissipation and ambient temperature, along(1) with two device and two system-level parameters:and then subtracting the total power dissipation of the • θJC, the junction-to-case thermal resistance, inexternal load(s): degrees Celsius per watt

  • θJB, the junction-to-board thermal resistance, in(2) degrees Celsius per watt The first TJ calculation uses the power dissipation • θCA, the case-to-ambient thermal resistance, inand ambient temperature, along with one parameter: degrees Celsius per wattθJA, the junction-to-ambient thermal resistance, in • θBA, the board-to-ambient thermal resistance, indegrees Celsius per watt. degrees Celsius per watt. The product of PD and θJA is the junction temperature In this analysis, there are two parallel paths, onerise above the ambient temperature. Therefore: through the case (package) to the ambient, and (3) another through the device to the PCB to the ambient. The system-level junction-to-ambient thermal impedance, θJA(S), is the equivalent parallel impedance of the two parallel paths: (4) where (5) The device parameters θJC and θJB account for the internal structure of the device. The system-level parameters θCA and θBA take into account details of the PCB construction, adjacent electrical and mechanical components, and the environmental conditions including airflow. Finite element (FE), finite difference (FD), or computational fluid dynamics (CFD) programs can determine θCA and θBA. Details on using these programs are beyond the scope of this data sheet, but are available from the software manufacturers.Figure 10. Thermal Impedance vs Air Flow

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Product Folder Links: TB3R1 TB3R2

www.ti.com 14-Jul-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TB3R1D Last Time Buy Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R1 TB3R1D.B Last Time Buy Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R1 TB3R1D1G4 Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R1 TB3R1D1G4.B Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R1 TB3R1DR Last Time Buy Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R1 TB3R1DR.B Last Time Buy Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R1 TB3R2D Last Time Buy Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R2 TB3R2D.B Last Time Buy Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R2 TB3R2D1G4 Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R2 TB3R2D1G4.B Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R2 TB3R2DR Last Time Buy Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R2 TB3R2DR.B Last Time Buy Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM -40 to 85 TB3R2 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1

www.ti.com 14-Jul-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TB3R1DR SOIC D 16 2500 350.0 350.0 43.0 TB3R2DR SOIC D 16 2500 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TB3R1D D SOIC 16 40 505.46 6.76 3810 4 TB3R1D.B D SOIC 16 40 505.46 6.76 3810 4 TB3R1D1G4 D SOIC 16 40 505.46 6.76 3810 4 TB3R1D1G4.B D SOIC 16 40 505.46 6.76 3810 4 TB3R2D D SOIC 16 40 505.46 6.76 3810 4 TB3R2D.B D SOIC 16 40 505.46 6.76 3810 4 TB3R2D1G4 D SOIC 16 40 505.46 6.76 3810 4 TB3R2D1G4.B D SOIC 16 40 505.46 6.76 3810 4 Pack Materials-Page 3

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