TB32301

TB32301 TOSHIBA | Alldatasheet

Document overview

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Technical content

Features

Consumption current : 35 mA (typ.) (at reception) : 26 mA (typ.) (at transmission) Operating power supply voltage : 2.7 V to 3.3 V (operating temperature range: -20°C to 70°C) Ultra-compact package: 36-pin QON On-chip LNA On-chip VCO On-chip PA Block Diagram Weight: 0.08 g (typ.) Marking: TB32301AFL TENTATIVE VCCRX2 2022 D-DATA AF1 VCC RX2 AF2 GND RX3 2326 25 IF-IN1 GND RX2 IF-IN2 GND RX1 1 2 3 4 5 76 9 RSSI FLLC1 VCCRX2 FLLC2 BS TXIN STB CLK DATA MIX O UT1 MIX F IL VCCRFRX RF I N GNDRF1 GNDRF2 TXOUT VCCRFTX VCCRF VCC Syn3 VCC Syn2 LOOP FIL1 GND Syn2 GND Syn3 GND Syn1 LD REF CLK VCC Syn1 ×2 VCO1 PLL1 TX FilterDATA SET FM-DET RX LPF Tuning RSSI This product is sensitive to electrostatic discharge. When handling the product, ensure that the environment is protected against electrostatic discharge. Dec./5th/2002 1

Pin Functions (typical resistor and capacitor values) Pin No. Pin Name Function Equivalent Circuit

1 VCCSyn3 Power supply pin 

2 VCCSyn2 Power supply pin 

3 LOOPFIL1 External pin for loop filter

4 GNDSyn2 Ground pin 

5 GNDSyn3 Ground pin 

6 GNDSyn1 Ground pin 

7 LD PLL lock detector output pin

8 REFCLK Reference clock input pin for PLL, TX filter and IF

9 VCCSyn1 Power supply pin 

10 DATA Serial data input pin

11 CLK Serial clock input pin

12 STB Serial strobe input pin

13 TXIN Transmit signal input pin

500 Ω GND2 8 100 kΩ 1 kΩ 10 VCCsyn 1 kΩ Dec./5th/2002 2

Pin No. Pin Name Function Equivalent Circuit

14 BS Battery-saving pin

15, FLLC2 FLLC1 Auto-tuning pin. External capacitor determines the time constant of auto-tuning circuit.

16 VCCRX2 Power supply pin 

18 RSSI This pin drives out DC voltage according to the

RF input signal level.

19 DDATA Comparator output pin

20 AF1 Demodulation signal output pin

1 kΩ 100 Ω 45 kΩ 10 kΩ 500 Ω Receive LPF (next stage of demodulator) FSK detection filter IF input stage internal BPF Internal reference voltage FLL detector Internal filer for transmit data Dec./5th/2002 3

Pin No. Pin Name Function Equivalent Circuit

21 VCCRX1 Power supply pin 

22 AF2 Comparator input pin

23 GNDRX2

24 GNDRX1

Ground pin 

25 IFIN1

26 IFIN2

27 GNDRF3 Ground pin 

28 MIXOUT1 Mixer output pin

29 MIXFIL Mixer filter pin

30 VCCRF1 Power supply pin 

31 RFIN RF signal input pin

10 kΩ 10 kΩ 100 kΩ 1 MΩ 360 Ω 2.9 kΩ 360 Ω 450 Ω 28 2 kΩ 50 µA 4 kΩ 3 kΩ 2 kΩ Dec./5th/2002 4

Pin No. Pin Name Function Equivalent Circuit

32 GNDRF1

33 GNDRF2

Ground pin 

34 TXOUT RF signal output pin 

35 VCCRF2 Power supply pin 

36 VCCRF3 Power supply pin 

Note: The equivalent circuit diagrams above are intended as an aid for designing external circuits. They do not show the exact layout of the internal circuits. Dec./5th/2002 5

Power Supply Name Pin No. Ground Relevant Pin Name Pin No. Block Name VCCSyn3 1 GND Syn3 5 VCO Doubler VCCSyn2 2 GND Syn2 2 VCO1 VCCSyn1 9 GND Syn1 6 PLL, DATA SET VCCRX2 16 GND RX3 23 Tuning (FLL), RX-AMP, RX-LPF, DATA COMP, FM-DET VCCRX1 21 GND RX2 24 TX-FILTER, PA, RSSI, IF-AMP, (IF-BPF) VCCRFRX 30 GND RF1 GND RF2

33 LNA

PA, MIXER, LNA Supplementary: Pins as shown below are shorted together. (1) V CC RX TX (35 pin) − VCC Syn2 (2 pin) (2) V CC RF (36 pin) − VCC RFRX (30 pin) Dec./5th/2002 6

1. Serial data input timing chart

• Data to control the TB32301AFL is serially applied to pins CLK, DATA and STB.
• Data is loaded into shift registers with MSB first on the rising edge of the clock and latched on the rising edge of the STB signal. When the STB pin is high, the data stored in the shift register is retained even if clock is applied. When the STB pin is low, the data can be rewritten.
• Input timings of the CLK, DATA and STB are shown below. = 0.01 µs STB DATA CLK > = 0.02 µs = 0.02 µs > = 0.05 µs > = 0.1 µs > = 0.02 µs > > = 0.02 µs 2. Serial data control contents The TB32301F has five types of control contents. These types are determined by serial input 5-bit register address (group code). The control contents consist of PLL main counter setting, PLL reference counter setting, auto-tuning reference counter setting, transmit power amplifier gain setting and system control setting. These settings are controlled independently one another.

2.1 Register address setting table (group code)

GC4 GC3 GC2 GC1 GC0 Control Contents 0 0 0 0 0 PLL main counter setting 0 0 0 0 1 PLL reference counter setting 0 0 0 1 0 Auto-tuning reference counter setting 0 0 0 1 1 Transmit power amplifier gain setting 0 0 1 0 0 System control register setting

2.2 PLL main counter setting

• The PLL main counter employs a swallow counter.
• It consists of 6-bit swallow counter, 9-bit programmable counter and 1/64, 1/65 2-modulus prescaler.
• The divide factor can be set in the range 4032 to 32767 by sending any data to the swallow counter and the programmable counter. MSB 1 0 1 0 0 0 0 0 0 N8 N7 N6 N5 N4 N3 N2 N1 N0 A5 A4 A3 A2 A1 A0 0 Group code Programmable counter: N Swallow counter: A (Divide factor) = 64N + A 4032 < = (Divide factor) < = 32767 Dec./5th/2002 7

2.3 PLL reference counter setting

• The PLL reference counter generates phase comparison frequency0.
• It consists of 9-bit reference counter. The divide factor can be set in the range 4 to 511 by sending any data to the reference counter. MSB 1 0 1 0 0 0 0 0 1 R8 R7 R6 R5 R4 R3 R2 R1 R0 0 0 0 0 0 0 0 Group code Auto-tuning counter: F (Divide factor) = R < = (Divide factor) < = 511

2.4 Auto-tuning reference counter setting

• The TB32301AFL has an automatic tuning system to correct the fluctuation of center frequency in FM detector, which is caused by, for example, temperature change. To generate a reference clock to correct the fluctuation, set the divide factor of auto-tuning reference counter to the value to obtain 200-kHz frequency, according to external reference clock frequency.
• The auto-tuning reference counter consists of 8 bits.
• The divide factor can be set in the range 6 to 255 by sending any data to the reference counter. (Divide factor) = F < = (Divide factor) < = 255 MSB 1 0 1 0 0 0 0 1 0 F7 F6 F5 F4 F3 F2 F1 F0 0 0 0 0 0 0 0 0 Group code Auto-tuning counter: F Internal control bits (always 0) (Note) Note Internal control bits are used to control the PLL. Please clear the bits. Otherwise, the PLL may not operate properly. Dec./5th/2002 8

2.5 Transmit power amplifier setting

Applying data serially to pins CLK, DATA and STB changes the gain of the transmit power amplifier. The power control counter consists of 5 bits. MSB 1 0 1 0 0 0 0 1 1 P4 P3 P2 P1 P0 0 0 0 0 0 0 0 0 0 0 0 Group code Power control counter: P Dec./5th/2002 9

2.6 System control register setting

In the system control register, applying data serially to pins CLK, DATA and STB sets the optional functions as described below. MSB 1 0 1 0 0 0 1 0 0 CP CP 1 0 MO D PD PD PD (M1) (M2) (M3) (M4) 0 0 0 0 DC DC Group code Charge pump current setting Transmit modulation control Battery-saving (power-down) control Transmit modulation control (Note) Comparator control Note: Please clear the bits.

• PLL charge pump current setting (CP1 and CP2 bits: 2.4 GHz) The TB32301AFL contains a constant current charge pump circuit. The output current of the circuit can be selected by setting the CP1 and CP2 bits. CP2 CP1 Charge Pump Current 0 0 4 mA 0 1 2 mA 1 0 1 mA
• Transmit data timing setting (MOD bit) Clearing the MOD bit makes the VCO circuit oscillate at the center frequency, which is controlled by the PLL. The circuit is not controlled by received data. MOD Transmit Data Timing

0 Modulator OFF

1 Modulator ON

• Battery-saving (power-down) mode setting (PD1, PD2 and PD3 bits) Setting the PD1, PD2 and PD3 bits controls the circuits in the reception and transmission blocks. The settings of the external BS control pin (14 pin) and the control bits are shown in the table below. BS Control Bits Reception Block Transmission Block Common Block PD3 PD2 PD1 LNA MIX IF-AMP FM-DET RX-LPF PA TX-LPF PLL, VCO Auto tuning L * * * OFF OFF OFF OFF OFF OFF OFF OFF OFF H 1 1 1 OFF OFF OFF OFF OFF OFF OFF OFF OFF H 1 0 0 OFF OFF OFF OFF OFF OFF OFF ON ON H 1 0 1 OFF OFF OFF OFF OFF ON ON ON ON H 0 0 1 OFF OFF OFF OFF OFF OFF ON ON ON H 0 0 0 ON ON ON ON ON OFF OFF ON ON H 0 1 1 OFF OFF OFF OFF OFF OFF OFF OFF ON
• Transmit modulation control bits (M1 to M4 bits) M1 to M4 bits are cleared for normal operation, however, M2 to M4 bits can be set to high to control the transmit modulation as shown below. Dec./5th/2002 10 M1 M2 M3 M4 Transmit Modulation 0 0 0 0 Normal modulation 0 1 1 1 Normal modulation × 16/8

• Rise time constant setting of comparator reference level (D1 and D2 bits) The rise time constant of data comparator reference level is determined by an external capacitance and an internal resistance. The internal resistance can be selected by applying data serially to pins CLK, DATA and STB. (Rise time constant) = (External capacitance: C) × (Internal resistance: R) DC2 DC1 Internal Resistance: R 0 0 10 kΩ 0 1 10 kΩ 1 0 100 kΩ 1 1 1000 kΩ 3. Image canceller mixer in reception block The TB32301AFL contains an image canceller mixer as the first stage of the reception block. The image canceller mixer is designed for upper local, therefore, please set the local signal frequency to f0 (desired reception frequency) + 11 MHz (IF frequency). 4. Lock detector function (LD pin: 7 pin) The TB32301AFL incorporates VCO lock detector function. When a phase error is detected in the phase comparator, 0 is driven out from the LD pin. When the VCO is locked or all the circuits are OFF, 1 is driven out from the pin. 5. VCO modulation polarity and demodulation data polarity
• VCO modulation polarity Transmit Data VCO Frequency Deviation

1 Positive (+) polarity

0 Negative (−) polarity

• Demodulation data polarity The polarity of the data, which is demodulated by the FM detector and the data comparator, is the same as that of transmit data. At Transmission At Reception Transmit Data FM Detector Data Comparator Output

1 Positive (+) polarity 1

0 Negative (−) polarity 0

Dec./5th/2002 11

Electrical Characteristics

Characteristics Symbol Rating Unit Power supply voltage VCC_A, VCC_D 3.6 V Power dissipation PD 530 mW Input pin voltage CLK, DATA, STB, BS, LD,TXIN 3.6 V Storage temperature range Tstg −50 to 150 °C Note 1: Maximum ratings are a set of specified parameter values which must not be exceeded during operation, even for an instant. Operating Ratings Characteristics Symbol Test Circuit Test Condition Rating Unit Operating voltage Vopr1 － Ta = 25°C, ground reference 2.7 to 3.3 V Operating temperature Topr1 － -20 to 70 °C Note 2: These ratings specify the ranges within which the device can operate its basic functions, even when fluctuations in its electrical characteristics occur. (Unless otherwise specified, Ta = 25°C, VCC = 3.0 V, f = 2450 MHz, Bit Rate = 100kHz, PA bit setting = 21, Dev = ± 160 kHz) Power Supply Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit Current consumption 1 at no signal ICC1 1 At reception BS = H, PD1 = 0, PD2 = 0, PD3 = 0 (Note 3) 28.0 35.1 42.0 mA Current consumption 2 at no signal ICC2 1 At transmission BS = H, PD1 = 1, PD2 = 0, PD3 = 1 (Note 3) 19 25.6 42 mA Supply current at no signal ICCQ1 1 In battery-saving mode BS = L, PD1 = 1, PD2 = 1 PD3 = 1 (Note 3)  0 10 µA High-level input voltage VIH － CLK, DATA, STB, BS, TXIN VCC ×

0.8 VCC VCC +

0.2 V Low-level input voltage VIL － CLK, DATA, STB, BS, TXIN −0.2 0 VCC × 0.2 V Note 3: Please refer to Section 2.6 “System control register setting”. Integrated Characteristics Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit Minimum input level VIN(min) 1 S/N = 20dB - 20.4 − dBµV Demodulation output level Vod － Vin (LNA) = 70dBµV − 450 − mVp-p Dec./5th/2002 12

(Unless otherwise specified, Ta = 25°C, VCC = 3.0 V, f = 2450 MHz, Bit Rate = 100kHz, PA = 21 setting, Dev = ± 160 kHz) LNA and Mixer Blocks Mixer image rejection ratio IRR 1 20 33  dB Output impedance R-OUT (MIX) －  470  Ω Output capacitance C-OUT (MIX) －  2  pF Operating frequency range (LNA and mixer) Fopr (LNA + MIX) 1 2400  2500 MHz Intercept point 1 output (LNA and mixer) OIP3-1 (LNA + MIX) － f1 (UD1) = 2453 MHz, UD1: No modulation f2 (UD2) = 2456 MHz, UD2: No modulation  85  dBµV IF Amplifier, DET and RX-LPF Blocks RSSI output voltage 1 V (RSSI-1) 1 Vin (IF) = 41dBµV, No modulation 0.36 0.54 0.72 V RSSI output voltage 2 V (RSSI-2) 1 Vin (IF) = 91dBµV, No modulation (1.25) (1.75) (2.25) V IF amplifier input impedance R-IN (IF) －  720  Ω IF amplifier input capacitance C-IN (IF) －  2  pF Comparator Duty ratio COMP (duty) 1 Open-drain output Internal time constant setting 1 (10 kΩ) 40 50 60 % High-level leakage current I (COMP-LEAK) 1 Open-drain output  0 5 µA Output ON resistance R (COMP-L) － IL = 100 µA  1  kΩ PLL Block Lock-up time t-lock 1 Phase comparison frequency: 500 kHz Charge pump output current = 4 mA  150  µs Reference clock operating frequency range fxin 1 4  20 MHz Reference clock input level range vxin 1 92 100 112 dBµV Clock (serial data) input frequency fclk 1   20 MHz Charge pump output current 1 Icp (1) 1 Vcp = 1/2VCC 350 500 650 µA Charge pump output current 2 Icp (2) 1 Vcp = 1/2VCC 0.7 1 1.3 mA Charge pump output current 3 Icp (3) 1 Vcp = 1/2VCC 1.4 2 2.6 mA Charge pump output current 4 Icp (4) 1 Vcp = 1/2VCC 2.8 4 5.2 mA LD OFF leakage current LD-off-LEAK 1 Open-drain output  0 5 µA LD ON resistance R(LD-on) 1 Open-drain output  1  kΩ VCO Block VCO Oscillation frequency range (× 2) f (VCO) 1 2400  2500 MHz VCO gain (× 2) Kv －  120  MHz/V pn1 － @500 kHz  107  dBc/Hz VCO phase noise (× 2) pn2 － @2 MHz  119  dBc/Hz Dec./5th/2002 13

(Unless otherwise specified, Ta = 25°C, VCC = 3.0 V, f = 2450 MHz, Bit Rate = 100kHz, PA = 21 setting, Dev = ± 160 kHz) Transmission Block Tx data input level Vtx － VCC × 0.2 Ｖ Local leakage spurious SPRlo 1 Test frequency: 1.225 GHz  −30 −20 dBm Maximum frequency deviation dev (tx) 1 On loop, fBB=100kHz (CW) (140) (190) (230) KHz PA Block Nominal output signal level PA-OUT (nom.) 1 DATA21 set for PA output (−9) (−3)  dBm Minimum output signal level PA-OUT (min.) 1 DATA3 set for PA output  (−30) (−25) dBm Output impedance Z-OUT (PA) 1  50  Ω Dec./5th/2002 14

C31 4.3 nF C32 10 nF R31 2.7 kΩ R71 10 kΩ C81 100 pF C91 10 pF C92 100 pF VCC Syn3 VCC Syn2 LOOP FIL1 GND Syn2 GND Syn3 GND Syn1 LD REF CLK VCC Syn1 RSSI FLLC1 VCC RX3 FLLC2 BS TXIN STB CLK DATA DATA SET R101 100 kΩ R101 100 kΩ R101 100 kΩ R101 100 kΩ R71 10 kΩ C162 1 µF 0.01 µFC161 C15A 0.01 µF C181 1000 pF C171 0.01 µF GND RX1 IF-IN2 IF-IN1 GND RX2 GND RX3 AF2 VCC RX2 AF1 D-DATA 2122 1920 ×2 VCO1 PLL1 TX LPF FM-DET RX LPF Tuning (FLL) RSSI IF BPF C271 1000 pF R281 200 Ω MIX OUT MIX F L VCCRFRX RF I N GNDRF1 GNDRF2 TXOUT VCCRFTX VCCRFC362 10 pF C361 1000 pF C351 10 pF C352 1000 pF C302 1000 pF C301 10 pF VCCRFRX C29A 0.01 µF V V V (RSSI-1) V (RSSI-2) V C342 10 pF C343 1000 pF L341 4.7 nH 31 L311 4. 7 n H C311 22 pF C341 10 pF SG fin = 13 MHz, 100 mVrms A VCC = 3.0 V R191 10 kΩ BER VIN (min) VOD C211 1000 pF C212 0.1 µF C202 300 pF C201 0.1 µF SG fin = 2450 MHz PA - OUT R201 1 kΩ ICC1, I CC2, ICCQ (1) Detailed test condition of minimum input level in the integrated characteristics Detector LPF: C202 = 300 pF, R201 = 1 kΩ and fT = 530 kHz • Total bits: 1.6 Mbits Data comparator output: Monitors using a probe. Input/output: LNA input, data comparator output Transmission modulation (DEV): 157.5 kHz Data: PRBS9 (1MBPS) BT = 0.5 gaussian filter IF filter used. (Note) Tested using a Toshiba’s mounting board Note: Ceramic filter manufacturer and product no. SFSCB11M0WF manufactured by Murata Manufacturing Co., Ltd. (2) Detailed test condition in the transmission block Tested using a Toshiba’s mounting board (3) Detailed test condition of output level in the PA block Tested using a Toshiba’s mounting board Dec./5th/2002 15

Weight: 0.08 g (typ.) Dec./5th/2002 16

Dec./5th/2002 17 rs. RESTRICTIONS ON PRODUCT USE 000707EBA TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It i s t he r esponsibility of th e buy er, w hen ut ilizing T OSHIBA produ cts, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set f orth in the m ost rec ent TOSHIBA products s pecifications. Als o, please ke ep in mind th e pr ecautions an d conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. The TO SHIBA products l isted in thi s do cument ar e inte nded for u sage in g eneral electronics app lications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). T hese T OSHIBA prod ucts are ne ither int ended n or w arranted for u sage i n e quipment th at re quires extraordinarily high quality and/or reliability or a malfunction or fa ilure of w hich may cause loss of human life or bodily inj ury (“Unintended U sage”). Unintended U sage i nclude at omic energy control i nstruments, a irplane or spaceship i nstruments, tra nsportation in struments, traf fic signal in struments, c ombustion control in struments, medical i nstruments, al l ty pes of safety dev ices, et c.. U nintended U sage of T OSHIBA produ cts l isted i n th is document shall be made at the customer’s own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The informa tion con tained h erein i s pre sented o nly as a guid e for the applications of our prod ucts. N o responsibility i s assumed by TOSHIBA C ORPORATION for any infringements of int ellectual pr operty or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or othe The information contained herein is subject to change without notice.