TB2118F | DigiCamel IC Datasheet

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TB2118F TOSHIBA | Alldatasheet

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TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC HIGH SPEED PLL FOR DTS TB2118F is a high-speed phase-locked loop (PLL) LSI for car audio tuners with a built-in charge pump circuit. All functions are controlled through serial bus lines. The device is used to configure high-performance digital tuning systems. TAG REG FEATURES TES @ Built-in high-speed program divider with built-in prescalers. FM : 30~150MHz (Pulse swallowing method) - SS0P24-P-300-1.00 AM : 1~40MHz — (Pulse swallowing method) Weight : 0.31 (Typ.) @ Phase comparator outputs are constant current output for both FM and AM. Current values can be switched using serial data. In high-speed mode for large current output seek, the lockup time between FM band edges can be set to approx. 500 us by selecting an appropriate VT range and low-pass filter constant. @ RDS supported N-value data and charge pump output current data (total of 18-bits) can be selected using two registers. @ Built-in low-pass filter op-amps for FM and AM. © Built-in 20-bit binary counter for counting IF frequency. @ Crystal oscillator can be used 10.25 MHz or 10.35 MHz. @ Two output ports (open-collector output) and two |/O ports (CMOS) supported. @ Package is SSOP 24 pin. (Note) Pins 1 and 24 are susceptible to surge. Take care when handling. 980910EBA1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. sire products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual Property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual Property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1999-10-13 1/19

Xo Ih 2a x; osc 2 23— A-GND ce ip 229 REG. Din M4 21h vec ck Ws 208 am cP Dour Be i) a sR 87 18 FM CP

04 Ms 17h o-cNb

10-2 Ho 16M AMyco. out Bro 15 FMyco our-2 Bu 148 Vop Vop2 12 139M IFC BLOCK DIAGRAM POWER SUPPLY VOLTAGE Vr osc Q) <q] Xo G) OSC CIRCUIT PHASE am cP [| REFERENCE COUNTER COMPARATOR aD 0) x @ 5 $16 Fuvco @) © prescaer abit Tea SWALLOW COUNTER AMyco (6 la 12-bit PROGRAMMABLE COUNTER REG. al : <o—- > oto Vv . ce @® poccsren Monn nn nn nnnnnn nnd ob anna a9 { Treaster: Po on® sera | Gerostena Fe | aor snr acoisren | ck G) GD (18)

1 FM cP

1/0 PORT OUTPUT PORT ‘SWITCH Dour ©) Yoo Vee way ~ SR 110-1 1/0-2 OUT-1 OUT-2 Vpp2~—- Vpp_D-GND Vcc A-GND. 1999-10-13 2/19

en | SYMBOL | PIN NAME | FUNCTION AND OPERATION REMARKS. x F . xn O ° © Serial data input : osc Crystal Setting FO and F1 bits selects the CIRCUIT Oscillator Pins frequency of the crystal oscillator to xour O be connected. x osc © Gi Copal Station requengy. 2 | osc |Oscillator ' quency. Output Pin 0 = output OFF p 1 = output ON © Serial data input: When AM/FM bit = “0” FMyco is Rain selected. 15 |FMyco FM Band Local @ Input signal is directly transferred to Signal Input — the swallow counter. @ Input frequency :30 to 150 MHz © Divided frequency :528 to 65.535 @ Serial data input: When AM/FM bit = “1” AMyco is selected. AMyco eM Band ‘eral © When MODE = “1” AM band is "9 pu selected (by pulse swallow). Input frequency :1.0 to 40 MHz Divided frequency :528 to 65.535 @ Input frequency : 0.1 to 15 MHz Rae IFC IF Signal Input © The selected signal is input to a 20-bit general-purpose counter via a gate circuit. Chip Enable Serial interface pins. ; 3 cE Input © Data used for controlling TB2118F are exchanged between controllers. ceck/D IN © Control data are input via Djy in sync. LS cK Clock Input with clock input via CK. Control data input start/stop is specified using CE. Pour Serial Data © General-purpose counter data are Input output in sync. with clock input via CK i from Dout- Dout Serial Data © The CK/CE/Djn pin is Schmitt trigger Output in put. 1999-10-13 3/19

ee | SYMBOL | PIN NAME | FUNCTION AND OPERATION REMARKS. . © Selects register 1 or 2.

7 SR pear Pin “L" = register 1 output

. “H" = register 2 output js |ivos @ Input or output is switched in units of V , - DD 1/0 Ports bits by serial data input. _—_——_ @ CMOS input/CMOS output 1/0-2 © At power on, set to input ports. +#— Output Ports © Open collector output ports. @ Single power supply for reference frequency block © Vpp2 = 3.0 to 5.5V voo @ Vpp2 (note that Vpp= Vpp2) ep © Due to the crystal high-frequency vo02@ *o receive interference characteristic, we pee oh recommend an Rp setting so that Vpp2 = 3.5V. | 4 | vo | cmos Power |* Power pins for digital block (digital Pins circuits). D-GND ®@ Vpp = 4.5 to 5.5V, D-GND = 0V Vv i - L 21 | vec | Bipolar Power © Power pins for analog block (eg, op: Pins amps, constant-voltage supply) © Vcc = 8 to 10V, A-GND = OV Ripple filter connecting pin for internal Ripple Filter constant voltage supply. Insert about Connecting Pin. | 10F (as high as possible) between this pin and A-GND. @ Input from the plus terminal of the . op-amp is internally biased to 2.5V. > aD 6) 3 19 | VT Tuning Voltage |@ External crystal for phase correction is co required because low gain is set by 3 ie high through rate. ~ 1999-10-13 4/19

ig [oweor] aweane [acto me onaanon | Charge pump output for AM © Serial data input : When AM/FM = “1” error output from the phase comparator is output as constant current. Yop AM Charge frer>fsig : Scurrent output | AM CP Pump Output freF = fsig: high impedance ® frer<fsig : @current output 5 [| © Serial data : eLje > | Output current can be switched using e[]4 O CRO and CR1 bits. rae | © Normally (when using AM op-amp), set | | € é © the OP SEL bit to “1”. a Charge pump output for FM © Serial data input : When AM/FM = “0” error output from the phase comparator is output <I as constant current. Inverter amp frer>fsig : Gcurrent output FM CP Pumnp Ourput frer = fs1G: high impedance ©) frer<fsig : @current output © Serial data : Output current can be switched using CRO and CR1 bits. @ Normally (when using FM op-amp), set the OP SEL bit to “0”. 1999-10-13 5/19

Configuration of Control Data (Serial data input/output) 1) Data input mode (Valid data length changes according to the address.) (Note) (Address) 5}3]s 3/8 slelele|2]z eels ae afalala]5/s BPEL EL Bolo =|- wooo efefelele ele eel EERE FEE a §£ input mode (1) —__ - fale elels}s 1285 5] ]2 int mode (82) A HERE REE ElEVS|olo ee ut (Note) @ TEST bit VALID DATA [pa [a] a forme] nen [a fo/#f[ifif @ | 40 bits Processes power on (initialization). When “0” is set in bits marked with #, data are loaded to register 1; when “1” is set, to register 2. (Note) @ Either “0” or “1” can be set in bits marked with *. @ TS1 and TS2 are pins for internal testing. At power on, be sure to clear to “0” (data set). 1999-10-13 6/19

3) Serial data transfer formats @ Data input mode (At input, Doyt becomes high impedance.) Lod End 05 ps min, 18 min 4058 min 05 us mine nce ee Se 05 ps min i cK t a H ECan be omitted H 05 ys min. i own KX XX XeoXarKaeX as _KooXo1 X02 X03 KoeXos_ Dae X037KoseXoa9XoacX * Can be omitted Input address i 0.1 ys max. ei data (Note) © When power for TB2118F is fully on, input data after 100 ms or more. © Until data input starts, set the CE pin to GND to avoid any noise input. @ Data output mode End ce a---- : tee Can be omitted i i Hl Can be omitted Output address; i Fo 0.1 ps max. (Low level) oe Po gh eee ae Dour (High impedance) 7 NpoorXazX oa Koa Xos 1711 baaXoxXoz2Xo2sXore/ ii (High impedance) Internal registers preset | | (Note) @ Normally, DouT is high impedance. © During data output, data output mode is terminated by changing CE = H to L. 1999-10-13 8/19

Setting Reference Frequency-Related (reference divider block) Items 1) Setting crystal oscillator (OSC) With TB2118F, the two-frequency oscillator shown below can be driven by self-oscillation. FO BIT F1 BIT INPUT FREQUENCY [ot 10.35 me (Note) At power on, F0/F1 = 0. @ Connection example osc our Xour Xin (Note) Use a crystal oscillator with Rs = 500 @ Q@) G2) and less and C, = 12 pF or less. } 2pF | 6 pF a Oh 2) Setting reference frequency (Rg, R1, R2) Es Oe pa fta1ftot -— {[ - | }o [| o [1 [ tokHe [ — | pi fo fa [| =~ [ gkte | potrtia{ — {[ = | i (Note) Do not select settings where __ is entered instead of frequency. 3) OSC output select (OSC) = oscillation frequency is output from the OSC OUT pin. O5¢ OUT PN [0 |_ Output OFF [1 | output on (Note) At power ON, OSC = 0. 1999-10-13 9/19

Setting Programmable Counter Block 1) Circuit configuration The programmable counter block consists of a 2-modulus prescaler, 4-bit swallow counter, and 12-bit programmable binary counter. PSC. 2-modulus 4-bit (P99 to Po3) “20 > s (am) PRS 12-bit (Poa to P15) I To phase (FM) comparator 2) Setting input pin/dividing mode (AM/FM, MODE) AM/FM | move | INPUT PIN |INPUT FREQUENCY] DIVIDED FREQUENCY DIVIDING MODE ; o | o [| FMvco 30~150 MHz By pulse swallow [ot aMyco [40 Me 52865.535 (16-bit) 3) Setting divided frequency (Pog to P45) @ By pulse swallow (in FW or SW mode), n =528 to 65.535 usB usp 20 ts 1999-10-13 10/19

Control of Phase Comparator and Charge Pumps The phase comparator compares the phase difference between the reference frequency signal (freF) and the programmable counter divisor output (fsjg) and outputs the result. The constant current driver block outputs phase error signals as a current. 1) Setting charge pumps and op-amps (OPSEL) The OPSEL bit is used to select a charge pump and an op-amp. OPSEL | CHARGE PUMP (CP) OUTPUT OP-AMP. AM CP OUTPUT | FM CP OUTPUT [0 [dorm [_fwamp | Wz | bo _| [+ p0aw A amp Hz = high impedance DO = tri-state output 2) Setting current value (CRO) @ AM/FM = “1” (AMjn input) @ AM/FM = “0” (FMix input) AM CP OUT output current FM CP OUT output current Ce 3) Connection example (The filter circuit is an example for reference. Check and design depending on the desired characteristics for your set.) 100 pF am cP out [ vr = Vr 0.047 pe 3.30 8 gl? cour @ ” 8200 pF 1999-10-13 11/19

Control of General-Purpose Counter Circuit The general-purpose counter is a 20-bit counter used to measure the intermediate frequency. This is used at auto tuning for detecting a radio station. Setting “1” in the START bit starts counting after counter reset. 1) Circuit configuration Coo to C19

2 OVER

a) > D 20-bit Overflow binary counter detection Reset detector ‘START Go Gy 2) Setting IF counter gate time/wait time (Gg, G1) | so | & | GATE TIME WAIT TIME po f{ of ims | 3.3~4.3 ms po [| 1 fT téms | 73~8.3 ms Patt [ 64ms | 3) Counter output data (Cgg to C19) Use se elslelelslslelslelelelclelele|2}elslele SIEISTEVS|S ISIS ISIS ISIS ISIS TO ISPS |S Jo |S pos 1999-10-13 12/19

4) Detecting counter operating status susy] COUNTER OPERATING STATUS over| COUNTER VALUE [0 Counting ended rs i EC (*) Setting the DOC bit to “1” enables constant output of BUSY state from the DouT pin. Note that at this time, the BUSY status is the inversion of the BUSY bit : BUSY status = 0 (counting) and BUSY status = 1 (counting ended). The DOC bit is set to “0” at power on. 5) Counter timing (when PLL data are updated and counting starts) ee es PLL data (OLD DATA) Y (NEW DATA) i Le : (*) Constant output from Gate ee | L_« Dour pin enabled {WAIT TIME GATE TIME E> kK 1999-10-13 13/19

Setting General-Purpose |/O Ports 1) Setting output ports (OUT-1, OUT-2) OUT1, 2 OUTPUT PORT STATUS | 0 [Driver off (high impedance) Driver on (Low level) 2) Setting |1/O control and |/O output ports (1/01, 1/02, 1/OC1, 10C2) 10C1, 2 1/O PORT SETTING 1/01, 2 | OUTPUT PORT STATUS | 0 [Input port (CMOS input) } oo | Low-level output | 1 [Output port (CMOS output) foi | High-level output (Note) Valid only when set to output port. @ At power on, |/O ports are set to input. 3) Reading |/O port data (1/01, 1/02 : output mode data) 1/01, 2 INPUT PORT STATUS [0 [Low-level input - [1 High-level input (Note) Valid only when set to input port. 7. Others 1) Control (DOC) of serial data output (DgyT) Dout OUTPUT STATUS REMARKS | 0 [Other than in output mode, high impedance. | ls

1 Outputs BUSY status of general-purpose counter (constant |0: Counting

output mode). 1: Counting ended @ At power on, DOC = 0. 1999-10-13 14/19

MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTICS SYMBOL RATING UNIT Power Supply Voltage (1) -0.3~6.0 Power Supply Voltage (2) | Vec | -03~110 |v Vpp Input Voltage -0.3~Vpp + 0.3 Vcc Input Voltage VIN (2 -0.3~Vcc + 03 Applied Voltage On Pins ©, 1, @ | Vceo [Power Dissipation ‘| Pp | 430+ mW | Operating Temperature -40~85 Storage Temperature -65~150 ELECTRICAL CHARACTERISTICS (unless otherwise specified, Ta = 25°C, Vcc = 8.5V, Vpp = 5V, Vpp2 = 3.5V, Vss = GND = 0V) SUPPLY VOLTAGE AND CURRENT (Vcc, Vpp, VpD2, A-GND, D-GND) TEST CHARACTERISTICS | SYMBOL TEST CONDITION a, | ve max UNIT CUIT [30] 85] 100] supply Veltoge., Ta = ~40~85°C [45[so[ 55] v Supply Voltage Voo2 Poet ast ss . eq = 10.25 Mz] Veg = 10 max Operating Power _ 5K — perating Power [inp | — |ta= 25° [Vpp =55V max [ — [200 [230] ma [ipa |__| Fwin = 150 MHz [Vpp2 = 55V max| — | 025] 1.0 CRYSTAL OSCILLATOR CIRCUIT (XtiIN, XTOUT) Crystal Oscillator fr Connect the crystal oscillator 10.25 | 10.35 | MHz Frequency to Xtin and XtouT- Oscillator Output Level OSCcO OSC pin | 100] 560] — [mVrms| TEST CIRCUIT 1 ost Monitor 2 i g 1999-10-13 15/19

OPERATING FREQUENCY RANGE (FMx, AMiy, AM/FM IF) TEST CHARACTERISTICS SYMBOL TEST CONDITION an. | ve. | UNIT CUIT - VIN = 0.2 Vp-p, sine wave FMvco Operating fem input, capacitive coupling, by 150 | MHz Frequency pulse swallow VIN = 0.2 Vp-p, sine wave AMvco Operating fam input, capacitive coupling, by 1.0 MHz Frequency pulse swallow - VIN = 0.2 Vp-p, sine wave IFC Operating fir | input, capacitive coupling, IFC 15 | MHz Frequency . pin INPUT RANGE (FMyco, AMyco, IFC) IFC Input Level IFC Vin | - | Input Frequency 0.1~15 MHz | o2| ~ | Yoo Input Frequency 30~120 MHz(*) Yop FMyco - 0.5 FMyco Input Level Vv V; Vp-p IN Input Frequency 120~150 MHz | o2| ~ | mart Input Frequency 1.0~15 MHz (*)| 0.113 Vop AMvco = 0.5 AMyco Input Level Vv Vv Vp-p IN Input Frequency 15~40 MHz | oz] ~ | an (*) Weekly code 9843~. SERIAL INTERFACE (CE, CK, Din, Dout, SR) V Input High Level VIH (1) CE, CK, Din, SR pins a | ~ | v00 | Vv voltage Vit [of = [45] Input High Level | MW (1 Vin =5V_ [=1.0 | — [+10 | pA Current me Vi=ov[-10[ — [+10 | carom Tm [| vu02v| 00 [30] ~ [ma Current - Output Off-leak Dour pin oro f _poveee [vo] = [ne] m OUTPUT PORTS (OUT-1, OUT-2) Low-level Output om [pare ec Output Off-leak Current lOFF (2) VOH = 10V -1.0 +1.0 | pA 1999-10-13 16/19

1/ OPORTS (1/O-1, 1/O-2) Input High Level | 11H (2 Vin = 5V [=1.0 | — [+10 | uA Current Le Viz OV [=10 | — [+10 | : Vi Input High Level VIH (2) [Yo] ~ | voo | Vv voltage vie [_o| = | 75] Output High Level oH (1 VoH = 4.0V [-5.0[-75] — | Current loi 3 Voi = 1.0V P35] 45] — | CHARGE PUMPS (AMCPoyt, FMCPouT) TEST TEST CHARACTERISTICS SYMBOL | cIR- Typ. | MAX.|} UNIT CuIT| CONDITION | cRo BIT} CR1 BIT Fw Charge Pump [Tormey | — loon pm © | 0 | #020|#025] #04] Output Current TOFM (2 [0 [1 _| #40] #50] #70) AM Charge Pump in [Oo [ 0 | £02] £03 40.45 DOAM pin mA Output Current loa (2 [1 [oJ s0al 205] 2075] OP-AMPS (V7) AM Op-amp Output Vin = Vop, Vout = 8.5V [10] 207 ~ To, Current Vin= GND, Voyr=0V —|=10 [-20 | — | FM Op-amp Output Vin = Vop. Vout = 8.5V | 50 | 90] —~ |. Curent Vin= 6ND,Vour=0V [=a |-30| — | woman [we [=] | = 1999-10-13 17/19

199.0 1000 pF wo ueo AM/FM IF Yoo Vee | { « Es = ips 5 6 pF lo.007 pro 0.047 yr aM FM oy 23) @ oD, , Vat wv, {6 Q5) i) (3) VV O OD) el abit 1 2

10.25 MHz_ swallow le modulasle—€P}

10.35 MHz Oscillation Counter} [Prescaler| 47 Rd

comparator Programable Counter 40 bit 20bit ft [| iy Xtout Tose cE Din CK Dout FSR 0-1 1/0-2. TOUT-1 TOuT-2 7 Vpp2 aoe our , re" oat 1999-10-13 18/19

SSOP24-P-300-1.00 Unit : mm 24 13 HHHHHHHAHHARH ae NN! = i 2 o| = 3] & 5 1 12 13.5MAX 13.0+0.2 a =8 z so =1 so wo =o) a 0.52540.2 Weight : 0.319 (Typ.) 1999-10-13 19/19

Product Information

TB2118F specifications and overview.

Summary

HIGH SPEED PLL FOR DTS

Description

HIGH SPEED PLL FOR DTS

Source title TB2118F Datasheet(PDF) - Toshiba Semiconductor

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