TB2110FN | DigiCamel IC Datasheet

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TB2110FN TOSHIBA | Alldatasheet

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TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC PLL FOR DTS The TB2110FN is a high-speed PLL LSI built in a 2 modulus prescaler that can operate with a 1.5V power supply. Each function is controlled via three serial bus lines, allowing you to configure a high-performance digital tuning system. > SMAI 9 sy NS aa FEATURES WSs @ Due to a Bi-CMOS structure, the 1.5 V power supply is stepped up and stabilized by a bipolar circuit to drive the CMOS section. Therefore, this chip is best suited for > SSOP24-P-300-0.65A digital tuning system in headphone stereos. Weight : 0.319 (Typ.) @ Built in a prescaler, This IC can operate with TV : 50~250 MHz and FM : 40~150 MHz (2 modulus type) for the FMjj input or at 0.5~40 MHz for the AMjy input (2 modulus type or directly divided). @ Comes with a 20 bit programmable counter, two parallel output phase comparators, crystal oscillator, reference counter, and a DC/DC converter control circuit. © The crystal oscillator (X’tal) used in this IC is a 75 kHz resonator. @ The reference frequency can be selected from seven frequencies available. (Ref = 1.0~25 kHz) @ A 20bit general-purpose counter is built in that can measure the IF and other frequencies. @ All device operations are controlled via three serial bus lines. © Operating voltage range : Vcc = 1.0~2.5V (Ta = -20~75°C) @ Package is SSOP24pin. 980910EBA2 © TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fall due to thei inherent electrical sensitivity and, vulnerability to physical stres. itis the responsibilty of the buyer, when utlizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing. your, designs, please ensure that TOSHIBA. products are, used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to the foreign exchange and foreign trade laws. © ‘he information contained herein is presented only as a guide for the applications, of our products. No_ responsibilty is assumed by, TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. e The information contained herein is subject to change without notice. 1999-03-05 1/18

(Note) This device is vulnerable to surge voltages. Take it into account when using this device in your system. TOO 99-03-05

z AM-IN C)} t> vec vo ANH & FMM & FML RESET STAND-BY [*—{ ) STAND-BY g 4bit SWALLOW COUNTER 1 | ge x0 oa na #8 TL aie }H mene commen Yr] her a CP ener are te DcDC cLoci one peaks. eS CPrcont ‘ADDRESS CONTROL Period () wO i >| wz LS d =e Lbaéd Orne OOOO OO zEged 29 8833 8 7999-03-05 3/18

[Pin No. SYMBOL PIN NAME FUNCTION REMARKS. Toma Connect a 75 kHz crystal XI . . F VoD XO Crystal oscillator pins | oscillator for the reference a frequency to these pins. 3 x! xo Serial data input/ Serial 1/0 port.

3 DATA out Use this pin to set the

put Yoo, Yoo divide ratio and divide 7 - . method, as well as transfer of | | CLOCK Clock signal input data to and from the 7 controller to control the DATA CLOCK, PERIOD PERIOD _ | Period signal input general-purpose counter and general-purpose |/O port.

6 OUT-1 This is an open-collector

7 OUT-2 General-purpose output port.

8 OUT-3 output port Use this port to output

9 OUT-4 control signals. Voo General-pur input This port accepts the data IN PORT . . al-purpose InPUut |+6 be fed to the output bit of P (OUT-5). nly, DC/DC converter This pin controls the DC/DC vec CONT control pin converter. . The Vpp power supply from Vpb CMOS section power | +46 DC/DC converter is pply applied to this pin. The device is placed in standby mode when a “L” is 20k STAND-BY | Standby input. The device is in active state when a “H” is input. General-purpose Use this pin for IF signal IF-AM (Pin 16) IF-FM (Pin 14) La | iFM counter input input on the FM side. O O

15 VREr2 Reference pin Use this pin as the reference S$

of the IF signal. vet O% re General-purpose Use this pin for IF signal (Pin 15) IF-AM 4 P : © ® counter input input on the AM side. GND [Bipolar section GND | —S— ——SSidP OCC 1999-03-05 4/18

foo] somo [rene [con [ras | | se | amin | AM/SW signal input Use this pin for AM/SW Farin 20) aarp ein 18) pin signal input. . Use this pin as the reference Ss 7 7 —— Vref

20 FM-IN FM/TV signal input Use this pin for FM/TV (Pin 19) ® @

pin signal input. supply This is a tri-state output of Vpp 22 DO1 Phase comparator the phase comparator. -

23 DO2 output DO1~DO2 are parallel je

outputs. [24 [| B-GND [MOS section GND COC OCS 1999-03-05 5/18

The TB2110FN has two pairs of 24 bit registers, so it can set data to a total of 48 bits to control each function. Each data in these registers are transferred to and from the controller through a serial port using three pins : DATA, CLOCK, and PERIOD. A total of 32 bits consisting of 8 bit address and 24 data bits can be handled in one serial transfer. Because all operations are controlled via register, this section describes mainly the function of 8 bit address and each register. The registers are configured in units of 24 bits, and are selected by an 8 bit address. The address mapping of each register is listed in the next page as “Register allocation.” PLL dividend number setting 16 Input Reference frequency setting 3 Re er 1 DOH | PLL input and mode setting 2 a Not used 3 Total 24 General-purpose counter control 7 Input Test bit 1 Re eer 2 D2H Output data 4

9 Not used 12

General-purpose counter numeric data 22 Ronin D1H Not used 2 i Total 24 Data in register D2 8 Output Lock detection data 2 Re ister 2 D3H Input data 1

9 Not used 13

The input data is latched into register 1 or register 2 at the falling edge of PERIOD to put each function to work. The output data that comes in parallel is latched into the output register at the 9th falling edge of CLOCK, and is serially output from the DATA pin. (Note)Transmit dummy data at least once before transferring regular data to initialize the device's internal circuits after power-on. 1999-03-05 6/18

i L i EDL ‘I: ER ME ENE EH I Le OME EER MH OGRE EER BBE HH OTR HE fhe EL ue ‘lel ue EE OME CER HE Tee EDEDE EEE EEE LO HERA EEE REE ob ec] OEP Ee EYER be HEE EOLA BREE) EERE fl: TTT G-03-05—- 78

PERIOD tall [2 ‘2 im ie al ety 9th falling edge cLock LU IL] LT] a I] * * 0 0 1 0 1 14 oata 67 wis, 72 210m Bbit address 2abit data © The serial transfer format consists of 8 bit address and 24 bit data as shown above. The addresses used here are DOH to D3H. O Crystal oscillator connecting pins (XI, XO) Connect a crystal oscillator and capacitors to these pins as shown in Figure 1 to generate the clock required for the device's internal operation. Use a 75 kHz crystal oscillator here. 19M awe nO : © xo ce Xtal cr C = 18pF Typ. (Note)Choose a crystal oscillator that has a small Cl value and good startup characteristics. Figure 1 1999-03-05 8/18

The programmable counter section consists of 1/4 + 1/2 prescalers, 2 modulus prescaler, and 4bit + 12bit programmable binary counters. 1. Setting the programmable counter section The programmable counter need to be set for the divisor (16 bits) and the dividing mode (2 bits). (1) Setting the dividing mode Use the FM and MODE bit to choose the input setting and the dividing mode (pulse swallow mode or direct dividing mode). Four mode are available as listed below. Choose the desired one according to the frequency bands used. TYPICAL INPUT FREQUENCY| INPUT Imove| Fw |move| DIVIDING MODE RECEIVING BAND RANGE DIVISOR | AM | 0 | 0 [Direct dividing mode Lw, MW O.5~10MH2 | vay [sw_[0 | 1_|Pulse swallow mode 3-40 MHz [| Pr |1 | 0 [1/4-pulse swallow made 49~150 MHz 1/8 pulse swallow mode 50=250 MHz [en _| (Note) ‘n’ denotes the set value. (2) Setting the divisor To determine the programmable counter's divisor, set binary data to the PO~P15 bits. @ For the pulse swallow mode (16 bits, SW, FM, and TV BAND) MSB LSB [p15]pr4]p13[P12]p1sfP1o[ pa [ps p7 [Pe] Ps [Pa] P32] Pi] Po] pis 50 Range of divisor set (pulse swallow mode) n = 210 H~FFFFH (528~65535) (Note) The actual divisor is 4 times the programmed number for the 1/4 +pulse swallow mode, and 8 times the programmed number for the 1/8 +pulse swallow mode. @ Direct divide method (12 bits) MsB LSB Range of divisor set (direct divide mode) n = 10 H~FFFH (16~4095) (Note) In the direct divide method, the data in PO~P3 becomes irrelevant and the P4 port becomes the LSB. 1999-03-05 9/18

Circuit configuration of prescaler and programmable counter (1) Circuit configuration in the pulse swallow mode Po=p3 rman C4 w Cie a, | reset AMANO) we prescater | T veeri-t FM. MODE ' counter 12 bit Pa~Pis The circuit is configured with a 2 modulus prescaler, swallow counter (4 bits), and a programmable counter (12 bits). In FM and TV modes, a 1/4 and a 1/8 prescaler are added in the front stage. (2) Circuit configuration in the direct divide method Amp. Preset rt vee-H | as P4a~P15 In the direct divide method, the prescaler section is passed through and the circuit consists of only a programmable counter (12 bits). (3) The FM-IN and AM-IN inputs each have a built-in amp, and are therefore capable of capacitor-coupled, small-amplitude operation. O Reference counter (divider to generate the reference frequency) The reference counter section is configured with a crystal oscillator and a counter. Using a 75 kHz crystal oscillator, this circuit can generate seven types of reference frequencies. 1. Setting the reference frequency Use the RO~R2 bits to set the reference frequency. FREQUENCY [0110] 215 oa device is placed in standby mode. pi [fo] o | 6.25 kHz Dao ft | 12.5 kee | pata fof sk | Li | 1 | 1 [standby mode 1999-03-05 10/18

The phase comparator compares the phase difference between the reference frequency signal fed from the reference frequency divider and the divided output from the programmable counter, and outputs the difference. In this way it controls the VCO through a low-pass filter to ensure that the frequencies and the phases of these two signals are matched to each other. Because this phase comparator has two tri-state buffers DO1 and DO2 connected in parallel as its outputs, you can design the optimum filter constant for each of the FM and AM bands. Furthermore, you can use the DOHZ bit of register D2 to place the DO2 output in a high- impedance state as necessary. DOHZ "1" : The DO2 pin is placed in the high-impedance state. “0” : Nomal operation Reference frequency Yop & Phase por = FM counter output Lee Ypb> poz do Lee Voc R [ l R2 RL : at To Di. on VCO tt u | V/ High level ht RB pe We TTS TNT a--- rt 77 Typical low-pass filter constant Low level Floating Typ. (Reference value for FM band) Try : 2SC1815 C = 0.33 uF Tr2 : 2SK246 R1 = 10k R2 = 8.2k0 R3 = 3300 RL = 10kO, DO output timing chart Example of an active low-pass filter circuit Shown above is a DO output timing chart and a typical active low-pass filter circuit based on a Darlington connection of FET and bipolar transistors. The filter circuit shown above is just one example. When designing the actual circuit, consider the band configuration and the desired characteristics of your system. 1999-03-05 11/18

This bit is used to detect an unlock condition of the PLL circuit. When not locked (i.e., the reference frequency and the programmable counter’s divided output are not locked in phase), the phase comparator outputs a pulse to the unlock F/F synchronously with the period of the reference frequency. The unlock F/F is set by this pulse. The unlock F/F is reset each time the RESET bit of register 2 (unlock reset bit) is set to 1. After the unlock F/F is reset in this way, you can access the unlock detection bit to see if the PLL circuit is in lock condition. Because the pulse is input synchronously with the period of the reference frequency, you must wait for a duration greater than the period of the reference frequency after resetting the unlock F/F before you can access the unlock detection bit (UNLOCK). If this duration is short, you cannot detect the correct lock condition. To solve this problem, the device has a lock enable F/F. This F/F is reset each time the unlock reset bit is set to 1, and lock enable bit is set to 1 with the unlock detection timing. This means that you can detect the correct unlock condition when the lock enable bit (ENABLE) is 1. ENABLE UNLOCK STATE [0 | _tock [1 untock —] Reference frequency LAFLTLPLS Ls Phase difference . l 4 Lock detection strobe Resetting unlock F/F : ‘ + Lock enable bit j j j i | l i j 1999-03-05 12/18

The general-purpose counter is used to count frequencies such as the FM/AM band IF frequency to detect the auto stop signal during auto search tuning. For this frequency counting, the general-purpose counter uses a frequency measurement (IF-AM, IF- FM input) method to count the number of pulses input to the counter during a certain duration of time (gate time). 1. General-purpose counter control bits (1) GO, G1 bits «+ These bits choose the general-purpose counter’s gate time. pa fo | 4ms | Lif | 64ms | (2) START bit + Each time the START bit is set to 1, measurement is restarted after resetting the general-purpose counter. (3) M8, M9 bits _--- These bits choose the general-purpose counter’s measurement mode and input pin. PIN INPUT FREQUENCY [me | ma | SELECTION RANGE REMARKS ; o | 1 | IFAM | 0.3~1.0MHz [Direct input to IF counter [1 [0 | IFFM 8~16 MHz IF frequency divided by 2 input to IF counter (Note)In the IF-FM mode, the general-purpose counter (20 bit binary counter) is preceded by an additionally inserted 1/2 prescaler. Therefore, the input signal from IF-FM is divided by 2 before being fed into the general-purpose counter. 2. General-purpose counter data output bits (f0~f19) (1) General-purpose counter count data bits (f0~f19) The resulting count of the general-purpose counter can be read in binary from the output registers f0 through f19. (2) General-purpose counter operation detect bits OVER -:: General-purpose counter "1" General-purpose counter is in overflow overflow bit condition. “0” General-purpose counter data is valid. BUSY -:: General-purpose counter a "1" General-purpose counter is counting. operation monitor "0" General-purpose counter has finished counting. (Note)When using the general-purpose counter, check to see that the BUSY bit is 0 (finished counting) and that the OVER bit is 0 (valid data) before you reference the contents of the general-purpose counter data bits (f0~f19). 1999-03-05 13/18

Circuit configuration of general-purpose counter The general-purpose counter section is configured with an input amp., a gate time control circuit, and a 20 bit binary counter. Ms M9 fo>f19 over ir-em C) > ' {> Ce o Overflow START Go GI 4. Measurement timing of general-purpose counter END PERIOD Lal START bit "1" set IFM or IAM BUSY bit 2 ] GATE | | counter input Clock pulse of measured frequency u—_—_ 0 < Ty S 0.25 (ys), 0 < Tz S 1 (ms) Frequency measurement timing chart (Note) IF-FM and IF-AM are capable of C-coupled, small-amplitude operation using a bipolar input. O General-purpose input/output ports The device has general-purpose input/output ports controlled by serial port. 1. General-purpose output ports (OT-1~OT-4) The data set to the 01~04 bits of input register 2 are output in parallel from their dedicated output ports OT-1~OT-4. 2. General-purpose input port (IN) The data input from the IN pin can be read out from the DATA pin as OUT-5 of the output register. (Note)The output ports are set to "0” when the device is powered on. (Therefore, the general- purpose output ports are held Low at power-on.) (Note)The TS bit of input register 2 must always be set to “0”. 1999-03-05 14/18

The TB2110FN uses a coil-type DC/DC converter (boosted voltage circuit) to allow for low-voltage operation. 4700 pF 151388 = oT 3 3] 36 “rT veo & bog Sehowty : Bi OHO 100 {3 100 pe @ Coil : (SUMIDA ELECTRIC CO., LTD, CP-4LB) BOTTOM VIEW TEST } same |isesan| — | [oe] wr | ar | one © 1999-03-05 15/18

MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage -0.3~4.5 Input Voltage -0.3~Vpp + 0.3 Operating Temperature =65=150

ELECTRICAL CHARACTERISTICS

(Unless otherwise specified, Ta = -20~75°C, Vcc = 1.0~2.5V, Vpp = 2.4V) TEST CHARACTERISTIC swwaot| er TEST CONDITION rn. |v. | ax UNIT CUIT Operating . 7 PLL operation Power Supply Biplor Unit) Vcc (Normal operating) 12 15 25 Vv Voltage MOS Unit Step-up control circuit operating| 2.2 | 24 | 3.6 | \\ PLL operation Operating Power Supply cc (Normal operating), TV mode Current PLL operation 15 7 (Normal operating), TV mode ° (Stand-by mode) Operating Power Supply I Vec = 1.5V 30 50 A Current cs cc # (Operating frequency) Crystal Oscillation Crystal oscillator connected to Frequency fxT | - | XI and XO pins. 75 kHz p Win | ay [= [tVmode «50 || 28 | | [erm firm [erm iY | | 16 Pe | Paw Tia eam | | =| 0 Le | (Input voltage) [sin [Vswin | — [SWmode = 25 300 Vv) [amin [Vain | — [AM mode = m¥rms iE FM Vier | — [FFM Vieam >= [ram SS 1999-03-05 16/18

SSOP24-P-300-0.65A Unit : mm 24 13 DHEAAARRERRG AFAAAAA RA AAA ay 2 S| & ea © wo n OUR HHH HHE HOGG RORAoaG 1 i 12 foes pose 8.3MAX 7.8+0.2 Nx 2 gs brid = = wo o a 0.45+0.2 o Weight : 0.31g (Typ.) 1999-03-05 18/18

Product Information

TB2110FN specifications and overview.

Summary

PLL FOR DTS

Description

PLL FOR DTS

Source title TB2110FN Datasheet(PDF) - Toshiba Semiconductor

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