TB2104F

TB2104F TOSHIBA | Alldatasheet

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TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC The TB2104F is a VFD (fluorescent display tube) driver IC implemented by the Bi-CMOS process. The logic section is configured with CMOS transistors, and the high voltage tolerant output driver section is configured with bipolar transistors. FEATURES RX o ras Senn @ Incorporates a shift register, latch, and driver capable of SH handling 20 bits of data. @ The output driver comes with an active pull-down, so it can function as a VFD grid, anode driver. @ Three serial data lines are used to input display data. SSOP30-P-375-1.00 . . Weight : 0.7: 5 © The data receiver section can also accept general-purpose ei 0.79 (Typ.) serial data and T-BUS (Toshiba Semiconductor Bus). @ In serial data mode, multiple drivers can be cascaded to expand the handling capacity in 20bit increments. PIN CONNECTION BLOCK DIAGRAM api i 30 J aD2 CLK DIN Ls GsVor cG/00 2 29 on @) 2) Q @__ Ge is 20 Mk VV V V V ame 27 Gno vi 5 26 By 0 Wo Hvo-20 If 6 25 fl Hvo-1 Hvo-19 7 24 ff Hvo-2 | sd Hvo-18 8 23 Hvo-3 ck D ck Tn >t HVO-1 svo-r7 Ws 22fl vos a Eee BP Hvo-16 ff 10 21 fl Hvo-s EY @ KD DS [2) Hv0-2 2obit 20bit : Hvo-15 Bit 20 A HvO-6 SHIFT REGISTER DATA LATCH Hi Hvo-14 12 19} Hv0-7 cIRCUIT cIRCUIT ! Hvo-13 J 13 18 Hvo-8 — HV0-20 Hvo-12 14 17 BJ Hvo-9 Q 220 i> D b> © Hvo-11 [15 16 BE HVO-10 i fD voo ft @ O) G9) @?) ce7b0 ADI ‘AD2 GND 9g0s0geBA2 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In ceveloping your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook 1998-05-15 1/8

ff aor | © Chip select / address setting inputs pele Address @ When using in Serial Mode, keep AD1 and AD2 “Open”. Ss Setting Input @ In other settings than “Open”, it becomes T-BUS Mode ra 20] aoe | and addresses up to 8 kinds can be set. E © Serial data input terminals @ Inputs display data through the DIN terminal synchronizing with rise of CLK input. CMOS }22| cux |etock mput | ® Display data are updated when inputting “H” level into Input }29| 01m |oate input | Ls terminal after completing data input. @ In T-BUS Mode, LS terminal becomes “PERIOD” input. @ Lamp test input terminal and data output terminal cmos @ In Serial Mode (AD1 =AD2 =Open), this terminal serves as Input / the serial data output terminal and enables cascade cmos Lamp Test connection of driver IC. Output 2 |CG/DO|Input and © In T-BUS Mode, this terminal serves as the lamp test built in Data Output input and is able to use all the driver outputs (HVO-1~ - aye - nun . pull-down 20) at “H” level by inputting “H” level signal. resistor @ During the normal operation in T-BUS Mode, use this 20k0 terminal by fixing at “L” level. © Driver OFF (blanking) input terminal laput _ @ All the driver outputs are fixed at “L” level when “L” built in cL Clear Input level signal is input. @ When “H" level signal is input, it becomes the normal pull-up mode. resistor 20kO. Logic Unit [5 | Yoo |r Soon | Vv Drive Unit @ Power supply and GND terminals DR | power Supply @ High-tension driver output terminal 25 |HVO-1 © Equivalent circuit 24 |Hvo-2 Vor 23 |HVO-3 : : Driver Output 8 |HVO-18 vo 7 |Hvo-19 DATA 6 |HVO-20 980508EBA2" by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice 8998-05-15 2/8

1. Serial data receiver circuit @ The serial data receiver circuit can be changed over to operate in the serial mode or the T-BUS Mode by switching, the AD1/AD2 terminals. @ In T-BUS Mode, the AD1/AD2 terminals become the chip select code inputs and it becomes possible to connect up to 8 drivers on the same bus line. 1) Input data format in serial data mode (AD1=AD2 ="Open”) cK J J l (ss) ) ls cH @ Display data are updated when data for 20 bits are input from MSB side (HVO-20), synchronizing with rise of CLK signal and LS input is set to "H” level after inputting data. @ When increasing driver ICs, connect them through cascade connection as shown below : “ eS Fe Oe is etal cK | cK cuK l Ls us us DIN DIN Do DIN bo DIN bo ooo OPEN—JaD1 = D2 ADI AD2 ADI AD2 2. Input data format in T-BUS Mode (start) (END) (PERIOD) weeeenen BIN NORRIE R KEKE NAKEXY) (.s8) (sa) (wise) (Us8) (MsB) (Us8) ss __— + T-BUS Address 8bit (TB2104F ="D4H") Display Data (20bit) Chip Select Code 4bit ("0H”~*7H") 1998-05-15 3/8

e@ In T-BUS Mode, start data transmission with the LS terminal (PERIOD) set at “L” level. Thereafter, send address data 8 bits, display data 20 bits, and chip select code 4 bits, synchronizing with rise of CLK signal. @ After sending data, set the LS terminal to “L” level again and terminate the data sending. @ On a driver IC when chip select code agrees with chip select code by AD1/AD2, display data are updated at fall of LS signal. @ When increasing driver ICs, it is possible to connect up to 8 ICs on the same bus line in combination with AD1/AD2. @ T-BUS address of the TB2104F is "D4H”. @ When data are transferred using T-BUS address "00H", the data can be input to all the driver ICs on the bus line independently of chip select codes ("0H"~"7H"). (This function can be used for Power On reset.) 3. AD1/AD2 input and chip select codes AD1/AD2 input are 3-value level inputs and 9 kinds (3 x3) of codes can be set. a | Va [ oof a fot [eH agus pt foo ft fH | Po fot ta a ee a a bap po] ad Po ft fo fH agus “wo [4a fo fof nH a 4. Example of extension of driver ICs in T-BUS Mode chip select code is ao ak a Ss ow a BR 8 1] ck cK ck cK DIN DIN A DIN -— DIN apt aD2 Fy oPEN—Jad1 — a2 ADI AD2 ADI AD2 Voo GND Chip Select Code (0H) (1H) (2H) . (7H) 1998-05-15 4/8

1. T-BUS Mode timing chart (START) tty th +3 ta us He + (END) By fl oN MAAAK KA AAAS @ = fcLK = 500kHz © t120.2ys, t220.2us e@ t321.0us, t4= 1.0us Cautions for use @ Therefore, multiple driver outputs may possibly become "H” level simultaneously after the power is turned ON. (In this case, the allowable power dissipation of a device using this IC may possible be exceeded, destroying the device.) © In order to avoid this, while keeping the clear terminal (C,) at "L” level, rise the power supply for the logic unit (Vpp) and then, that for the drivers (Vpp), reset all the contents of the data latch ("L” level) by serial data, and initialize the driver outputs. 1998-05-15 5/8

MAXIMUM RATINGS (Ta =25°C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage =03=70 Input Voltage =0.3~Vpp +0.3 [Driver Current | Ipr | _50__| ma | Pp (Note) Operating Temperature -40~85 =55~150 (Note) In case it is used at more than Ta =25°C, it is considered by reducing 6.4mW each 1°C. ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vpp =5V, VpR=50V, Ta = 25°C) TEST} CHARACTERISTIC Prmaoi| ci TEST CONDITION an | rv. | UNIT CUIT Operating Supply Voltage (1) [Vpp [| — logic unit TST SOT 55] VI Operating Supply Voltage (2)|Vpr | — [Driver unit | tof ~ | so] v | Operating Supply Current (1) [Ipp _| — [No load, No input | — {| o3[ 15{ ma | Operating Supply Current (2) [IpR__| — |No load, Output Vo, level [| — | 23[ 3.5] ma | mye VpD Input VIH (1) CMOS input terminal | $95 | = | vo | Vv Voltage DIN, CLK, LS, CG, CL “LU Level | ViL(1) t eno | ~ | Yoo mye Vp> vin 53 | = | voo| Input 3-value input terminal Vpb foo ~ | Input cmos A Current input terminal [vy =ov[ -1.0| ~ | 1.0] “ [input Resistance [Rin | — [3-value input terminal | 80] too] 120] kQ | Output HVO-1~-20 [Vow=4sv[ — [-84] -5] Current | “L" Level [lon (a) | | Output terminal [Vop=3V_ | 20] 27[ — | Output DO output [Von=4v_ | — | -03] -o1] Current___[ *L Level [lou (2) | — | terminal [Vosiv | 01} 03] — | Clock Frequency CLK max. operating | — | 5.0] 40 | mie | Clock Pulse Width [CLK min. operating | 75] 60] — | ns _| DIN min. operating pulse [_50[ 40] — | ns | Data Hold Time [tdh |e, ; [width [ so] 40; — | ns | 1S Pulse Width 9-1l15 min. operating | 80| 60] — | ns | CLK-LS Delay Time CLK-LS delay time | so| 4o{ — | ns | a CLK—»DOUT delay time cout Th iS Soe 9998-05-15 6/8

Fig.1 : Serial data timing chart 1/feuKk ck 50% y ~ J cour K __> ted ls a TT 95-157

SSOP30-P-375-1.00 Unit : mm 30 16 HOHOAAAAAREAAAAG ] HOO ( al 2 = 3] & Ble x] 3 MOOMMOOOHHHdon tC, WOOUMWOUUUUOUUdOO U 4 15 15.9MAX 15.440.2 ay -3 re i $9 WOTUTOUU UOC s) « a F ° q 0.9240.2 Weight : 0.7g (Typ.) 1998-05-15 8/8