TB1031N | DigiCamel IC Datasheet

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TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC As an interface between the microcontroller and peripheral devices, TB1031N is an ideal driver IC. Because it contains various drivers on one chip, TB1031N _f effectively reduces the number of parts. ae The device features built-in registers that can simplify a — wy software design when used in combination with an eight- Q2 ay Wt bit microcontroller. Hoy it ques

FEATURES

© Built-in zero-cross detector circuit SDIP30-P-400-1.78 Weight : 1.99g (Typ.) @ High-current output ports (two 70mA, two 60mA, two 50mA ports ; four 30mA ports) © Direct drive for triac buzzer @ Built-in buzzer drive circuit (2.7kHz) @ Built-in pulse multiplication (x2) function © 8bit serial interface © Built-in watchdog timer (30ms, 15ms settings) @ Built-in mains voltage monitoring circuit @ Built-in LC oscillator circuit © Built-in 8bit D/A converter for constant-current control 961001684 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. Sir: products described in this document are subject to foreign exchange and foreign trade control laws. The information contained herein is presented oniy as a guide for the applications of our products. No responsibility is assumed. by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1997-04-07 1/22

Vcc AGND DGND WLO- WLI WL2 ROTOUT XIN XOUT1 XOUT2 circuit [De De > ° Out orf >o me? arial coe ws (4x2) cI (> otro ase SF Yo~ V2 <i sce GS Regine selector [-—\\y 7 =i. circuit by 2 | D/A co CYH> Control register 0 +> i == BS Mains voltage UY aossea a | pow C} monitoring circuit > Ale Ace TBIP| generator TRC7 TOM-T2M | TBF V Triac gate trigger |PHOUT| phase control | [ Buzzer drive [> sacour o<] Brevik circa crcut arst CY ea rere to 1D accax et) CO GO GO CO O O O O O O O O O O TBI 180 Tco TC TQ Te Tea 16 Tes 17 1997-04-07 2/22

MAXIMUM RATINGS (Ta = 25 + 1.5°C) CHARACTERISTIC SYMBOL RATING UNIT Supply VoRiage =03=70 input Voltage ~O3=Vec+05 POW Pin Input Voltage VINPOW TBO And TB1 Pin Input Voltage VINTB Pp (Note 1) Operating Temperature Storage Temperature [Trg | = 58125 | *c_| Electrostatic Destruction ESD (Note 2) Latch Up Current (Note 1) The power dissipation decreases about 12mW for every degree of temperature increase. (Note 2) C=200pF and R=0, one discharge for each polarity. ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vcc =5.0V, Ta=25+1.5°C) TEST } cramacrensre | srmwor [Ei] test conomow | mn. | re [wax] ur CUIT Operating Supply Voltage Vee v Operating Current \\ 8.0MHz oscillation with no mA Dissipation cc load Operating Frequency FOPRAN Band Open Pin Voltage VOPRTIN When idle v (Design Target) Low-level Input Current | IILRRTIN | — |When idle and Vin =0V [| -77 | -100 | -143[ aA | High-level Input 0.8 Voltage VIHRTIN vee Vec | Vv 0.2 Low-level Input Voltage] VILRTIN Vv fowieenot vote] virrw f=] of = Jee] | Pin 2 (TBO), Pin 3 (TB1) Off-leak Current IOFFTBO1 | — [When idle and Vin =5V [| -1] — | 1] 4A | Low-level Output 1997-04-07 5/22

CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT Pin 4 (TCO), Pin 5 (TC1) forrieak current _OFFTCOT | — [When idle and Vig=sv_[ -1] — | 1] 2a | Low-level Output sr fosen [fie nee Pin 7 (TC2), Pin 8 (TC3) Off-leak Current IOFFTC23__| — [When idle and Vin =5V [ -1[ — [ 1] ga | Low-level Output _ Pin 9 (TC4), Pin 10 (TCS), Pin 11 (TC6), Pin 12 (TC7) Off-leak Current 1OFFTC47__| — [When idle and Vin =5V [| -1[ — | 1] ga | Low-level Output High-level Output _ Voltage MVOHACOUT loH= -—1mMA Vv Low-level Output When input goes from high to Threshold Voltage VTHACCLK low, voltage to change 0.25 | 0.35 Vv BACOUT from high to low When input goes from low to high, difference between Hysteresis Width VHYSACCK VTHACCLK and voltage needed| 50 100 mv to change BACOUT pin from low to high Pin 15 (POW) . When input changes from high High-level Threshol Volta me reshold VTHPOW to low, voltage to change Vv

9 BRST pin from high to low

When input goes from low to high, difference between Hysteresis Width VHYSPOW VTHPOW and voltage needed 1.35 | 1.45 Vv to change BRST pin from low to high Voltage that can be applied to Input Voltage Range VINPOW | - | POW pin Vv Recommended oscillator : Murata 8MHz Ceralock ceramic oscillator (CST8.0MTW) 1997-04-07 6/22

CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT Pin 17 (OPTRO) Vcc =5V, When 300 external resistor connected, 3.0V Output Current 1 applied to OPTIN pin, and 67 70 73 DAC =FF Vcc =5V, When 302 external Output Current 2 resistor connected, 3.0V (Design Target) 'opa applied to OPTIN pin, and 0.55 | 1.24) ma DAC=01 Vcc =5V, When 300 external resistor connected, 3.0V Output Current 3 1oP3 applied to OPTIN pin, and 33.1 | 35.3 | 37.6 DAC =80 Vcc =5V, When 300 external resistor connected, 3.0V Output Current 4 applied to OPTIN pin, and 0.12 | 0.82 | 1.53 DAC =02 Vcc =5V, When 300 external resistor connected, 3.0V Output Current 5 1OP5 applied to OPTIN pin, and 1.37 | 2.10 DAC =04 Vcc =5V, When 300 external resistor connected, 3.0V Output Current 6 applied to OPTIN pin, and 2.46 | 3.24 DAC =08 Vcc =5V, When 300 external resistor connected, 3.0V Output Current 7 10P7 applied to OPTIN pin, and 3.78 | 4.65 | 5.53 DAC=10 Vcc =5V, When 300 external resistor connected, 3.0V 1OP: . . 7.97 10.1 Output Current & ors applied to OPTIN pin, and 9 0 DAC =20 Vcc =5V, When 300 external resistor connected, 3.0V Output Ci it 9 . uo 17.8 | 19.3 utput Curren’ applied to OPTIN pin, and DAC =40 1997-04-07 7/22

CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT When Vcc =4.5V, 302. external resistor connected, 2.5V Output Current 10 1OP10 applied to OPTIN pin, and DAC =FF Vcc =5.5V, When 302 external resistor connected, 3.5V Output Current 11 10OP11 applied to OPTIN pin, and 74 77 DAC =FF Pin 18 (OPTIN) When DAC data are 00 and crn cn [evo] fypearr™™ | [—[ [om 8bit D/A Converter (DAC) Characteristics DAC Reference Voltage 1 (Design Target) [ver [| en Vee =. | 203 | 200 [28] v | DAC Reference Voltage Vee =5.0V DAC Output Voltage 1 | VOPTRO1 When DAC data FF and 302 | » 4, 2.20} v external resistor connected to OPTRO pin When Vcc =4.5V, DAC data FF, DAC Output Voltage 2 | VOPTRO2 and 300, external resistor Vv connected to OPTRO pin IDAC (n + 1) - IDAC (n) Monotony AIDAC1 | - | n=0~255 0.27 pacer? [oun] = RR om ow] — | Pin 19 (WLO) High-level Input oe A Current IIHRWLO Vin =5V, WL1 pin open 4.3 17.1 | pA Low-level Input Current | IILRWLO | — |Vin=0V, WL1 pin open [-43 | -86 [-17.1] pA | 1997-04-07 8/22

CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT Pin 20 (WL1) High-level Output lous | — | Vin =0V, OV applied to WLO | -09] — | — | m | Current pin Low-level Output looms | — | Vin =5V, 5V applied to WLO | 03] — | — | ma | Current pin High-level Output a Voltage VOHWL2 lon = -1mA 45 Vec | V Low-level Output = Pin 22 (XIN) High-level Input oe Voltage IHXIN Vin =5V 1.5 7.0 vA Pin 23 (XOUT1) High-level Output =- Voltage VOHXOUTI lon = - 300A 45 Vec | V Low-level Output _ Pin 24 (XOUT2) High-level Output __ Voltage VOHXOUT2 loH = -1mA 45 Vec Vv Low-level Output _ Oscillator Characteristics Oscillation Start VSTA When using 4~8MHz v Voltage oscillation Oscillation Holding VHOLD When using 4~8MHz v Voltage oscillation Oscillation Start Time | TSTA When using 4~8MHz oscillation Pin 25 (Dl) Open Pin Voltage VoPDI When idle 5.000 v (Design Target) Low-level Input Current | _IILRDI | — [When idle and Vin =0V [-0.77[ -1.0[-1.43| mA | High-level Input 0.8 Voltage VIHDI Ve Vec v nt mae] wor [=| | te | | 1997-04-07 9/22

(1) Control registers To control the TB1031N operation, set the internal registers through serial communications with the microcontroller. The control registers are 8bit registers organized as in the following table. 1.1. Control registers REGISTER NAME SYMBOL Command Register 0 Command Register 1 Triac Register TRCO~7 Phase Data Register 1 | PDOO0~07 Phase Data Register 2 | PD10~17 Command register (Cp, C1) functions REGISTER SYMBOL FUNCTION Watchdog timer operation enable/disable ¢ Watchdog timer time selection [ RP | Pulse multiplication circuit (ROTOUT) output selection TB1 port output mode selection System clock selection [ Tz [TCO and TC1 simultaneous ON enable/disable TC2 and TC3 simultaneous ON enable/disable [PHF [Phase control enable/disable CS c TCO~TC3 triac gate pulse width selection

1 TCO and TC1 pulse mode selection

TC2 and TC3 pulse mode selection TBIF TB1 ON/OFF control TBOF TBO ON/OFF control 1997-04-07 11/22

Control register 0 (Cg) pit state PMSB tT Po to Ty wor wor wir ref tere scr [0 [Normal mode | Disable | 15ms | _wi2 | xt | 27KHa | 1 | Test mode | Enable | 30ms__| ROTOUT LAfterreset | 0 To foo fT oo foo foo fo fT | (Note) Set bits Tg and Tj to “0”. Control register 1 (C4) BIT STATE MsB LSB Tair] TBOF [0 | Bisabie | Disabie | Disable | ims | oc | bc | ofr _| orf _ [After reset | oT of oT

1.2 Triac register (TRCO~7)

The triac register is organized as in the following table. This register is used to select a port (pins TCO~TC7) to drive. Triac register (TRC) BIT NAME MsB LSB [0 [oF [or [or [on [or [on [or [or] pafterreset | oo To fT oo fT oe 1.3. Phase data registers 1 and 2 (Ppgo~Ppo7. Pp10~Pp17) The phase data registers are organized as in the following table. When performing phase control, the delay time data from the zero-cross point can be set. Phase data register 1 (Ppg) BIT NAME MsB LSB poo7_ | pooe | ppos [ ppo4 | ppo3 | ppo2 | _PD01 PDOO [Atterreset | oT oT Phase data register 1 (Pp4) BIT NAME MsB LSB | poi | poi [pois ppia J pb13 Tppi2_ | pp | Ppi0_ | | Afterreset | OT of 1997-04-07 12/22

1.4 D/A data register (Yg~Y7)

The D/A data register is organized as in the following table. The register can be used to set the built-in 8bit D/A converter data. D/A data register (Y97) BIT NAME MsB LSB [Atterreset | 0 oT oo fT oT (2) Communication with microcontroller Communication with the microcontroller is based on serial communications controlled by the data received from the microcontroller. Transfer data consist of 2-byte commands (Cg, C1) and 4-byte data (TRC, Ppg, Pp1, Yo7). Command transfer is enabled on the rising edge of the C/D pin. Data transfer is enabled on the falling edge of the C/D pin. Transfer timing chart sck Command /data switching Frommana enabled Data enabled cD LSB>MSBLSB>MSB LSB>MSB —LSBOMSB_LSB-MSB_LSB-9MSB (3) | Phase data resolution The delay time from the zero-cross point is set using the internal 32kHz-clock as a reference. The maximum delay is 8ms (at FFH) ; the minimum delay is 31.25ys (at OOH). (Example) (Example) Motor driving time : Short Motor driving time : Long + Slow rotation ts Fast rotation : ACN aN H i i Pp (max) : Po (min) | | ae Zero-cross : _ pulse | 1997-04-07 13/22

(4) Data register combination during phase control Four pins are provided as phase-controllable port pins : TCO, TC1, TC2, TC3 The Cy register contains two bits (T2, T3) to select a combinations of the four pins to be used simultaneously. During phase control, these bits can be set to change the combination of the phase data output to the port pins. Phase data combinations using simultaneous ON control bits Tz and T3. SIMULTANEOUS ON e HIGH-CURRENT OUTPUT PORT PIN po | o [Poo fT por poo fT tT oT a When performing phase control, set the PHF bit in the C1 register to “1”. (5) | TCO~TC3 pins zero-cross synchronization / pulse output To avoid radio-frequency impulse noise and triac degradation, the TB1031N is designed so that the triac trigger can be turned ON at a timing synchronized to the zero-cross point. Also, to reduce power dissipation, the pulse signals can be used to trigger the triacs. The internal 4kHz- clock can also be used for pulse output. Bits TOM and T2M of command register 1 (C1) can select DC and pulse output. TooTe TTC [0 «| Dc output | DC output _| Pulse output (4kHz) | Pulse output (4kHz) Timing chart Zero-cross pulse oon | ee | ee | Triac data i (e TRCO-TRC1-TRC2-TRC3 Zero-cross synchronization JTL DC output Pulse output (4kHz) 1997-04-07 14/22

(6) Zero-cross detector circuit The voltage divided from full-wave rectified AC power is input to ACCLK. The circuit detects the rising edge of the ACIN and can generate a 1ms-zero-cross pulse at BACOUT. Block diagram Voc g c* 2 @ ile sl |e ga os be v= () generator © Microcontroller Timing chart Hysteresis voltage VHYSACCK : 0.1V ACCLK Threshold voltage SN... t i VTHACCLK : 0.35V i ACIN i BACOUT Pulse width : Ims (7) _ Triac gate signal width selection (GW) During phase control, the pulse width of the gate signal for the triac connected to pins TCO~TC3 can be selected from two pulse widths in accordance with the triac sensitivity. Register C1 is used for the gate signal width selection. es P12] 1997-04-07 15/22

(8) TBO and TB1 pin control The bits (TB1F and TBOF) to turn the output of pins TBO and TB1 ON and OFF are assigned to register Cy. Pin TB1 also has a bit (TB1P) to select DC output or the pulse output (2.7kHz) for driving a buzzer, for example. [o_o or | 2 7itr ontnt [1 on onc output _| (9) System clock selection (SCF) TB1031N includes an internal clock generator to generate several basic clocks and supply the clocks to the logic circuits. When the source clock is 8MHz, be sure to set the SCF bit of the Cg register to “1”. When the source clock is 4MHz, set SCF to “0”. Using 8MHz oscillator (10) Watchdog timer The watchdog timer is cleared each time one byte of serial data is sent from the microcontroller. If serial data are not sent for 15ms or 30ms, a 1ms-width reset signal can be output to the BRST pin to reset the microcontroller. The watchdog timer control bits (WDF and WDT) are assigned to register Cg. [0 _—*'| __ Disabled Detection time _15ms | 1 ~~ ‘[ Enabled Detection time 30ms Timing chart Serial clock see SLU L_15ms or 30ms Reset output + 7 BRST : U : x 1ms 1997-04-07 16/22

(11) Pulse multiplication circuit This circuit can detect the rising or falling edge of the pulse input from the ROTIN pin, and output a 1x or 2x pulse to the ROTOUT pin. The ROTOUT output selection bit (RP) is assigned to register Cg. When 2x, the pulse width is fixed at 1ms. [ __0 _|ROTOUT : Outputs 1xROTIN pulse ROTOUT : Outputs 2xROTIN pulse Timing chart ROTIN l l ROTOUT ax ROTOUT r1 rl rd im (2x) a =r Fixed at Ims (12) LC oscillator circuit An LC oscillator circuit can be configured simply by attaching an external variable coil (L) and a fixed capacitor (C). The square wave signal (WLOUT) formed from the WL1 output is output to pin WL2. Bit WLF, located in the Cg register, can be used to select either WLOUT output or ROTOUT output. | 0 —_[WL2 : WLOUT (WL1) output WL2 : ROTOUT output Example circuit WLO O Ry wl BY * Rp ¥ Waid 33K selector ROTOUT Microcontroller: circuit, Example design : L=0.38mH C=0.022pF 1997-04-07 17/22

(13) 8Bit D/A converter for constant-current control To make the load current constant, attach a load such as a sensor to the OPTIN pin, set the data in the D/A data register, and connect a resistor to the OPTRO pin. Block Diagram VReF vec DAOUT Rg om 1! <i <i Bed DIA aa Yo~Y7 onrnarhy Pa (Note) Because the AMP1 output is held low when the D/A data are 00H, Q1 is OFF. Therefore, the effective data length is seven bits (Y1~Y7). The 8bit D/A resolution is : VpEF (2.1V)/256 =about 8.2mV (@Vcc =5V) (14) Mains voltage monitoring circuit Implement full-wave rectification on the secondary side output of the transformer and step down the smoothed voltage. By monitoring the stepped-down voltage at the POW pin (pin 15), a reset can be performed on the internal registers and logic circuits. Also, by connecting the BRST pin to the reset pin of the microcontroller, the entire application system can be reset. As the following timing chart shows, the reset voltage has hysteresis, which guarantees operation during momentary outages, for example. Block diagram * vec ow? monitoring Logic circuit reset east pin Watchdog timer reset 1997-04-07 18/22

Reset release voltage Hysteresis voltage VTHPOW VHYSPOW 5.AV (TYP) oy eeveeseseeeenel ASM TYP Microcontroller minimum operating voltage; F eset voltage, ; . 400 0 pen i VTHPOW2 GND trst i i tt BRST | The above chart shows the recommended design for the relationship between the mains power monitoring voltage (VPOW) and the system power supply (Vcc). (15) High-current output port The high-current output port (pins TBO, TB1, TCO~TC7) are NPN open collector circuits and can directly drive devices such as a triac or buzzer. Select the most suitable triac or buzzer in accordance with the use conditions. Block diagram Voc a Control signal ze qe Resistors Ry and R2 are configured for each port as in the following table. OUTPUT RPRRENT Ry Ro OUTPUT CURRENT Ry Ro CAPACITY (min CAPACITY (min) “ae 30mA 6500 | 70kQ zen yon fT (Note) Depending on the number of high-current output ports ON simultaneously, the power dissipation shown in the maximum ratings may be inadvertently exceeded. Take care not to exceed the rating. 1997-04-07 19/22

(16) Oscillator circuit The oscillator circuit is configured as in the following diagram. Connecting 4MHz~8MHz oscillators creates a system clock. To supply a clock to the microcontroller, connect the XOUT2 pin to the microcontroller’s XOUT pin. Block diagram xu gto Clock v ¥v ad ¥ cx a W Microcontroller SOO" sb XOUT pin Recommended oscillators : 8MHz : Murata 8MHz Ceralock ceramic oscillator (CST8, OMTW) 4MHz : Murata 4MHz Ceralock ceramic oscillator (CST4, OMGW) 1997-04-07 20/22

APPLICATION CIRCUIT EXAMPLE ara oe | Q 3| Sle" a | ROTIN @) vec BD eo Vp | start/stop rer dio ob qd Fa ato OE 76 rool es @ ocno 1 ‘eo (9 ae Tez xour2 [> C} xour LO ye Gio x0n pare Me rr Tea XIN BAER Ki Jwater level detection Soft h Dirt detection omener Supply CQ] Tes wiz 2) C Wash volume detection Gy 16 wu [9 im: q @] 107 wio [19 ro BacouT oPTIN [9 ACCLK OPTRO LED a 2 EL ower Pins @] pow —acno [® vss 1 1997-04-07 21/22

SDIP30-P-400-1.78 Unit : mm fo 30 16 bd Noma a a a a a a a ° | 0 ro) » g ° = 38 | #9 ee oe ee ee § t 15 27.9MAX 27.440.2 Pool og MO OOO st 8 z bid HE: _ o Weight : 1.99g (Typ.) 1997-04-07 22/22

Product Information

TB1031N specifications and overview.

Summary

INTERFACE DRIVER IC FOR WASHING MACHINE

Description

INTERFACE DRIVER IC FOR WASHING MACHINE

Source title TB1031N Datasheet(PDF) - Toshiba Semiconductor

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