TAS6424MQDKQRQ1

TAS6424M-Q1 TI1 | Alldatasheet

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Technical content

5.9 cm2 27 mm 22 mm Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TAS6424M-Q1 SLOS948 – FEBRUARY 2019 TAS6424M-Q145-W,2-MHzdigitalinput4-channelautomotiveclass-Daudioamplifier withloaddumpprotectionandI2Cdiagnostics

1 Features

1• AEC-Q100 Qualified for Automotive Applications – Device Temperature Grade 1: –40°C to +125°C TA

• Advanced Load Diagnostics – DC Diagnostics run without Input Clocks – AC Diagnostic for Tweeter Detection with Impedance and Phase Response
• Easily meet CISPR25-L5 EMC Specification
• Audio Inputs – 4 Channel I2S or 4/8-Channel TDM Input – Input Sample Rates: 44.1 kHz, 48 kHz, 96 kHz – Input Formats: 16-bit to 32-bit I2S, and TDM
• Audio Outputs – Four-Channel Bridge-Tied Load (BTL) – Two-Channel Parallel BTL (PBTL) – Up to 2.1 MHz Output Switching Frequency – 27 W, 10% THD Into 4 Ω at 14.4 V BTL – 45 W, 10% THD Into 2 Ω at 14.4 V BTL – 80 W, 10% THD Into 2 Ω at 18 V PBTL
• Audio Performance Into 4 Ω at 14.4 V BTL – THD+N < 0.02% at 1 W – 42 µVRMS Output Noise – –90 dB Crosstalk
• Load Diagnostics – Output Open and Shorted Load – Output-to-Battery or Ground Shorts – Line Output Detection Up to 6 kΩ – Host-Independent Operation
• Protection – Output Current Limiting – Output Short Protection – 40 V Load Dump – Open Ground and Power Tolerant – DC Offset – Overtemperature – Undervoltage and Overvoltage
• General Operation – 4.5 V to 18 V Supply voltage – I2C Control With 4 Address Options – Clip Detection and Thermal Warning

2 Applications

• Automotive Head Unit
• Automotive External Amplifier

3 Description

The TAS6424M-Q1 device is a four-channel digital- input Class-D audio amplifier that implements a 2.1 MHz PWM switching frequency enabling a cost- optimized solution in a very small PCB size, full operation down to 4.5 V for start/stop events, and exceptional sound quality with up to 40 kHz audio bandwidth. The output switching frequency can be set either above the AM band, which eliminates AM-band interferences and reduces output filtering and cost, or below the AM band to optimize efficiency. The device has a built-in load diagnostic function for detecting and diagnosing misconnected outputs as well as detection of AC-coupled tweeters to help to reduce test time during the manufacturing process. The TAS6424M-Q1 Class-D audio amplifier is designed for use in automotive head units and external amplifier modules. The device provides four channels at 27 W into 4 Ω at 10% THD+N and 45 W into 2 Ω at 10% THD+N from a 14.4 V supply. For pin compatible one, two and four-channel devices see the TAS6421-Q1, TAS6422-Q1, TAS6424L-Q1 and TAS6424-Q1. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TAS6424M-Q1 HSSOP (56) 18.41 mm × 7.49 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. PCB AREA

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13.2 Receiving Notification of Documentation Updates 58

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES February 2019 * Initial release.

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5 Device Options

Limit (Typ) Output Power / 10% THD 4 Ω / BTL 14.4 V 4 Ω / BTL Max Voltage 2 Ω / BTL 14.4 V 2 Ω / PBTL Max Voltage TAS6424-Q1 4 4.5 V to 26.4 V 6.5 A 27 W 75 W at 25 V 45 W 150 W at 25 V TAS6424M-Q1 4 4.5 V to 18 V 6.5 A 27 W 45 W at 18 V 45 W 80 W at 18 V TAS6424L-Q1 4 4.5 V to 18 V 4.8 A 27 W 45 W at 18 V 27 W 80 W at 18 V TAS6422-Q1 2 4.5 V to 26.4 V 6.5 A 27 W 75 W at 25 V 45 W 150 W at 25 V TAS6421-Q1 1 4.5 V to 26.4 V 6.5 A 27 W 75 W at 25 V 45 W N/A

3VBAT 54 BST_4P 4AREF 53 OUT_4P 5VREG 52 GND 6VCOM 51 OUT_4M 7AVSS 50 BST_4M 8AVDD 49 GND 9GVDD 48 BST_3P 10GVDD 47 OUT_3P 11GND 46 GND 12MCLK 45 OUT_3M 13SCLK 44 BST_3M 14FSYNC 43 PVDD 15SDIN1 42 PVDD 16SDIN2 41 BST_2P 17GND 40 OUT_2P 18GND 39 GND 19VDD 38 OUT_2M 20SCL 37 BST_2M 21SDA 36 GND 22I2C_ADDR0 35 BST_1P 23I2C_ADDR1 34 OUT_1P 24STANDBY 33 GND 25MUTE 32 OUT_1M 26FAULT 31 BST_1M 27WARN 30 PVDD 28GND 29 PVDD Not to scale Thermal Pad TAS6424M-Q1 SLOS948 – FEBRUARY 2019 www.ti.com Product Folder Links: TAS6424M-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

6 Pin Configuration and Functions

56-Pin HSSOP With Exposed Thermal Pad Top View

www.ti.com SLOS948 – FEBRUARY 2019 Product Folder Links: TAS6424M-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output, DI/O = digital input and output, NC = no connection Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. AREF 4 PWR VREG and VCOM bypass capacitor return AVDD 8 PWR Voltage regulator bypass. Connect 1 µF capacitor from AVDD to AVSS AVSS 7 PWR AVDD bypass capacitor return BST_1M 31 PWR Bootstrap capacitor connection pins for high-side gate driver BST_1P 35 PWR Bootstrap capacitor connection pins for high-side gate driver BST_2M 37 PWR Bootstrap capacitor connection pins for high-side gate driver BST_2P 41 PWR Bootstrap capacitor connection pins for high-side gate driver BST_3M 44 PWR Bootstrap capacitor connection pins for high-side gate driver BST_3P 48 PWR Bootstrap capacitor connection pins for high-side gate driver BST_4M 50 PWR Bootstrap capacitor connection pins for high-side gate driver BST_4P 54 PWR Bootstrap capacitor connection pins for high-side gate driver FAULT 26 DO Reports a fault (active low, open drain), 100-kΩ internal pull-up resistor FSYNC 14 DI Audio frame clock input GND 1, 11, 17, 18, 28, 33, 36, 39, 46, 49, 52 GND Ground GVDD PWR Gate drive voltage regulator derived from VBAT input pin. Connect 2.2 µF capacitor to GND 10 Gate drive voltage regulator derived from VBAT input pin. Connect 2.2 µF capacitor to GND I2C_ADDR0 22 DI I2C address pins. Refer to Table 8 I2C_ADDR1 23 MCLK 12 DI Audio master clock input MUTE 25 DI Mutes the device outputs (active low) while keeping output FETs switching at 50%, 100-kΩ internal pull-down resistor OUT_1M 32 NO Negative output for the channel OUT_1P 34 PO Positive output for the channel OUT_2M 38 NO Negative output for the channel OUT_2P 40 PO Positive output for the channel OUT_3M 45 NO Negative output for the channel OUT_3P 47 PO Positive output for the channel OUT_4M 51 NO Negative output for the channel OUT_4P 53 PO Positive output for the channel PVDD 2, 29, 30, 42, 43, 55, 56 PWR PVDD voltage input (can be connected to battery). Bulk capacitor and bypass capacitor required SCL 20 DI I2C clock input SCLK 13 DI Audio bit and serial clock input SDA 21 DI/O I2C data input and output SDIN1 15 DI TDM data input and audio I2S data input for channels 1 and 2 SDIN2 16 DI Audio I2S data input for channels 3 and 4 STANDBY 24 DI Enables low power standby state (active Low), 100-kΩ internal pull-down resistor VBAT 3 PWR Battery voltage input VCOM 6 PWR Bias voltage VDD 19 PWR 3.3-V external supply voltage VREG 5 PWR Voltage regulator bypass WARN 27 DO Clip and overtemperature warning (active low, open drain), 100-kΩ internal pull-up resistor Thermal Pad — GND Provides both electrical and thermal connection for the device. Heatsink must be connected to GND.

SLOS948 – FEBRUARY 2019 www.ti.com Product Folder Links: TAS6424M-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT PVDD, VBAT DC supply voltage relative to GND –0.3 30 V VMAX Transient supply voltage: PVDD, VBAT t ≤ 400 ms exposure –1 40 V VRAMP Supply-voltage ramp rate: PVDD, VBAT 75 V/ms VDD DC supply voltage relative to GND –0.3 3.5 V IMAX Maximum current per pin (PVDD, VBAT, OUT_xP, OUT_xM, GND) 8 A IMAX_PULSED Pulsed supply current per PVDD pin (one shot) t < 100 ms 12 A VLOGIC Input voltage for logic pins (SCL, SDA, SDIN1, SDIN2, MCLK, BCLK, LRCLK, MUTE, STANDBY, I2C_ADDRx) –0.3 VDD + 0.5 V VGND Maximum voltage between GND pins –0.3 0.3 V TJ Maximum operating junction temperature –55 150 °C Tstg Storage temperature –55 150 °C (1) AEC Q100–002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS–001 specification.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100–002(1) HBM ESD Classification Level 2 ±3000 V Charged-device model (CDM), per AEC Q100–011 CDM ESD Classification Level C4 All pins ±500 Corner pins (1, 28, 29 and 56) ±1000

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7.3 Recommended Operating Conditions

PVDD Output FET supply voltage Relative to GND 4.5 18 V VBAT Battery supply voltage input Relative to GND 4.5 14.4 18 V VDD DC logic supply Relative to GND 3.0 3.3 3.5 V TA Ambient temperature –40 125 °C TJ Junction temperature An adequate thermal design is required –40 150 °C RL Nominal speaker load impedance BTL Mode 2 4 Ω PBTL Mode 1 2 RPU_I2C I2C pullup resistance on SDA and SCL pins 1 4.7 10 kΩ CBypass External capacitance on bypass pins Pin 2, 3, 5, 6, 8, 19 1 µF CGVDD External capacitance on GVDD pins Pin 9, 10 2.2 µF COUT External capacitance to GND on OUT pins Limit set by DC-diagnostic timing 1 3.3 µF LO Output filter inductance Minimum inductance at ISD current levels 1 µH (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). (2) JEDEC Standard 4 Layer PCB. (3) Measured using the TAS6424M-Q1 EVM layout and heat sink. The device is not intended to be used without a heat sink.

7.4 Thermal Information

THERMAL METRIC(1) TAS6424M-Q1(2) TAS6424M-Q1(3) UNITDKQ (HSSOP) DKQ (HSSOP)

56 PINS 56 PINS

RθJA Junction-to-ambient thermal resistance 38.8 — °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.3 1.1 °C/W RθJB Junction-to-board thermal resistance 16.0 — °C/W ψJT Junction-to-top characterization parameter 0.1 — °C/W ψJB Junction-to-board characterization parameter 14.6 10 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a — °C/W

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7.5 Electrical Characteristics

Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 79 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING CURRENT IPVDD_IDLE PVDD idle current All channels playing, no audio input 75 90 mA IVBAT_IDLE VBAT idle current All channels playing, no audio input 90 100 mA IPVDD_STBY PVDD standby current STANDBY Active, VDD = 0 V 0.5 1 μA IVBAT_STBY VBAT standby current STANDBY Active, VDD = 0 V 4 6 μA IVDD VDD supply current All channels playing, –60-dB signal 15 18 mA OUTPUT POWER PO_BTL Output power per channel, BTL 4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 20 22 W 4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 25 27 2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 38 40 2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 42 45 4 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C 30 33 4 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C 40 45 PO_PBTL Output power per channel in parallel mode, PBTL 2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 35 40 W 2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 45 50 1 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 72 80 1 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 80 90 2 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C 60 65 2 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C 75 80 EFFP Power efficiency 4 channels operating, 25 W output power/ch, 4 Ω load, PVDD = 14.4 V, TC = 25°C, including inductor losses(1) 86% AUDIO PERFORMANCE Vn Output noise voltage Zero input, A-weighting, gain level 1, PVDD = 14.4 V 42 μV Zero input, A-weighting, gain level 2, PVDD = 14.4 V 55 Zero input, A-weighting, gain level 3, PVDD = 18 V 67 Zero input, A-weighting, gain level 4, PVDD = 18 V 85 GAIN Peak output voltage/dBFS Gain level 1, Register 0x01, bit 1-0 = 00 7.5 V/FS Gain level 2, Register 0x01, bit 1-0 = 01 15 Gain level 3, Register 0x01, bit 1-0 = 10 21 Gain level 4, Register 0x01, bit 1-0 = 11 29 Crosstalk Channel crosstalk PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz –90 dB PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz 75 dB THD+N Total harmonic distortion + noise 0.02% GCH Channel-to-channel gain variation –0.5 0 0.5 dB LINE OUTPUT PERFORMANCE Vn_LINEOUT Line output noise voltage Zero input, A-weighting, channel set to LINE MODE 42 μV VO_LINEOUT Line output voltage 0-dB input, channel set to LINE MODE 5.5 VRMS THD+N Line output total harmonic distortion + noise VO = 2 VRMS , channel set to LINE MODE 0.01% DIGITAL INPUT PINS VIH Input logic level high 70 %VDD VIL Input logic level low 30 %VDD IIH Input logic current, high VI = VDD 15 µA IIL Input logic current, low VI = 0 –15 µA PWM OUTPUT STAGE RDS(on) FET drain-to-source resistance Not including bond wire and package resistance 90 mΩ OVERVOLTAGE (OV) PROTECTION VPVDD_OV PVDD overvoltage shutdown 19.3 20 22 V VPVDD_OV_HYS PVDD overvoltage shutdown hysteresis 0.8 V VVBAT_OV VBAT overvoltage shutdown 20 21.5 23 V

www.ti.com SLOS948 – FEBRUARY 2019 Product Folder Links: TAS6424M-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 79 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVBAT_OV_HYS VBAT overvoltage shutdown hysteresis 0.6 V UNDERVOLTAGE (UV) PROTECTION VBATUV VBAT undervoltage shutdown 4 4.5 V VBATUV_HYS VBAT undervoltage shutdown hysteresis 0.2 V PVDDUV PVDD undervoltage shutdown 4 4.5 V PVDDUV_HYS PVDD undervoltage shutdown hysteresis 0.2 V BYPASS VOLTAGES VGVDD Gate drive bypass pin voltage 7 V VAVDD Analog bypass pin voltage 6 V VVCOM Common bypass pin voltage 2.5 V VVREG Regulator bypass pin voltage 5.5 V POWER-ON RESET (POR) VPOR VDD voltage for POR 2.1 2.7 V VPOR_HY VDD POR recovery hysteresis voltage 0.5 V OVERTEMPERATURE (OT) PROTECTION OTW(i) Channel overtemperature warning 150 °C OTSD(i) Channel overtemperature shutdown 175 °C OTW Global junction overtemperature warning Set by register 0x01 bit 5-6, default value 130 °C OTSD Global junction overtemperature shutdown 160 °C OTHYS Overtemperature hysteresis 15 °C LOAD OVER CURRENT PROTECTION ILIM Overcurrent cycle-by-cycle limit OC Level 1 4 4.8 A OC Level 2 6 6.5 ISD Overcurrent shutdown OC Level 1, Any short to supply, ground, or other channels 7 A OC Level 2, Any short to supply, ground, or other channels 9 MUTE MODE GMUTE Output attenuation 100 dB CLICK AND POP VCP Output click and pop voltage ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z 7 mV DC OFSET VOFFSET Output offset voltage 2 5 mV DC DETECT DCFAULT Output DC fault protection 2 2.5 V DIGITAL OUTPUT PINS VOH Output voltage for logic level high I = ±2 mA 90 %VDD VOL Output voltage for logic level low I = ±2 mA 10 %VDD tDELAY_CLIPDET Signal delay when output clipping detected 20 μs LOAD DIAGNOSTICS S2P Maximum resistance to detect a short from OUT pins to PVDD 500 Ω S2G Maximum resistance to detect a short from OUT pins to ground 200 Ω SL Shorted load detection tolerance Other channels in Hi-Z ±0.5 Ω OL Open load Other channels in Hi-Z 40 70 Ω TDC_DIAG DC diagnostic time All 4 Channels 230 ms LO Line output 6 kΩ TLINE_DIAG Line output diagnostic time 40 ms ACIMP AC impedance accuracy Gain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω, 25% Offset ±0.5 Ω TAC_DIAG AC diagnostic time All 4 Channels 520 ms

SLOS948 – FEBRUARY 2019 www.ti.com Product Folder Links: TAS6424M-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 79 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2C_ADDR PINS tI2C_ADDR Time delay needed for I2C address set-up 300 μs (1) Tested with Output Inductor DFEG7030D-3R3M.

7.6 Timing Requirements

Test conditions (unless otherwise noted): TC = 25 °C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, PO = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 79 MIN TYP MAX UNIT I2C CONTROL PORT (See Figure 42) tBUS Bus free time between a STOP and START condition 1.3 μs tHOLD1 Hold time, SCL to SDA 0 ns tHOLD2 Hold time, start condition to SCL 0.6 μs tSTART I2C startup time after VDD power on reset 12 ms tRISE Rise time, SCL and SDA 300 ns tFALL Fall time, SCL and SDA 300 ns tSU1 Setup, SDA to SCL 100 ns tSU2 Setup, SCL to start condition 0.6 μs tSU3 Setup, SCL to stop condition 0.6 μs tW(H) Required pulse duration SCL High 0.6 μs tW(L) Required pulse duration SCL Low 1.3 μs SERIAL AUDIO PORT (See Figure 32) DMCLK, DSCLK Allowable input clock duty cycle 45% 50% 55% ƒMCLK Supported MCLK frequencies: 128, 256, or 512 128 512 xFS ƒMCLK_Max Maximum frequency 25 MHz tSCY SCLK pulse cycle time 40 ns tSCL SCLK pulse-with LOW 16 ns tSCH SCLK pulse-with HIGH 16 ns trise/fall Rise and fall time <5 ns tSF SCLK rising edge to FSYNC edge 8 ns tFS FSYNC rising edge to SCLK edge 8 ns tDS DATA set-up time 8 ns tDH DATA hold time 8 ns ci Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1, SDIN2 10 pF TLA Latency from input to output measured in FSYNC sample count FSYNC = 44.1 kHz or 48 kHz 30 FSYNC = 96 kHz 12

7.7 Typical Characteristics

Figure 1. Crosstalk vs Frequency Figure 2. PVDD PSRR vs Frequency Figure 3. VBAT PSRR vs Frequency PO = 1 W fSW = 384 kHz Figure 4. THD+N vs Frequency Figure 5. THD+N vs Frequency Figure 6. THD+N vs Frequency

1 W fSW = 384 kHz

Figure 19. PBTL THD+N vs Frequency Figure 20. PBTL THD+N vs Frequency Figure 21. PBTL THD+N vs Frequency Figure 22. PBTL THD+N vs Frequency Figure 23. PBTL THD+N vs Power Figure 24. PBTL THD+N vs Power

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8 Parameter Measurement Information

The parameters for the TAS6424M-Q1 device were measured using the circuit in Figure 79. For measurements with 2.1 MHz switching frequency the 3.3 µH inductor from the TAS6424M-Q1 EVM is used. For measurements with 384 kHz switching frequency a 10 µH inductor was used.

OUT_1P OUT_1M OUT_2P OUT_2M OUT_3P OUT_3M OUT_4P OUT_4M VREG I2C_ADDR1 I2C_ADDR0 SDA SCL I2C Control SDIN1 SDIN2 SCLK FSYNC MCLK Serial Audio Port PLL and Clock Management STANDBY WARN FAULT Digital Core Reference Regulators Gate Drive Regulator Channel 1 Powerstage Channel 2 Powerstage Channel 3 Powerstage Channel 4 Powerstage Volume Control -100 to +24 dB 0.5 dB steps Gate Drives Digital to PWM Clip Detection Closed Loop Class D Amplifier Overcurrent Limit Protection Overcurrent Overtemperature Overvoltage and Undervoltage DC Detection Short to GND DC Load Diagnostics Short to Power Open Load Shorted Load AC Load Diagnostics MUTE Copyright © 2016, Texas Instruments Incorporated TAS6424M-Q1 www.ti.com SLOS948 – FEBRUARY 2019 Product Folder Links: TAS6424M-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

9 Detailed Description

9.1 Overview

The TAS6424M-Q1 device is a four-channel digital-input Class-D audio amplifier specifically tailored for use in the in the automotive industry. The device is designed for vehicle battery operation. This ultra-efficient Class-D technology allows for reduced power consumption, reduced PCB area and reduced heat. The device realizes an audio sound-system design with smaller size and lower weight than traditional Class-AB solutions. The core design blocks are as follows:

• Serial audio port
• Clock management
• High-pass filter and volume control
• Pulse width modulator (PWM) with output stage feedback
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Serial Audio Port

The serial audio port (SAP) receives audio in either I2S, left justified, right justified, or TDM formats. Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04] section. Figure 31 shows the digital audio data connections for I2S and TDM8 mode for an eight channel system. Figure 31. Digital-Audio Data Connection

9.3.1.1 I2S Mode

complement form (MSB-first). The data is valid on the rising edge of the bit clock and is used to clock in the data.

9.3.1.2 Left-Justified Timing

9.3.1.3 Right-Justified Timing

rising edge of bit clock. The device pads the unused leading data-bit positions in the L/R frame with zeros.

9.3.1.4 TDM Mode

stream. The TDM mode supports 16-bit, 24-bit, and 32-bit input data lengths. SDIN2 pin (pin 16) to ground. Table 1 lists register settings for the TDM channel selection. Table 1. TDM Channel Selection If PBTL mode is programmed for channel 1/2 or channel 3/4 the datasource can be set according to Table 2. Table 2. TDM Channel Selection in PBTL Mode

9.3.1.5 Supported Clock Rates

The device supports MCLK rates of 128 × fS, 256 × fS, or 512 × fS. The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz. and 512x 50% duty is not required.

9.3.1.6 Audio-Clock Error Handling

returns to the state it was in. See the Timing Requirements table for timing requirements. Figure 32. Serial Audio Timing Figure 33. Left-Justified Audio Data Format

32 SCLK

Figure 34. I2S Audio Data Format Figure 35. TDM8 Audio Data Format

9.3.2 High-Pass Filter

approximately 8 Hz for 96 kHz sampling rates.

9.3.3 Volume Control and Gain

Each channel has an independent digital-volume control with a range from –100 dB to +24 dB with 0.5-dB steps. to optimize output noise and dynamic range performance.

9.3.4 High-Frequency Pulse-Width Modulator (PWM)

Table 3. Output Switch Frequency Option

9.3.5 Gate Drive

FET stage. The device uses proprietary techniques to optimize EMI and audio performance.

9.3.6 Power FETs

9.3.7 Load Diagnostics

available to function. DC Diagnostic results are reported for each channel separately through the I2C registers.

9.3.7.1 DC Load Diagnostics

channel has a load impedance greater than the limits in the Specifications section. Figure 36. DC Load Diagnostic Reporting Thresholds

9.3.7.2 Line Output Diagnostics

load is present as well. This test is not pop free, so if an external amplifier is connected it should be muted.

9.3.7.3 AC Load Diagnostics

be tested, the diagnostics should be run in series. The AC load-diagnostic test procedure is as follows.

9.3.7.3.1 Impedance Magnitude Measurement

1. Set the channels to be tested into the Hi-Z state.
2. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0.
3. Apply a full-scale input signal from the DSP for the tested channels with the desired frequency

(recommended 10 kHz to 20 kHz). The device ramps the signal up and down automatically to prevent pops and clicks.

1. Set the device into the AC diagnostic mode (set bit 3 through bit 0 as needed in register 0x15 to 1 for CH1 to
2. Read back the AC impedance (register 0x17 through register 0x1A).

mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.

Figure 37. AC Magnitude Calculation

9.3.7.3.2 Impedance Phase Reference Measurement

sequentially, they cannot be measured at the same time.

• BTL mode 1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode. 2. Apply a 0-dBFS 19 kHz signal and enable AC load diagnostics. CH1 and CH2 reuse the AC sensing loop of CH1 (set bit 3 in register 0x15 to 1). CH3, CH4 reuse the AC sensing loop of CH3 (set bit 1 in register 0x15 to 1). 3. Read back the 16bit hexadecimal, AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register 0x1C holds the LSB. 4. For channel 1/2 set bit 3 in register 0x15 to 0. For channel 3/4 set bit 1 in register 0x15 to 0.
• PBTL mode 1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode. 2. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 0 without toggling SDz pin to enter BTL mode only for load diagnostics. 3. Apply a 0 dBFS 19 kHz signal and enable AC load diagnostics. For PBTL_12, enable the AC sensing loop of CH1 (set bit 3 in register 0x15 to 1). For PBTL_34, enable the AC sensing loop of CH3 (set bit 1 in register 0x15 to 1). 4. Read back the AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register 0x1C holds the LSB. 5. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 1 to go back to PBTL mode for load diagnostics. 6. For PBTL_12 set bit 3 in register 0x15 to 0. For PBTL_34 set bit 1 in register 0x15 to 0. When the test is complete, the channel reporting register indicates the status change from the AC diagnostic mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.

9.3.7.3.3 Impedance Phase Measurement

in the same manner as the reference measurements, except the loopback is disabled in bit 7 register 0x16. be measured. Measure the channels sequentially as they cannot be measured at the same time.

• BTL mode 1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0 to disable AC loopback mode. 2. Apply a 0-dBFS 19 kHz signal and enable AC load diagnostics. CH1 and CH2 reuse the AC sensing loop of CH1 (set bit 3 in register 0x15 to 1). CH3, CH4 reuse the AC sensing loop of CH3 (set bit 1 in register 0x15 to 1). 3. Read back the 16bit hexadecimal, AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register 0x1C holds the LSB. 4. Read back the hexadecimal stimulus value, STI. Register 0x1D holds the MSB and register 0x1E holds

1. For channel 1/2 set bit 3 in register 0x15 to 0. For channel 3/4 set bit 1 in register 0x15 to 0.

diagnostic mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.

• PBTL mode 1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0 to disable AC loopback mode. 2. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 0 without toggling SDz pin to enter BTL mode only for load diagnostics. 3. Apply a 0 dBFS 19 kHz signal and enable AC load diagnostics. For PBTL_12, enable the AC sensing loop of CH1 (set bit 3 in register 0x15 to 1). For PBTL_34, enable the AC sensing loop of CH3 (set bit 1 in register 0x15 to 1). 4. Read back the AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register 0x1C holds the LSB. 5. Read back the hexadecimal stimulus value, STI. Register 0x1D holds the MSB and register 0x1E holds the LSB 6. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 1 to go back to PBTL mode for load diagnostics. 7. For PBTL_12 set bit 3 in register 0x15 to 0. For PBTL_34 set bit 1 in register 0x15 to 0. The AC phase in degrees is calculated with the following equation:

Figure 38. AC Phase Calculation

• Phase_CHx(LBK) is the reference phase measurement. LBK stands for loopback mode
• Phase_CHx(LDM) is the phase measure of the load. LDM stands for load mode
• STI_CHx(LDM) is the stimulus value

Table 4. AC Impedance Code to Magnitude

9.3.8 Protection and Monitoring

9.3.8.1 Overcurrent Limit (ILIMIT)

Miscellaneous Control 1 register (address 0x01).

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9.3.8.2 Overcurrent Shutdown (ISD)

If the output load current reaches ISD, such as an output short to GND, then a peak current limit occurs, which shuts down the channel. The time to shutdown the channel varies depending on the severity of the short condition. The affected channel is placed into the Hi-Z state, the fault is reported to the register, and the FAULT pin is asserted. The device will remain in this state until the CLEAR FAULT bit is set in Miscellaneous Control 3 Register, 0x21 bit 7. After clearing this bit and if the diagnostics are enabled, the device will automatically start diagnostics on the channel and, if no load failure is found, the device will restart. If a load fault is found the device continues to rerun the diagnostics once per second. Because this hiccup mode uses the diagnostics, no high current is created. If the diagnostics are disabled, the device sets the state for that channel to Hi-Z and requires the MCU to take the appropriate action, setting the CLEAR FAULT bit after the fault got removed, in order to return to Play state. Two programable levels can be set by bit 4 in the Miscellaneous Control 1 register (address 0x01).

9.3.8.3 DC Detect

This circuit detects a DC offset continuously during normal operation at the output of the amplifier. If the DC offset exceeds the threshold, that channel is placed in the Hi-Z state, the fault is reported to the I2C register, and the FAULT pin is asserted. A register bit can be used to mask reporting to the FAULT pin if required.

9.3.8.4 Clip Detect

The clip detect is reported on the WARN pin if 100% duty-cycle PWM is reached for a minimum number of PWM cycles set by the Clip Wndow Register (address 0x23). The default is 20 PWM cycles. If any channel is clipping, the clipping is reported to the pin. The clip detect is latched and can be cleared by I2C. Masking the clip reporting to the pin is possible through I2C.

9.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)

Four overtemperature warning levels are available in the device (see the Register Maps section for thresholds). When the junction temperature exceeds the warning level, the WARN pin is asserted, unless the mask bit has been set to disable reporting. The device functions until the OTSD value is reached at which point all channels are placed in the Hi-Z state, and the FAULT pin is asserted. When the junction temperature returns to normal levels, the device automatically recovers and places all channels into the state indicated by the register settings.

9.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]

In addition to the global OTW, each channel also has an individual overtemperature warning and shutdown. If a channel exceeds the OTW(i) threshold, the warning register bit is set as the WARN pin is asserted, unless the mask bit has been set to disable reporting. If the channel temperature exceeds the OTSD(i) threshold then that channel goes to the Hi-Z state until the temperature drops below the OTW(i) threshold. At this point, the channel goes to the state indicated by the state control register.

9.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)

The undervoltage (UV) protection detects low voltages on the PVDD and VBAT pins. In the event of an UV condition, the FAULT pin is asserted, and the I2C register is updated. A power-on reset (POR) on the VDD pin causes the I2C to goes to the high-impedance (Hi-Z) state, and all registers are reset to default values. At power- on or after a POR event, the POR warning bit and WARN pin are asserted.

9.3.8.8 Overvoltage (OV) and Load Dump

The overvoltage (OV) protection detects high voltages on the PVDD pin. If the PVDD pin reaches the OV threshold, the FAULT pin is asserted and the I2C register is updated. The device can withstand 40 V load-dump voltage spikes.

9.3.9 Power Supply

The device has three power supply inputs, VDD, PVDD, and VBAT, which are described as follows: VDD This pin is a 3.3V supply pin that provides power to the low voltage circuitry. VBAT This pin is a higher voltage supply that can be connected to the vehicle battery or the regulated voltage rail in a boosted system within the recommended limits. For best performance, this rail

supply voltage. This supply rail is used for higher voltage analog circuits but not the output FETs. second ground path through the body diode in the output FETs.

9.3.9.1 Vehicle-Battery Power-Supply Sequence

the STANDBY pin high. As reference, please see Figure 40. Figure 39. Power-Up Sequence Option 1 Figure 40. Power-Up Sequence Option 2

SLOS948 – FEBRUARY 2019 www.ti.com Product Folder Links: TAS6424M-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Power-Down Sequence When removing power from the device, TI recommends to deassert the VBAT and PVDD supplies together first, which provides the lowest click and pop performance, and VDD last. During powering down, VDD must remain available for at least 1.01s after all output stages got set to Hi-Z. To shorten this required delay to 46ms, a 20kOhm parallel resistor between AVDD and AVSS can be added.

9.3.9.2 Boosted Power-Supply Sequence

In this scenario, the VBAT and PVDD inputs are not connected to the same supply. During power-up, PVDD should be supplied last while during power-down PVDD should be removed first. All other recommendation apply as described in Vehicle-Battery Power-Supply Sequence.

9.3.10 Hardware Control Pins

The device has four pins for control and device status: FAULT, MUTE, WARN, and STANDBY.

9.3.10.1 FAULT

The FAULT pin reports faults and is active low under any of the following conditions:

• Any channel faults (overcurrent or DC detection)
• Overtemperature shutdown
• Overvoltage or undervoltage conditions on the VBAT or PVDD pins
• Clock errors The FAULT pin is deactivated when none of the previously listed conditions exist. Register bits are available to mask fault categories from reporting to the FAULT pin. These bits only mask the setting of the pin and do not affect the register reporting or protection of the device. By default all faults are reported to the pin. See the Register Maps section for a description of the mask settings. This pin is an open-drain output with an internal 100 kΩ pullup resistor to VDD.

9.3.10.2 WARN

This active-low output pin reports audio clipping, overtemperature warnings, and POR events. Clipping is reported if any channel is at the maximum modulation for 20 consecutive PWM clocks which results in a 10-µs delay to report the onset of clipping. The warning bit is sticky and can be cleared by the CLEAR FAULT bit (bit 7) in register 0x21. An overtemperature warning (OTW) is reported if the general temperature or any of the channel temperature warnings are set. The warning temperature can be set through bits 5 and 6 in register 0x01. Register bits are available to mask either clipping or OTW reporting to the pin. These bits only mask the setting of the pin and do not affect the register reporting. By default both clipping and OTW are reported. The WARN pin is latched and can be cleared by writing the CLEAR FAULT bit (bit 7) in register 0x21. This pin is an open-drain output with an internal 100 kΩ pullup resistor to VDD.

9.3.10.3 MUTE

This active-low input pin is used for hardware control of the mute and unmute function for all channels. This pin has a 100 kΩ internal pulldown resistor.

9.3.10.4 STANDBY

When this active-low input pin is asserted, the device goes into shutdown and current draw is limited. This pin can be used to shut down the device rapidly. The outputs are ramped down in less than 5 ms if the device is not already in the Hi-Z state. This pin has a 100 kΩ internal pulldown resistor.

9.4 Device Functional Modes

9.4.1 Operating Modes and Faults

The operating modes and faults are listed in the following tables. Table 5. Operating Modes Table 6. Global Faults and Actions Table 7. Channel Faults and Actions

9.5 Programming

9.5.1 I2C Serial Communication Bus

or run diagnostics. For a complete list and description of all I2C controls, see the Register Maps section. additional bus switching hardware. The I2C ADDRx pins set the slave address of the device as listed in Table 8. Table 8. I2C Addresses

9.5.2 I2C Bus Protocol

insertion. The control interface is used to program the registers of the device and to read device status. device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Figure 41. Typical I2C Sequence

Figure 42. SCL and SDA Timing single-byte or multiple-byte data transfers.

9.5.3 Random Write

bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer. Figure 43. Random Write Transfer

9.5.4 Sequential Write

responds with an acknowledge bit and the I2C subaddress is automatically incremented by one. Figure 44. Sequential Write Transfer

9.5.5 Random Read

single-byte data-read transfer. Figure 45. Random Read Transfer

9.5.6 Sequential Read

by a stop condition to complete the transfer. Figure 46. Sequential Read Transfer

9.6 Register Maps

Table 9. I2C Address Register Definitions

9.6.1 Mode Control Register (address = 0x00) [default = 0x00]

The Mode Control register is shown in Figure 47 and described in Table 10. Figure 47. Mode Control Register Table 10. Mode Control Field Descriptions

7 RESET R/W 0 0: Normal operation

1: Resets the device. Self-clearing, will read back 0.

6 RESERVED R/W 0 RESERVED

5 PBTL CH34 R/W 0 0: Channels 3 and 4 are in BTL mode

4 PBTL CH12 R/W 0 0: Channels 1 and 2 are in BTL mode

3 CH1 LO MODE R/W 0 0: Channel 1 is in normal/speaker mode

2 CH2 LO MODE R/W 0 0: Channel 2 is in normal/speaker mode

1 CH3 LO MODE R/W 0 0: Channel 3 is in normal/speaker mode

0 CH4 LO MODE R/W 0 0: Channel 4 is in normal/speaker mode

9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]

The Miscellaneous Control 1 register is shown in Figure 48 and described in Table 11. Figure 48. Miscellaneous Control 1 Register Table 11. Misc Control 1 Field Descriptions

7 HPF BYPASS R/W 0 0: High pass filter eneabled

4 OC CONTROL R/W 1 0: Overcurrent is level 1

Table 11. Misc Control 1 Field Descriptions (continued)

9.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]

The Miscellaneous Control 2 register is shown in Figure 49 and described in Table 12. Figure 49. Miscellaneous Control 2 Register Table 12. Misc Control 2 Field Descriptions

7 RESERVED 0

3 RESERVED 0 0

2 SDM_OSR R/W 0 0: 64x OSR

9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]

The SAP Control (serial audio-port control) register is shown in Figure 50 and described in Table 13. Figure 50. SAP Control Register Table 13. SAP Control Field Descriptions

Table 13. SAP Control Field Descriptions (continued)

4 TDM SLOT SIZE R/W 0 0: TDM slot size is 24-bit or 32-bit

3 TDM SLOT SELECT 2 R/W 0 0: Normal

9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]

The Channel State Control register is shown in Figure 51 and described in Table 14. Figure 51. Channel State Control Register Table 14. Channel State Control Field Descriptions

9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]

The Channel 1 Through 4 Volume Control registers are shown in Figure 52 and described in Table 15. Figure 52. Channel x Volume Control Register Table 15. Ch x Volume Control Field Descriptions

9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]

The DC Diagnostic Control 1 register is shown in Figure 53 and described in Table 16. Figure 53. DC Load Diagnostic Control 1 Register Table 16. DC Load Diagnostics Control 1 Field Descriptions

7 DC LDG ABORT R/W 0 0: Default state, clear after abort

1 LDG LO ENABLE R/W 0 0: Line output diagnostics are disabled

0 LDG BYPASS R/W 0 0: Automatic diagnostics when leaving Hi-Z and after

9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]

The DC Diagnostic Control 2 register is shown in Figure 54 and described in Table 17. Figure 54. DC Load Diagnostic Control 2 Register

Table 17. DC Load Diagnostics Control 2 Field Descriptions

9.6.9 DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]

The DC Diagnostic Control 3 register is shown in Figure 55 and described in Table 18. Figure 55. DC Load Diagnostic Control 3 Register Table 18. DC Load Diagnostics Control 3 Field Descriptions

9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]

DC Load Diagnostic Report 1 register is shown in Figure 56 and described in Table 19. Figure 56. DC Load Diagnostic Report 1 Register Table 19. DC Load Diagnostics Report 1 Field Descriptions

7 CH1 S2G R 0 0: No short-to-GND detected

Table 19. DC Load Diagnostics Report 1 Field Descriptions (continued)

6 CH1 S2P R 0 0: No short-to-power detected

5 CH1 OL R 0 0: No open load detected

4 CH1 SL R 0 0: No shorted load detected

3 CH2 S2G R 0 0: No short-to-GND detected

2 CH2 S2P R 0 0: No short-to-power detected

1 CH2 OL R 0 0: No open load detected

0 CH2 SL R 0 0: No shorted load detected

9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]

The DC Load Diagnostic Report 2 register is shown in Figure 57 and described in Table 20. Figure 57. DC Load Diagnostic Report 2 Register Table 20. DC Load Diagnostics Report 2 Field Descriptions

7 CH3 S2G R 0 0: No short-to-GND detected

6 CH3 S2P R 0 0: No short-to-power detected

5 CH3 OL R 0 0: No open load detected

4 CH3 SL R 0 0: No shorted load detected

3 CH4 S2G R 0 0: No short-to-GND detected

2 CH4 S2P R 0 0: No short-to-power detected

1 CH4 OL R 0 0: No open load detected

0 CH4 SL R 0 0: No shorted load detected

9.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]

The DC Load Diagnostic Report, Line Output, register is shown in Figure 58 and described in Table 21. Figure 58. DC Load Diagnostics Report 3 Line Output Register Table 21. DC Load Diagnostics Report 3 Line Output Field Descriptions

3 CH1 LO LDG R 0 0: No line output detected on channel 1

2 CH2 LO LDG R 0 0: No line output detected on channel 2

1 CH3 LO LDG R 0 0: No line output detected on channel 3

0 CH4 LO LDG R 0 0: No line output detected on channel 4

9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]

The Channel State Reporting register is shown in Figure 59 and described in Table 22. Figure 59. Channel State-Reporting Register Table 22. State-Reporting Field Descriptions

9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]

The Channel Faults (overcurrent, DC detection) register is shown in Figure 60 and described in Table 23. Figure 60. Channel Faults Register Table 23. Channel Faults Field Descriptions

7 CH1 OC R 0 0: No overcurrent fault detected

6 CH2 OC R 0 0: No overcurrent fault detected

5 CH3 OC R 0 0: No overcurrent fault detected

4 CH4 OC R 0 0: No overcurrent fault detected

3 CH1 DC R 0 0: No DC fault detected

2 CH2 DC R 0 0: No DC fault detected

1 CH3 DC R 0 0: No DC fault detected

0 CH4 DC R 0 0: No DC fault detected

9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]

The Global Faults 1 register is shown in Figure 61 and described in Table 24. Figure 61. Global Faults 1 Register Table 24. Global Faults 1 Field Descriptions

4 INVALID CLOCK R 0 0: No clock fault detected

3 PVDD OV R 0 0: No PVDD overvoltage fault detected

2 VBAT OV R 0 0: No VBAT overvoltage fault detected

1 PVDD UV R 0 0: No PVDD undervoltage fault detected

Table 24. Global Faults 1 Field Descriptions (continued)

0 VBAT UV R 0 0: No VBAT undervoltage fault detected

9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]

The Global Faults 2 register is shown in Figure 62 and described in Table 25. Figure 62. Global Faults 2 Register Table 25. Global Faults 2 Field Descriptions

4 OTSD R 0 0: No global overtemperature shutdown

3 CH1 OTSD R 0 0: No overtemperature shutdown on Ch1

2 CH2 OTSD R 0 0: No overtemperature shutdown on Ch2

1 CH3 OTSD R 0 0: No overtemperature shutdown on Ch3

0 CH4 OTSD R 0 0: No overtemperature shutdown on Ch4

9.6.17 Warnings Register (address = 0x13) [default = 0x20]

The Warnings register is shown in Figure 63 and described in Table 26. Figure 63. Warnings Register Table 26. Warnings Field Descriptions

5 VDD POR R 0 0: No VDD POR has occurred

1 VDD POR occurred

4 OTW R 0 0: No global overtemperature warning

3 OTW CH1 R 0 0: No overtemperature warning on channel 1

2 OTW CH2 R 0 0: No overtemperature warning on channel 2

Table 26. Warnings Field Descriptions (continued)

1 OTW CH3 R 0 0: No overtemperature warning on channel 3

0 OTW CH4 R 0 0: No overtemperature warning on channel 4

9.6.18 Pin Control Register (address = 0x14) [default = 0x00]

The Pin Control register is shown in Figure 64 and described in Table 27. Figure 64. Pin Control Register Table 27. Pin Control Field Descriptions

7 MASK OC R/W 0 0: Report overcurrent faults on the FAULT pin

6 MASK OTSD R/W 0 0: Report overtemperature faults on the FAULT pin

5 MASK UV R/W 0 0: Report undervoltage faults on the FAULT pin

4 MASK OV R/W 0 0: Report overvoltage faults on the FAULT pin

3 MASK DC R/W 0 0: Report DC faults on the FAULT pin

2 MASK ILIMIT R/W 0 0: Report Ilimit on the FAULT pin

1 MASK CLIP R/W 0 0: Report clipping on the WARN pin

0 MASK OTW R/W 0 0: Report overtemperature warnings on the WARN pin

9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]

The AC Load Diagnostic Control 1 register is shown in Figure 65 and described in Table 28. Figure 65. AC Load Diagnostic Control 1 Register Table 28. AC Load Diagnostic Control 1 Field Descriptions

7 CH1, CH2, PBTL12: GAIN R/W 0 0: Gain 1

6 RESERVED R/W 0 0

Table 28. AC Load Diagnostic Control 1 Field Descriptions (continued)

5 CH3, CH4, PBTL34: GAIN R/W 0 0: Gain 1

4 RESERVED R/W 0 0

3 CH1 ENABLE R/W 0 0: AC diagnostics disabled

2 CH2 ENABLE R/W 0 0: AC diagnostics disabled

1 CH3 ENABLE R/W 0 0: AC diagnostics disabled

0 CH4 ENABLE R/W 0 0: AC diagnostics disabled

9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]

The AC Load Diagnostic Control 2 register is shown in Figure 66 and described in Table 29. Figure 66. AC Load Diagnostic Control 2 Register Table 29. AC Load Diagnostic Control 2 Field Descriptions

7 AC_DIAGS_LOOPBACK R/W 0 0: Disable AC Diag loopback

4 AC TIMING R/W 0 0: 32 Cycles

9.6.21 AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17–0x1A)

The AC Load Diagnostic Report Ch1 through CH4 registers are shown in Figure 67 and described in Table 30. Figure 67. AC Load Diagnostic Impedance Report Chx Register

Table 30. Chx AC LDG Impedance Report Field Descriptions

9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]

The AC Load Diagnostic Phase High value registers are shown in Figure 68 and described in Table 31. Figure 68. AC Load Diagnostic (LDG) Phase High Report Register Table 31. AC LDG Phase High Report Field Descriptions

9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]

The AC Load Diagnostic Phase Low value registers are shown in Figure 69 and described in Table 32. Figure 69. AC Load Diagnostic (LDG) Phase Low Report Register Table 32. AC LDG Phase Low Report Field Descriptions

9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]

The AC Load Diagnostic STI High value registers are shown in Figure 70 and described in Table 33. Figure 70. AC Load Diagnostic (LDG) STI High Report Register Table 33. AC LDG STI High Report Field Descriptions

9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]

The AC Load Diagnostic STI Low value registers are shown in Figure 71 and described in Table 34. Figure 71. AC Load Diagnostic (LDG) STI Low Report Register Table 34. Chx AC LDG STI Low Report Field Descriptions

9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]

The Miscellaneous Control 3 register is shown in Figure 72 and described in Table 35. Figure 72. Miscellaneous Control 3 Register Table 35. Misc Control 3 Field Descriptions

7 CLEAR FAULT R/W 0 0: Normal operation

6 PBTL_CH_SEL R/W 0 0: PBTL normal signal source

5 MASK ILIMIT WARNING R/W 0 0: Report ILIMIT on the WARN pin

4 RESERVED R/W 0

3 OTSD AUTO RECOVERY R/W 0 0: OTSD is latched

9.6.27 Clip Control Register (address = 0x22) [default = 0x01]

and Clip Warning Register (address = 0x24) [default = 0x00] must be set accordingly. Figure 73. Clip Control Register Table 36. Clip Control Field Descriptions

0 CLIPDET_EN R/W 1 0: Clip detect disable

9.6.28 Clip Window Register (address = 0x23) [default = 0x14]

minimum number of 100% duty-cycle PWM cycles in hexadecimal notation before Clip Detect is reported. Figure 74. Clip Window Register Table 37. Clip Window Field Descriptions

9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]

The Clip Window register is shown in Figure 75 and described in Table 38. Figure 75. Clip Warning Register Table 38. Clip Warning Field Descriptions

3 CH4_CLIP R 0 0: No Clip Detect

2 CH3_CLIP R 0 0: No Clip Detect

1 CH2_CLIP R 0 0: No Clip Detect

0 CH1_CLIP R 0 0: No Clip Detect

9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]

The ILIMIT Status register is shown in Figure 76 and described in Table 39. Figure 76. ILIMIT Status Register Table 39. ILIMIT Status Field Descriptions

3 CH4_ILIMIT_WARN R 0 0: No ILIMIT

2 CH3_ILIMIT_WARN R 0 0: No ILIMIT

Table 39. ILIMIT Status Field Descriptions (continued)

1 CH2_ILIMIT_WARN R 0 0: No ILIMIT

0 CH1_ILIMIT_WARN R 0 0: No ILIMIT

9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]

The Miscellaneous Control 4 register is shown in and described in Table 40. Figure 77. Miscellaneous Control 4 Register Table 40. Misc Control 4 Field Descriptions

www.ti.com SLOS948 – FEBRUARY 2019 Product Folder Links: TAS6424M-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The TAS6424M-Q1 is a four-channel class-D digital-input audio-amplifier design for use in automotive head units and external amplifier modules. The TAS6424M-Q1 incorporates the necessary functionality to perform in demanding OEM applications.

10.1.1 AM-Radio Band Avoidance

AM-radio frequency interference can be avoided by setting the switching frequency of the device above the AM band. The switching frequency options available are 38 fs, 44 fs, and 48 fs. If the switch frequency cannot be set above the AM band, then use the two options of 8 fs and 10 fs. These options should be changed to avoid AM active channels.

10.1.2 Parallel BTL Operation (PBTL)

The device can drive more current-paralleling BTL channels on the load side of the LC output filter. For parallel operation, the parallel BTL mode, PBTL, must be used and the paralleled channels must have the same state in the state control register. If the two states are not aligned the device reports a fault condition. To set the requested channels to PBTL mode the device must be in standby mode for the commands to take effect. A load diagnostic is supported for PBTL channels. Paralleling on the device side of the LC output filter is not supported.

10.1.3 Demodulation Filter Design

The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These transistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. An LC demodulation filter is used to recover the audio signal. The filter attenuates the high-frequency components of the output signals that are out of the audio band. The design of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, to meet the system THD+N requirements, the selection of the inductors used in the output filter should be carefully considered.

10.1.4 Line Driver Applications

In many automotive audio applications, the same head unit must drive either a speaker (with several ohms of impedance) or an external amplifier input (with several kiloohms of impedance). The design is capable of supporting both applications and has special line-drive gain and diagnostics. Coupled with the high switching frequency, the device is well suited for this type of application. Set the desired channel in line driver mode through I2C register 0x00, the externally connected amplifier must have a differential impedance from 600 Ω to 4.7 kΩ for the DC line diagnostic to detect the connected external amplifier. Figure 78 shows the recommended external amplifier input configuration.

Figure 78. External Amplifier Input Configuration for Line Driver

10.2 Typical Applications

10.2.1 BTL Application

Figure 79 shows the schematic of a typical 4-channel solution for a head-unit application. Figure 79. TAS6424M-Q1 Typical 4-Channel BTL Application Schematic

SLOS948 – FEBRUARY 2019 www.ti.com Product Folder Links: TAS6424M-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Typical Applications (continued)

10.2.1.1 Design Requirements

Use the following requirements for this design:

• This head-unit example is focused on the smallest solution size for 4 × 50 W output power into 2 Ω with a battery supply of 14.4 V.
• The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which results in a frequency of 2.11 MHz.
• The selection of a 2.11 MHz switch frequency enables the use of a small output inductor value of 3.3 µH which leads to a very small solution size.

10.2.1.2 Communication

All communications to the TAS6424M-Q1 are through the I2C protocol. A system controller can communicate with the device through the SDA pins and SCL pins. The TAS6424M-Q1 is an I2C slave device and requires a master. The device cannot generate an I2C clock or initiate a transaction. The maximum clock speed accepted by the device is 400 kHz. If multiple TAS6424M-Q1 devices are on the same I2C bus, the I2C address must be different for each device. Up to four TAS6424M-Q1 devices can be on the same I2C bus. The I2C bus is shared internally. NOTE Complete any internal operations, such as load diagnostics, before reading the registers for the results.

10.2.1.3 Detailed Design Procedure

10.2.1.3.1 Hardware Design

Use the following procedure for the hardware design:

• Determine the input format. The input format can be either I2S or TDM mode. The mode determines the correct pin connections and the I2C register settings.
• Determine the power output that is required into the load. The power requirement determines the required power-supply voltage and current. The output reconstruction-filter components that are required are also driven by the output power.
• With the requirements, adjust the typical application schematic in Figure 79 for the input connections.

10.2.1.3.2 Digital Input and the Serial Audio Port

The TAS6424M-Q1 device supports four different digital input formats which are: I2S, Right Justified, Left Justified, and TDM mode. Depending on the format, the device can support 16, 18, 20, 24, and 32 bit data. The supported frequencies are 96 kHz, 48 kHz, and 44.1 kHz. Please see Table 13 for the I2C register, SAP Control, for the complete matrix to set up the serial audio port. NOTE Bits 3, 4, and 5 in this register are ignored in all input formats except for TDM. Setting up all the control registers to the system requirements should be done before the device is placed in Mute mode or Play mode. After the registers are setup, use bit 7 in register 0x21 to clear any faults. Then read the fault registers to make sure no faults are present. When no faults are present, use register 0x04 to place the device properly into play mode.

10.2.1.3.3 Bootstrap Capacitors

The bootstrap capacitors provide the gate-drive voltage of the upper N-channel FET. These capacitors must be sized appropriately for the system specification. A special condition can occur where the bootstrap may sag if the capacitor is not sized accordingly. The special condition is just below clipping where the PWM is slightly less than 100% duty cycle with sustained low-frequency signals. Changing the bootstrap capacitor value to 2.2 µF for driving subwoofers that require frequencies below 30 Hz may be necessary.

10.2.1.3.4 Output Reconstruction Filter

provided by the system design. The DCR of the inductor directly affects the output power of the system design. to 50 mΩ and for a 2 Ω system is 20 to 25 mΩ.

10.2.1.4 Application Curves

Figure 80. THD vs Output Power Figure 81. THD vs Frequency

10.2.2 PBTL Application

where high power into 2 Ω is required. Figure 82. TAS6424M-Q1 Typical 2-Channel PBTL Application Schematic all four channels for a one channel amplifier.

10.2.2.1 Design Requirements

• This head-unit example is focused on the smallest solution size for 2 x 50 W output power into 2 Ω with a battery supply of 14.4 V.
• The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which results in a frequency of 2.11 MHz.
• The selection of a 2.11 MHz switch frequency enables the use of a small output inductor value of 3.3 µH which leads to a very small solution size.

10.2.2.1.1 Detailed Design Procedure

register 0x21 controls the frame selection.

10.2.2.2 Application Curves

Figure 83. THD vs Output Power Figure 84. Frequency Response

11 Power Supply Recommendations

shown in the Recommended Operating Conditions table.

SLOS948 – FEBRUARY 2019 www.ti.com Product Folder Links: TAS6424M-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

12 Layout

12.1 Layout Guidelines

The pinout of the TAS6424M-Q1 was selected to provide flowthrough layout with all high-power connections on the right side, and all low-power signals and supply decoupling on the left side. Figure 85 shows the area for the components in the application example (see the Typical Applications section). The TAS6424M-Q1 EVM uses a four-layer PCB. The copper thickness was selected as 70 µm to optimize power loss. The small value of the output filter provides a small size and, in this case, the low height of the inductor enables double-sided mounting. The EVM PCB shown in Figure 85 is the basis for the layout guidelines.

12.1.1 Electrical Connection of Thermal pad and Heat Sink

For the DKQ package, the heat sink connected to the thermal pad of the device should be connected to GND. The heat slug must not be connected to any other electrical node.

12.1.2 EMI Considerations

Automotive-level EMI performance depends on both careful integrated circuit design and good system-level design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the design. The design has minimal parasitic inductances because of the short leads on the package which reduces the EMI that results from current passing from the die to the system PCB. Each channel also operates at a different phase. The design also incorporates circuitry that optimizes output transitions that cause EMI. For optimizing the EMI a solid ground layer plane is recommended, for a PCB design the fulfills the CISPR25 level 5 requirements, see the TAS6424M-Q1 EVM layout.

12.1.3 General Guidelines

The EVM layout is optimized for low noise and EMC performance. The TAS6424M-Q1 has an exposed thermal pad that is up, away from the PCB. The layout must consider an external heat sink. Refer to Figure 85 for the following guidelines:

• A ground plane, A, on the same side as the device pins helps reduce EMI by providing a very-low loop impedance for the high-frequency switching current.
• The decoupling capacitors on PVDD, B, are very close to the device with the ground return close to the ground pins.
• The ground connections for the capacitors in the LC filter, C, have a direct path back to the device and also the ground return for each channel is the shared. This direct path allows for improved common mode EMI rejection.
• The traces from the output pins to the inductors, D, should have the shortest trace possible to allow for the smallest loop of large switching currents.
• Heat-sink mounting screws, E, should be close to the device to keep the loop short from the package to ground.
• Many vias, F, stitching together the ground planes can create a shield to isolate the amplifier and power supply.

12.2 Layout Example

Figure 85. EVM Layout

12.3 Thermal Considerations

• RθJC of the TAS6424M-Q1
• Thermal resistance of the thermal interface material
• Thermal resistance of the heat sink The thermal resistance of the thermal interface material can be determined from the manufacturer’s value for the area thermal resistance (expressed in °Cmm2/W) and the area of the exposed metal package. For example, a typical, white, thermal grease with a 0.0254 mm (0.001 inch) thick layer is approximately 4.52°C mm2/W. The TAS6424M-Q1 in the DKQ package has an exposed area of 47.6 mm2. By dividing the area thermal resistance by the exposed metal area determines the thermal resistance for the thermal grease. The thermal resistance of the thermal grease is 0.094°C/W Table 41 lists the modeling parameters for one device on a heat sink. The junction temperature is assumed to be 115°C while delivering and average power of 10 watts per channel into a 4 Ω load. The thermal-grease example previously described is used for the thermal interface material. Use Equation 1 to design the thermal system.

Table 41. Thermal Modeling

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

• PurePath™ Console 3 Graphical Development Suite
• TAS6424-Q1 EVM User's Guide (SLOU453)

13.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

13.3 Community Resources

solve problems with fellow engineers. foster collaboration among engineers. Ask questions and receive answers in real-time.

13.4 Trademarks

PurePath, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

www.ti.com SLOS948 – FEBRUARY 2019 Product Folder Links: TAS6424M-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 2-Mar-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TAS6424MQDKQRQ1 ACTIVE HSSOP DKQ 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TAS 6424M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Mar-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS6424MQDKQRQ1 HSSOP DKQ 56 1000 367.0 367.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Mar-2019 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 10.67

10.03 TYP

54X 0.635 56X 0.37 0.17 17.15 0.25

0.13 TYP 0 - 8

0.08 0.00 8.661 8.611 5.533 5.483 2.475 2.240 NOTE 6 (2.29) 2.29 0.05 0.25 GAGE PLANE 1.02 0.51 A 18.54 18.29 NOTE 3 B 7.59 7.39 NOTE 4 PowerPAD HSSOP - 2.475 mm max heightDKQ0056A PLASTIC SMALL OUTLINE 4221870/D 01/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. The exposed thermal pad is designed to be attached to an external heatsink. 6. For clamped heatsink design, refer to overall package height above the seating plane as 2.325 +/- 0.075 and molded body thickness dimension. PowerPAD is a trademark of Texas Instruments. TM 1 56

0.13 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.000

www.ti.com EXAMPLE BOARD LAYOUT (9.5)

0.05 MAX

0.05 MIN

56X (1.9) 56X (0.4) 54X (0.635) (R0.05) TYP PowerPAD HSSOP - 2.475 mm max heightDKQ0056A PLASTIC SMALL OUTLINE 4221870/D 01/2019 SYMM SYMM SEE DETAILS LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:6X 28 29 TM NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 9. Size of metal pad may vary due to creepage requirement. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 56X (1.9) 56X (0.4) 54X (0.635) (9.5)(R0.05) TYP PowerPAD HSSOP - 2.475 mm max heightDKQ0056A PLASTIC SMALL OUTLINE 4221870/D 01/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. TM SYMM SYMM 28 29 SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE:6X

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