TAS5103DAP

TAS5102_1 TI | Alldatasheet

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VCC − Supply Voltage − V 5 10 15 20 25 PO − Output Power − W G009 THD+N = 1% THD+N = 10% f = 1 kHz R L = 8 Ω (BTL) Gain = 3 dB TAS5102 TAS5103 www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 20-W/15-W STEREO DIGITAL AMPLIFIER POWER STAGE A low-cost, high-fidelity audio system can be built using a TI chipset, comprising a modulator (e.g., W at 10% THD+N Into Ω BTL at V TAS5086) and the TAS5102/TAS5103. This system (With Heatsink for TAS5102) only requires a simple passive LC demodulation filter W at 10% THD+N Into Ω BTL at 15.5 V to deliver high-quality, high-efficiency audio for TAS5103 amplification with proven EMI compliance. These devices require two power supplies, at 3.3 V for W at 10% THD+N Into Ω BTL at V VREG, and up to V for PVDD. The >100-dB SNR (A-Weighted) TAS5102/TAS5103 does not require power-up 0.1% THD+N at W sequencing due to internal power-on reset. The efficiency of this digital amplifier is greater than 90% Thermally Enhanced Package: 32-pin HTSSOP into Ω which enables the use of smaller power DAD (TAS5102) Pad Up supplies and heatsinks. DAP (TAS5103) Pad Down The TAS5102/3 has an innovative protection system High-Efficiency Power Stage >90%) With integrated on chip, safeguarding the device against a 180-m Ω Output MOSFETs wide range of fault conditions that could damage the Wide PVDD Range from to 23V system. These safeguards are short-circuit protection, overcurrent protection, undervoltage protection, and Power-On Reset for Protection on Power Up overtemperature protection. The TAS5102/TAS5103 Without Any Power-Supply Sequencing has a new proprietary current-limiting circuit that Integrated Self-Protection Circuits Including reduces the possibility of device shutdown during Undervoltage, Overtemperature, Overcurrent, high-level music transients. Short Circuit BTL OUTPUT POWER Built-In Regulator for Gate Drive Supply vs SUPPLY VOLTAGE Error Reporting EMI Compliant When Used With Recommended System Design Televisions Mini/Micro Audio Systems DVD Receivers Home Theaters The TAS5102/TAS5103 are integrated stereo digital amplifier power stages with an advanced protection system. The TAS5102/TAS5103 are capable of driving an Ω bridge-tied load (BTL) at up to W/15 W per channel with low integrated noise at the output, low THD+N performance, and low idle power dissipation. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

OUT_B PVDD_A PGND_CD BST_A BST_C PGND_AB PGND_AB PVDD_B OUT_A BST_B PVDD_C PGND_CD OUT_C PVDD_D OUT_D BST_D OTW VREG FAUL T GVDD_AB PWM_B GND SSTIMER RESET AGND PWM_A PWM_C OC_ADJ PWM_D GVDD_CD OUT_C PVDD_D PGND_AB BST_D BST_B PGND_CD PGND_CD PVDD_C OUT_D BST_C PVDD_B PGND_AB OUT_B PVDD_A OUT_A BST_A PWM_D SSTIMER GVDD_CD PWM_A OC_ADJ FAUL T PWM_C PWM_B RESET GND OTW VREG AGND GVDD_AB MODE Selection Pins Package Heat Dissipation Ratings TAS5102 TAS5103 SLLS801A JUNE 2008 REVISED JUNE 2008 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The TAS5102/TAS5103 are available in a thermally enhanced package: TAS5102 Pad Up 32-pin HTSSOP PowerPAD package (DAD) TAS5103 Pad Down 32-pin HTSSOP PowerPAD package (DAP) DAD PACKAGE DAP PACKAGE (TOP VIEW) (TOP VIEW) Mode PWM INPUT OUTPUT CONFIGURATION PROTECTION SCHEME (1) AD/BD modulation channels BTL output BTL mode (2) (1) AD modulation channels BTL output BTL mode (2) Protection works similarly to BTL mode (2) Only (1) AD modulation channels SE output difference in SE mode is that OUT_X is Hi-Z instead of a pulldown through internal pulldown resistor. Reserved (1) The and naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific mode. (2) An overcurrent protection (OC) occurring on A or B causes all channels to shut down. An OC on C or D works similarly. Global errors like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels. PARAMETER TAS5102DAD TAS5103DAP R θ JC C/W) 1.69 1.69 R θ JA C/W) See Note (1) 23.5 (1) The TAS5102 package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the device with the pad exposed to ambient air as the only means for heat dissipation for higher power applications. For this reason, R θ JA a system parameter that characterizes the thermal treatment, is provided in the Application Information section of the data sheet. An example and discussion of typical system R θ JA values are provided in the Thermal Information section. This example provides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate the heat dissipation ratings for a specific application. TI application engineering provides technical support to design heatsinks if needed. Also, for additional general information on PowerPad packages, see TI document SLMA002 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

(1) TAS5102 TAS5103 www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 over operating free-air temperature range (unless otherwise noted) UNIT PVDD_X to GND_X DC -0.3 to V PVDD_X to GND_X (2) 0.3 to V OUT_X to GND_X (2) 0.3 to V BST_X to GND_X (2) 0.3 to 43.2 V VREG to AGND 0.3 to 4.2 V GVDD to GND -0.3 to 13.2 V GND_X to GND 0.3 to 0.3 V GND_X to AGND 0.3 to 0.3 V GND to AGND 0.3 to 0.3 V PWM_X, OC_ADJ, M1, to AGND 0.3 to 4.2 V RESET_X FAULT OTW to AGND 0.3 V to V Maximum continuous sink current FAULT OTW) mA T J Maximum operating junction temperature range, to 150 C T STG Storage temperature range to 150 C Minimum pulse duration, low ns (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) These voltages represent the dc voltage peak ac waveform measured at the terminal of the device in all conditions. ORDERING INFORMATION T A PACKAGE (1) C to C TAS5103DAP 32-pin HTSSOP (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5102 TAS5103

www.ti.com Pin Functions PIN FUNCTION (1) NO. NO AGND P Analog ground BST_A P HS bootstrap supply (BST). External capacitor to OUT_A required. BST_B P HS bootstrap supply (BST). External capacitor to OUT_B required. BST_C P HS bootstrap supply (BST). External capacitor to OUT_C required. BST_D P HS bootstrap supply (BST). External capacitor to OUT_D required. FAULT O Device error signal (shutdown); open drain GND P Ground PGND_AB P Power ground for half-bridges A and B PGND_AB P Power ground for half-bridges A and B PGND_CD P Power ground for half-bridges C and D PGND_CD P Power ground for half-bridge D GVDD_AB P Gate-drive voltage supply. Requires µ F capacitor to GND. GVDD_CD P Gate-drive voltage supply. Requires µ F capacitor to GND. Mode selection connect to either AGND or VREG, no pull-up or pull-down I resistors Mode selection connect to either AGND or VREG, no pull-up or pull-down I resistors OC_ADJ O Analog overcurrent programming. Requires resistor to ground. OTW O Overtemperature warning signal, push-pull, active high OUT_A O Output, half-bridge A OUT_B O Output, half-bridge B OUT_C O Output, half-bridge C OUT_D O Output, half-bridge D Power supply input for half-bridge Requires close decoupling of 0.1- µ F PVDD_A P capacitor to GND_A. Power supply input for half-bridge Requires close decoupling of 0.1- µ F PVDD_B P capacitor to GND_B. Power supply input for half-bridge Requires close decoupling of 0.1- µ F PVDD_C P capacitor to GND_C. Power supply input for half-bridge Requires close decoupling of 0.1- µ F PVDD_D P capacitor to GND_D. PWM_A I Input signal for half-bridge A PWM_B I Input signal for half-bridge B PWM_C I Input signal for half-bridge C PWM_D I Input signal for half-bridge D RESET I PWM is not active if RESET goes low. Controls start/stop time of PWM modulation. Requires 2.2 nF capacitor to GND SSTIMER I for AD BTL. Leave pin floating (NC) for BD BTL mode. Also, leave pin floating (NC) for SE mode. VREG P Digital regulator supply filter. Requires 0.1- µ F capacitor to AGND. (1) I input, O output, P power Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

2nd-Order□L-C Output□Filter for□Each Half-Bridge Bootstrap Capacitors 2-Channel H-Bridge BTL Mode System Microcontroller OUT_A OUT_B OUT_C OUT_D BST_A BST_B BST_C BST_D RESET System Power Supply Hardwire Mode Control PVDD VREG GND Hardwire OC□Limit PVDD GVDD Power Supply Decoupling 8□V□-□23□V 3.3□V GND VAC PWM_A PWM_C PWM_D PWM_B VALID Left- Channel Output Right- Channel Output Input H-Bridge□1 Input H-Bridge□2 VREG Power□Supply Decoupling GND VREGAGND OC_ADJ Bootstrap Capacitors 2nd-Order□L-C Output□Filter for□Each Half-Bridge FAUL T OTW Output H-Bridge□2 Output H-Bridge□1 OTW FAULT TAS5508 GVDD_AB,□CD TAS5102 TAS5103 www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 SYSTEM BLOCK DIAGRAM Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5102 TAS5103

Temp. Sense VALID FAULT OTW AGND OC_ADJ VREG Power On Reset Under- voltage Protection GND PWM_D OUT_D GND_D PVDD_D BST_D Gate Drive PWM Rcv . Overload Protection Isense Protection and I/O□Logic PWM_C OUT_C GND_C PVDD_C BST_C Timing Gate DriveCtrl.PWM Rcv . GVDD_CD PWM_B OUT_B GND_B PVDD_B BST_B Timing Gate DriveCtrl.PWM Rcv . PWM_A OUT_A GND_A PVDD_A BST_A Timing Gate DriveCtrl.PWM Rcv . GVDD_AB Ctrl. BTL/PBTL−Configuration Pulldown Resistor BTL/PBTL−Configuration Pulldown□Resistor BTL/PBTL−Configuration Pulldown□Resistor BTL/PBTL−Configuration Pulldown□Resistor Internal□Pullup Resistors□to□VREG GVDD_CD Regulator GVDD_AB Regulator Timing TAS5102 TAS5103 SLLS801A JUNE 2008 REVISED JUNE 2008 www.ti.com FUNCTIONAL BLOCK DIAGRAM Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

(BTL) TAS5102 TAS5103 www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 MIN TYP MAX UNIT Half-bridge supply, PVDD_X DC supply voltage V V SS Supply for Protection and I/O Logic, VREG DC supply voltage 3.3 3.6 V R L (BTL) 6-8 Output filter: L µ C 470 nF. R L (SE) Load impedance Output AD modulation, switching 3-4 Ω frequency 350 kHz R L (PBTL) 3-4 L O (BTL) 200 Minimum output inductance under L O (SE) Output-filter inductance 200 nH short-circuit condition L O (PBTL) 200 F PWM PWM frame rate 192 384 432 kHz T J Junction temperature 125 C PVDD_X BTL mode, R L Ω R OC K Ω C BST 33-nF, audio frequency kHz, AES17 filter, F PWM 384 kHz, ambient temperature C (unless otherwise noted). Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PVDD 10% THD PVDD THD P O Power output per channel W PVDD 10% THD PVDD THD PVDD 18V, Po =10 W (half-power) 0.15 THD+N Total harmonic distortion noise PVDD 12V, Po =4.5 W (half-power) 0.18 W 0.05 V n Output integrated noise A-weighted µ V SNR Signal-to-noise ratio (1) A-weighted 105 dB A-weighted, input level dBFS using DNR Dynamic range 105 dB TAS5086 modulator P D Power dissipation due to idle losses (IPVDD_X) P O channels switching (2) 0.6 W (1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5102 TAS5103

(Single-Ended Output) TAS5102 TAS5103 SLLS801A JUNE 2008 REVISED JUNE 2008 www.ti.com PVDD_X SE mode, R L Ω R OC k Ω C BST 33-nF, audio frequency kHz, AES17 filter, F PWM 384 kHz, ambient temperature C (unless otherwise noted). Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PVDD 10% THD PVDD THD P O Power output per channel W PVDD 10% THD 4.5 PVDD THD PVDD 18V, Po W (half-power) 0.2 THD+ Total harmonic distortion noise N PVDD 12V, Po =2.25 W (half-power) 0.2 V n Output integrated noise A-weighted µ V SNR Signal-to-noise ratio (1) A-weighted 105 dB DNR Dynamic range A-weighted, input level dBFS using TAS5086 modulator 105 dB Power dissipation due to idle P D P O channels switching (2) 0.6 W losses (IPVDD_X) (1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 R L Ω F PWM 384 kHz (unless otherwise noted). All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal Voltage Regulator and Current Consumption V SS Digital Input Supply Voltage, VREG 3.3 3.6 V Operating, 50% duty cycle 6.5 I (VREG) Supply current, VREG mA Reset mode, no switching 6.5 50% duty cycle, without output filter or load I (PVDD_X) Total Half-bridge idle current mA Reset mode, no switching 6.3 Output Stage MOSFETs Drain-to-source resistance, LS T J includes metallization resistance 180 m Ω R DS(on) Drain-to-source resistance, HS T J includes metallization resistance 180 m Ω I/O Protection Undervoltage protection limit, GVDD_X, V uvp,G 5.7 V voltage rising Undervoltage protection limit, GVDD_X, V uvp,G 5.5 V voltage falling OTW (1) Overtemperature warning 125 C Temperature drop needed below OTW OTW HYST (1) temperature for OTW to be inactive after C the OTW event OTE (1) Overtemperature error 150 C OTE-OTW (1) OTE-OTW differential C A RESET must occur to exit shutdown OTE HYST (1) and to release FAULT following an OTE C event. OCPC Overcurrent protection counter F PWM 384 kHz 0.63 ms Resistor programmable, max. current, I OC Overcurrent limit protection 4.5 A R OCP k Ω I OCT Overcurrent response time 150 ns Resistor tolerance for typical value; the k Ω R OCP OC programming resistor range minimum resistance should not be less than 20k Ω Internal pulldown resistor at the output of Connected when RESET is active to provide R PD k Ω each half-bridge bootstrap capacitor charge. Not used in SE mode (1) Specified by design Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5102 TAS5103

f − Frequency − Hz VCC = 8 V R L = 8 Ω (BTL) Gain = 3 dB 100 1k 10k THD+N − Total Harmonic Distortion + Noise − % 0.001 20k 0.1 G001 PO = 0.5 W 0.01 PO = 1 W PO = 2.5 W f − Frequency − Hz VCC = 12 V R L = 8 Ω (BTL) Gain = 3 dB 100 1k 10k THD+N − Total Harmonic Distortion + Noise − % 0.001 20k 0.1 G002 PO = 0.5 W PO = 5 W 0.01 PO = 2.5 W TAS5102 TAS5103 SLLS801A JUNE 2008 REVISED JUNE 2008 www.ti.com DC Characteristics (continued) R L Ω F PWM 384 kHz (unless otherwise noted). All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Digital Specifications V IH High-level input voltage V PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, RESET V IL Low-level input voltage 0.8 V Static, High PWM_A, PWM_B, PWM_C, PWM_D, 100 M1, M2, RESET I lkg Input leakage current µ A Static, Low PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, RESET FAULT R INT_PU Internal pullup resistance, FAULT k Ω Internal pullup resistor 3.3 3.6 V OH High-level output voltage V External pullup of 4.7 k Ω to V 5.5 V OL Low-level output voltage I O mA 0.25 0.5 V TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY Figure Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

f − Frequency − Hz VCC = 18 V R L = 8 Ω (BTL) Gain = 3 dB 100 1k 10k THD+N − Total Harmonic Distortion + Noise − % 0.001 20k 0.1 G003 0.01 PO = 10 W PO = 5 W PO = 1 W PO − Output Power − W 0.01 VCC = 8 V R L = 8 Ω (BTL) Gain = 3 dB 0.1 1 10 THD+N − Total Harmonic Distortion + Noise − % 0.001 0.01 0.1 G004 f = 20 Hz f = 1 kHz f = 10 kHz PO − Output Power − W 0.01 VCC = 12 V R L = 8 Ω (BTL) Gain = 3 dB 0.1 1 10 THD+N − Total Harmonic Distortion + Noise − % 0.001 0.01 0.1 G005 f = 20 Hz f = 1 kHz f = 10 kHz PO − Output Power − W 0.01 VCC = 18 V R L = 8 Ω (BTL) Gain = 3 dB 0.1 1 10 THD+N − Total Harmonic Distortion + Noise − % 0.001 0.01 0.1 G006 f = 20 Hz f = 1 kHz f = 10 kHz TAS5102 TAS5103 www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY OUTPUT POWER Figure Figure TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER Figure Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5102 TAS5103

PO − Total Output Power − W 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 45 50 ICC − Supply Current − A G008 f = 1 kHz R L = 8 Ω (BTL) Gain = 3 dB VCC = 8 V VCC = 12 V VCC = 18 V PO − Output Power − W 100 0 5 10 15 20 25 Efficiency − % G007 f = 1 kHz R L = 8 Ω (BTL) Gain = 3 dB VCC = 18 VVCC = 12 V VCC = 8 V VCC − Supply Voltage − V 5 10 15 20 25 PO − Output Power − W G009 THD+N = 1% THD+N = 10% f = 1 kHz R L = 8 Ω (BTL) Gain = 3 dB −100 −90 −80 −70 −60 −50 −40 −30 −20 f − Frequency − Hz Crosstalk − dB G010 20 100 1k 10k 20k Left to Right Right to Left VCC = 18 V R L = 8 Ω (BTL) PO = 0.25 W Gain = 3 dB TAS5102 TAS5103 SLLS801A JUNE 2008 REVISED JUNE 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY SUPPLY CURRENT vs vs OUTPUT POWER TOTAL OUTPUT POWER Figure Figure OUTPUT POWER CROSSTALK vs vs SUPPLY VOLTAGE FREQUENCY Figure Figure 10. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

f − Frequency − Hz VCC = 12 V R L = 4 Ω (SE) Gain = 3 dB 100 1k 10k THD+N − Total Harmonic Distortion + Noise − % 0.001 20k 0.1 G011 0.01 PO = 2.5 W PO = 1 W PO = 0.5 W f − Frequency − Hz VCC = 18 V R L = 4 Ω (SE) Gain = 3 dB 100 1k 10k THD+N − Total Harmonic Distortion + Noise − % 0.001 20k 0.1 G012 0.01 PO = 2.5 W PO = 5 W PO = 0.5 W VCC − Supply Voltage − V 5 10 15 20 25 PO − Output Power − W G014 THD+N = 1% THD+N = 10% f = 1 kHz R L = 4 Ω (SE) Gain = 3 dB PO − Output Power − W 0.01 f = 1 kHz R L = 4 Ω (SE) Gain = 3 dB 0.1 1 10 THD+N − Total Harmonic Distortion + Noise − % 0.001 0.01 0.1 G013 VCC = 12 V VCC = 18 V TAS5102 TAS5103 www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY Figure 11. Figure 12. TOTAL HARMONIC DISTORTION NOISE OUTPUT POWER vs vs OUTPUT POWER SUPPLY VOLTAGE Figure 13. Figure 14. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5102 TAS5103

PO − Total Output Power − W 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ICC − Supply Current − A G015 f = 1 kHz R L = 4 Ω (SE) Gain = 3 dB VCC = 8 V VCC = 12 V VCC = 18 V VCC − Supply Voltage − V −100.0 −80.0 −60.0 −40.0 −20.0 0.0 A-W eighted Noise − dBv G016 f = 1 kHz R L = 4 Ω (SE) Gain = 3 dB −80 −70 −60 −50 −40 −30 −20 −10 f − Frequency − Hz Crosstalk − dB G018 20 100 1k 10k 20k Left to Right Right to Left R L = 4 Ω (SE) PO = 0.25 W Gain = 3 dB VCC = 18 V TAS5102 TAS5103 SLLS801A JUNE 2008 REVISED JUNE 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT A-WEIGHTED NOISE vs vs TOTAL OUTPUT POWER SUPPLY VOLTAGE Figure 15. Figure 16. CROSSTALK vs FREQUENCY Figure 17. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

*2200pF 50V *AD□mode□only . Leave□open□for□BD mode□and□SE . 0.1uF 16V 0.1uF 16V 1uF 16V 1uF 50V 0.1uF 50V 0.033uF 50V 0.033uF 50V 0.033uF 50V 0.033uF 50V 0.1uF 50V 0.1uF 50V 0.1uF 50V 1uF 50V 1uF 50V 10uH 10uH 10uH 10uH 0.47uF 50V 0.47uF 50V 0.47uF 50V 0.47uF 50V 3.3 3.3 3.3 3.3 10nF 50V 10nF 50V 10nF 50V 10nF 50V 220uF 35V 220uF 35V 330uF 35V 1uF 50V TAS5102 TAS5103 www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 Figure 18. Typical Differential (2N) BTL Application With AD Modulation Filters Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5102 TAS5103

*2200pF 50V *AD□mode□only . Leave□open□for□BD mode□and□SE . 0.1uF 16V 0.1uF 16V 1uF 16V 1uF 50V 0.1uF 50V 0.033uF 50V 0.033uF 50V 0.033uF 50V 0.033uF 50V 0.1uF 50V 0.1uF 50V 0.1uF 50V 1uF 50V 1uF 50V 10uH 10uH 10uH 10uH 0.47uF 50V 0.47uF 50V 0.47uF 50V 0.47uF 50V 3.3 3.3 3.3 3.3 10nF 50V 10nF 50V 10nF 50V 10nF 50V 220uF 35V 220uF 35V 330uF 35V 1uF 50V TAS5102 TAS5103 SLLS801A JUNE 2008 REVISED JUNE 2008 www.ti.com Figure 19. Typical Non-Differential (1N) BTL Application With AD Modulation Filters Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

(GVDD) SYSTEM POWER-UP/POWER-DOWN Powering Up TAS5102 TAS5103 www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to To facilitate system design, the TAS5102/3 needs each supply pin. It is recommended to follow the PCB only a 3.3-V supply in addition to the (typical) 18-V layout of the TAS5102/3 reference design. For power-stage supply. An internal voltage regulator additional information on recommended power supply provides suitable voltage levels for the gate drive and required components, see the application circuitry. Additionally, all circuitry requiring a floating diagrams given previously in this data sheet. voltage supply, e.g., the high-side gate drive, is The 3.3-V supply should be from a low-noise, accommodated by built-in bootstrap circuitry requiring low-output-impedance voltage regulator. Likewise, the only a few external capacitors. 18-V power-stage supply is assumed to have low In order to provide outstanding electrical and output impedance and low noise. The power-supply acoustical characteristics, the PWM signal path for sequence is not critical as facilitated by the internal the output stage is designed as identical, power-on-reset circuit. Moreover, the TAS5102/3 is independent half-bridges. For this reason, each fully protected against erroneous power-stage turnon half-bridge has separate bootstrap pins (BST_X), and due to parasitic gate charging. power-stage supply pins (PVDD_X). The gate drive voltages (GVDD_AB and GVDD_CD) are derived from the PVDD voltage. Separate, internal voltage regulators reduce and regulate the PVDD voltage to a The TAS5103 has an integrated gate drive supply, voltage appropriate for efficient gave drive operation. which eliminates the need for an external regulator. If Furthermore, an additional pin (VREG) is provided as the PVDD is V (i.e., max PVDD 13.2 V), it is supply for all common logic circuits. Special attention possible to connect the PVDD to the GVDD through a should be paid to placing all decoupling capacitors as ten ohm resistor. This will allow the power stage to close to their associated pins as possible. In general, operate as low a V during dips. Otherwise the inductance between the power supply pins and GVDD undervoltage protection will shutdown the decoupling capacitors must be avoided. (See outputs when the supply drops to Care must be reference board documentation for additional taken to not connect GVDD and PVDD together in information.) this manner if the operating voltage is higher than For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin SEQUENCE (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power- supply pin (GVDD_X) and the bootstrap pin. When The outputs of the H-bridges remain in a the power-stage output is high, the bootstrap high-impedance state until the internal gate-drive capacitor potential is shifted above the output supply voltage (GVDD_XY) and external VREG potential and thus provides a suitable voltage supply voltages are above the undervoltage protection (UVP) for the high-side gate driver. In an application with voltage threshold (see the Electrical Characteristics PWM switching frequencies in the range from 352 section of this data sheet). Although not specifically kHz to 384 kHz, it is recommended to use 33-nF required, it is recommended to hold RESET in a low ceramic capacitors, size 0603 or 0805, for the state while powering up the device. This allows an bootstrap supply. These 33-nF capacitors ensure internal circuit to charge the external bootstrap sufficient energy storage, even during minimal PWM capacitors by enabling a weak pulldown of the duty cycles, to keep the high-side power stage FET half-bridge output. The output impedance is (LDMOS) fully turned on during the remaining part of approximately Ω under this condition, unless mode the PWM cycle. In an application running at a (Single-ended Mode), is used. This means that reduced switching frequency, generally 192 kHz, the the TAS5102/3 should be held in reset for at least bootstrap capacitor might need to be increased in 200 µ S to ensure that the bootstrap capacitors are value. charged. This also assumes that the recommended 0.033- µ F bootstrap capacitors are used. Changes to Special attention should be paid to the power-stage bootstrap capacitor values will change the bootstrap power supply; this includes component selection, capacitor charge time. To avoid pops and clicks PCB placement, and routing. As indicated, each follow the recommended timing diagram in Figure half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5102 TAS5103

Transition□to□50%□duty□cycle and□hold□for□10□ms Transition□to□50%□duty□cycle and□hold□for□10□ms Powering Down ERROR REPORTING DEVICE PROTECTION SYSTEM TAS5102 TAS5103 SLLS801A JUNE 2008 REVISED JUNE 2008 www.ti.com When the TAS5102/3 is being used with TI PWM modulators such as the TAS5086, no special attention to the state of RESET is required, provided that the chipset is configured as recommended. Figure 20. Power-Down/Power-Up Timing Diagram Table (continued) FAULT OTW C and no faults (normal operation) above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of Junction temperature higher than this data sheet). Although not specifically required, it 125 C (overtemperature warning) is a good practice to hold RESET low during power Note that asserting either RESET low forces the down, thus preventing audible artifacts, including FAULT signal high, independent of faults being pops or clicks To avoid pops and clicks follow the present. TI recommends monitoring the OTW signal recommended timing diagram in Figure using the system microcontroller and responding to When the TAS5102/3 is being used with TI PWM an overtemperature warning signal by, e.g., turning modulators such as the TAS5086, no special down the volume to prevent further heating of the attention to the state of RESET is required, provided device, resulting in device shutdown (OTE). that the chipset is configured as recommended. To reduce external component count, an internal pullup resistor to 3.3 V is provided on the FAULT output. Level compliance for 5-V logic can be The FAULT pin is an active-low, open-drain output. obtained by adding external pullup resistors to V The OTW pin is a push-pull, active-high output. Their (see the Electrical Characteristics section of this data function is for protection-mode signaling to a PWM sheet for further specifications). controller or other system-control device. Any fault resulting in device shutdown is signaled by the FAULT pin going low. Likewise, OTW goes high The TAS5102/3 contains advanced protection when the device junction temperature exceeds 125 C circuitry carefully designed to facilitate system (see Table integration and ease of use, as well as to safeguard the device from permanent failure due to a wide Table range of fault conditions such as short circuits, overtemperature, and undervoltage. The TAS5102/3 FAULT OTW a fault by immediately setting the power Overcurrent (OC) or undervoltage stage in a high-impedance (Hi-Z) state and asserting (UVP) warning or overtemperature error (OTE) the FAULT pin low. In situations other than overcurrent (OC) and overtemperature error (OTE), Overtemperature warning (OTW) or overcurrent (OC) or undervoltage the device automatically recovers when the fault (UVP) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

(UVP) and Power-On DEVICE RESET Overcurrent (OC) Protection With Current TAS5102 TAS5103 www.ti.com SLLS801A JUNE 2008 REVISED JUNE 2008 condition has been removed. For highest possible reliability, recovering from an overcurrent fault The TAS5102/3 has a two-level requires external reset of the device (see the Device temperature-protection system that asserts an Reset section of this data sheet) no sooner than 300 active-high warning signal (OTW) when the device ms after the shutdown. junction temperature exceeds 125 C (nominal) and, if the device junction temperature exceeds 150 C (nominal), the device is put into thermal shutdown, Capable Systems resulting in all half-bridge outputs being set in the This device requires at least ns of low time on the high-impedance (Hi-Z) state and FAULT being output per 384-kHz PWM frame rate in order to keep asserted low. OTE is latched in this case. To clear the bootstrap capacitors charged. As an example, if the OTE latch, RESET must be asserted. Thereafter, the modulation index is set to 99.2% in the TAS5086, the device resumes normal operation. this setting allows PWM pulse durations down to ns. This signal, which does not meet the 50-ns Reset (POR) requirement, is sent to the PWM_X pin, and this low-state pulse time does not allow the bootstrap The UVP and POR circuits of the TAS5102/3 fully capacitor to stay charged. In this situation, the low protect the device in any power-up/down and voltage across the bootstrap capacitor can cause the brownout situation. While powering up, the POR bootstrap UVP circuitry to activate and shutdown the circuit resets the overload circuit (OLP) and ensures device. The TAS5102/3 device requires limiting the that all circuits are fully operational when the TAS5086 modulation index to 96.1% to keep the GVDD_XY and VREG supply voltages reach 5.7 V bootstrap capacitor charged under all signals and (typical) and 2.7 respectively. Although GVDD_XY loads. and VREG are independently monitored, a supply voltage drop below the UVP threshold on VREG or Therefore, TI strongly recommends using a TI PWM either GVDD_XY pin results in all half-bridge outputs processor, such as TAS5508 or TAS5086, with the immediately being set in the high-impedance (Hi-Z) modulation index set at 96.1% to interface with state and FAULT being asserted low. The device TAS5102/3. This is done by writing 0x04 to the automatically resumes operation when all supply Modulation Limit Register (0x10) in the TAS5086 or voltages have increased above the UVP threshold. 0x04 to the Modulation Limit Register (0x16) in the TAS5508. One reset pin is provided for control of half-bridges Limiting A/B/C/D. When RESET is asserted low, all four The device has independent, fast-reacting current power-stage FETs in half- bridges and D are detectors on all high-side and low-side power-stage forced into a high-impedance (Hi-Z) state. Thus, the FETs. The detector outputs are closely monitored by reset pin is well suited for hard-muting the power two protection systems. The first protection system stage if needed. controls the power stage in order to prevent the In BTL modes, to accommodate bootstrap charging output current further increasing, i.e., it performs a prior to switching start, asserting the reset input low cycle-by-cycle current-limiting function, rather than enables weak pulldown of the half-bridge outputs. In prematurely shutting down during combinations of the SE mode, the weak pulldowns are not enabled, high-level music transients and extreme speaker load and it is therefore recommended to ensure bootstrap impedance drops. If the high-current condition capacitor charging by providing a low pulse on the situation persists, i.e., the power stage is being PWM inputs when reset is asserted high. overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being Asserting the reset input low removes any fault set in the high-impedance (Hi-Z) state. Current information to be signaled on the FAULT output, i.e., limiting and overcurrent protection are not FAULT is forced high. independent for half-bridges A and B and, A rising-edge transition on the reset input allows the respectively, C and That is, if the bridge-tied load device to resume operation after an overcurrent fault. between half-bridges A and B causes an overcurrent fault, half-bridges and D are shut down. The overcurrent protection threshold is set by a resistor to ground from the OC_ADJ pin. A value of 22k Ω will result in an overcurrent threshold of 4.5 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5102 TAS5103

www.ti.com and heat can be continually removed from the IC. Because of the efficiency of the TAS5102, heatsinks The SSTIMER pin uses a capacitor connected can be used which are much smaller than those between this pin and ground to control the output required for linear amplifiers of equivalent duty cycle when a transition occurs on the RESET performance. pin. The capacitor on the SSTIMER pin is slowly charged through an internal current source, and the R θ JA is a system thermal resistance from junction to charge time determines the rate at which the output ambient air. As such, it is a system parameter with transitions from a near zero duty cycle to the duty roughly the following components: R θ JC (the thermal cycle that is present on the inputs. This allows for a resistance from junction to case, or in this instance smooth transition with no audible pop or click noises the metal pad), thermal grease thermal resistance, when the RESET pin transitions from high-to-low or and heatsink thermal resistance. R θ JC has been low-to-high. provided in the Device Information section. The thermal grease thermal resistance can be calculated For a high-to-low transition of the RESET pin from the exposed pad area and the thermal grease (shutdown case), it is important for the modulator to manufacturer s area thermal resistance (expressed in remain switching for a period of at least ms (if C-in /W). The area thermal resistance of the using a 2.2 nF capacitor). Larger capacitors will example thermal grease with a 0.001-inch thick layer increase the start-up/shutdown time, while capacitors is about 0.054 C-in /W. The approximate exposed smaller than 2.2 nF will decrease the pad area is 0.01164 in Dividing the example thermal start-up/shutdown time. The inputs MUST remain grease area resistance by the area of the pad gives switching on the shutdown transition to allow the the actual resistance through the thermal grease 3.3 outputs to slowly ramp down the duty cycle to near C/W. zero before completely shutting off. The SSTIMER pin should be left floating for BD modulation and also Heatsink thermal resistance is generally predicted by for SE (single-ended) mode. the heatsink vendor, modeled using a continuous flow dynamics (CFD) model, or measured. Thus for a single IC, the system R θ JA R θ JC thermal grease resistance heatsink resistance. The thermally augmented package provided with the TAS5102 is designed to be interfaced directly to a Thermal information for the TAS5103 Pad Down heatsink using a thermal interface compound (for design can be found in TI document SLMA002 example, Wakefield Engineering type 126 thermal PowerPAD Thermally Enhanced Package Application grease.) The heatsink then absorbs heat from the IC Report Additional material regarding thermal metrics and couples it to the local air. If the heatsink is can be found in TI document SPRA953A, IC Package carefully designed, this process can reach equilibrium Thermal Metrics (Rev. A). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5102 TAS5103

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TAS5102DAD ACTIVE HTSSOP DAD 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5102DADG4 ACTIVE HTSSOP DAD 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5102DADR ACTIVE HTSSOP DAD 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5102DADRG4 ACTIVE HTSSOP DAD 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5103DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5103DAPG4 ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5103DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5103DAPRG4 ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Jul-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5102DADR HTSSOP DAD 32 2000 346.0 346.0 41.0 TAS5103DAPR HTSSOP DAP 32 2000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Jul-2008 Pack Materials-Page 2

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Summary

20-W/15-W STEREO DIGITAL AMPLIFIER POWER STAGE

Description

20-W/15-W STEREO DIGITAL AMPLIFIER POWER STAGE

Source title TAS5103DAP Datasheet(PDF) - Texas Instruments

Read TAS5103DAP online.