TAS5100_08 TI1 | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 16

Technical content

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 /C0084/C0082/C0085/C0069 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0065/C0085/C0068/C0073/C0079 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0084/C0065/C0083/C0053/C0049/C0048/C0048 /C0080/C0087/C0077 /C0080/C0079/C0087/C0069/C0082 /C0079/C0085/C0084/C0080/C0085/C0084 /C0083/C0084/C0065/C0071/C0069 1www.ti.com

FEATURES

/C0068TAS5000 + TAS5100 TDAA System-High Quality Digital Audio Amplification /C006893-dB Dynamic Range (TDAA System) /C0068THD+N < 0.08% (1 kHz, 1 W to 30 W RMS Into 6Ω) /C0068Power Efficiency > 90% Into 8-Ω Load /C0068Low Profile, SMD 32-Pin PowerPAD Package Requires No Heat-Sink When Using Recommended Layout /C006830-W RMS Continuous Power Into 4 Ω to 8 Ω /C0068Self-Protecting Design /C00683.3-V Digital Interface /C0068EMI Compliant When Used With Recommended System Design

APPLICATIONS

/C0068DVD Receiver /C0068Home Theater /C0068Car Audio Amplifiers and Head Units /C0068Internet Music Appliance /C0068Mini/Micro Component Systems

DESCRIPTION

True digital audio amplifier (TDAA) is a new paradigm in digital audio. The TDAA system currently consists of the TAS5000 PCM-PWM modulator device + TAS5100 PWM power output device. This system accepts a serial PCM digital audio stream and converts it to a 3.3-V PWM audio stream (TAS5000). The TAS5100 device then provides a large-signal PWM output. This digital PWM signal is then demodulated providing power output for driving loudspeakers. This patented technology provides low-cost, high-quality, high-efficient digital audio applicable to many audio systems developed for the digital age. The TAS5100 is a single-channel PWM power audio device. It contains integrated gate drivers, four matched and electrically isolated enhancement- mode N-channel power DMOS transistors. Also, included are protection and fault-reporting circuitry. This device is optimized for use with the TAS5000 digital modulator. TYPICAL TDAA STEREO AUDIO SYSTEM Digital Audio

  • TAS3001
  • DSP
  • SPDIF
  • 1394 TAS5000 L-C Filter L-C Filter Left Right TAS5100
  • Volume
  • EQ
  • DRC
  • Bass
  • Treble
  • Serial Audio Input Port
  • Internal PLL
  • PCM−PWM Modulator • 2 H-Bridge Power Devices TAS5100 /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 PowerPAD and Equibit are trademarks of Texas Instruments. Copyright  2001, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 2 www.ti.com terminal assignments The TAS5100 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP). PWM_AP PWM_AM ERR1 ERR0 SHUTDOWN DVDD DVSS DVSS DVSS VRFILT BIAS_A BIAS_B PWDN RESET PWM_BM PWM_BP PVDDA2 LDROUTA BOOTSTRAPA PVDDA1 PVDDA1 OUTPUTA OUTPUTA PVSS PVSS OUTPUTB OUTPUTB PVDDB1 PVDDB1 BOOTSTRAPB LDROUTB PVDDB2 DAP PACKAGE (TOP VIEW)

ordering information

0°C to 70°C TAS5100DAP −40°C to 85°C TAS5100IDAP references TAS5000 Digital Audio PWM Process Data Manual − TI Literature Number SLAS270 System Design Considerations for True Digital Audio Power Amplifiers − TI Literature Number SLAA117 Digital Audio Measurements − TI Literature Number SLAA114 PowerPAD Thermally Enhanced Package − TI Literature Number SLMA002

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 3www.ti.com functional block diagram Boot Strap Gate Drive DIFF RCVR LDR Boot Strap Gate Drive DIFF RCVR LDR Control/Sense Circuit Bandgap Reference 1/2 H-Bridge 1/2 H-Bridge OUTPUTA OUTPUTA PVSS BOOTSTRAPB PVDDB1 PVDDB1 OUTPUTB OUTPUTB DVDD DVSS PVSS PWM_AP PWM_AM PWDN RESET SHUTDOWN ERR1 ERR0 LDROUTB VRFILT PVDDB2 PWM_BM PWM_BP PVDDA2 LDROUTA BOOTSTRAP A PVDDA1 PVDDA1 BIAS_A BIAS_B

See application note SLAA117 for more details.

  • USB
  • IEEE 1394
  • SPDIF
  • ADC
  • Automotive MOST Network Digital Audio TAS3001 IIC Audio Control TAS5000 TAS5100Left Right
  • Digital Parametric EQ
  • Volume
  • DRC
  • Bass
  • Treble
  • Serial Audio Input Port
  • Internal PLL
  • 2 H-Bridges TAS5100

Figure 1. System #1: Stereo Configuration With TAS3001 Digital Audio Processor

  • Dolby AC-3
  • DTS
  • Volume
  • EQ
  • DRC
  • Bass
  • Treble Home Theater DVD 6-Channel Encoded Digital Audio Source TAS5000 TAS5100CH1 CH2 TAS5000 CH3 CH4 TAS5000 CH5 CH6 TAS5100 TAS5100 TAS5100 TAS5100 TAS5100 Left Right Surround Left Surround Right Center Subwoofer TAS5100

Figure 2. System #3: 6-Channel Audio Playback

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 6 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION BIAS_A 11 I Connect external resistor to DVSS. See application note SLAA117 BIAS_B 12 I Connect external resistor to DVSS. See application note SLAA117 BOOTSTRAPA 30 O Bootstrap capacitor pin for H-bridge A BOOTSTRAPB 19 O Bootstrap capacitor pin for H-bridge B DVDD 6 I 3.3-V digital voltage supply for logic DVSS 7, 8, 9 I Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not connected externally to PVSS. See Figure 5. ERR1 3 O Error/warning report indicator. This output is open drain with internal pullup resistor. ERR0 4 O Error/warning report indicator. This output is open drain with internal pullup resistor. LDROUTA 31 O Low voltage drop-out regulator output A (not to be used to supply current to external circuitry) LDROUTB 18 O Low voltage drop-out regulator output B (not to be used to supply current to external circuitry) OUTPUTA 26, 27 O H-bridge output A OUTPUTB 22, 23 O H-bridge output B PVDDA1 28, 29 I High voltage power supply, H-bridge A PVDDA2 32 I High voltage power supply for low-dropout voltage regulator A-side PVDDB1 20, 21 I High voltage power supply, H-bridge B PVDDB2 17 I High voltage power supply for low-dropout voltage regulator B-side PVSS 24, 25 I High voltage power supply ground PWDN 13 I Power down = 0, normal mode = 1 PWM_AP 1 I PWM input A(+) PWM_AM 2 I PWM input A(−) PWM_BP 16 I PWM input B(+) PWM_BM 15 I PWM input B(−) RESET 14 I Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are in low-low output state. Asserting the RESET signal low causes all fault conditions to be cleared. SHUTDOWN 5 O Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when device is in shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be cleared by asserting the RESET signal. This output is open drain with internal pullup resistor. VRFILT 10 O A filter capacitor must be added between VRFILT and DVSS pins. NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5000 output pins, and never left floating. Floating PWM input pins will cause an illegal PWM input state signal to be asserted. Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output devices. Failure to connect all the multiple pins to the same respective node will result in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same node, respectively.

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 7www.ti.com functional description PWM H-bridge state control The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals are a complementary differential signal format for the A-side H-bridge and the B-side H-bridge. bootstrapped gate drive The TAS5100 includes 2 dedicated bootstrapped power supplies. A bootstrap capacitor is connected between the individual bootstrap pin and the associated output as described in the application note SLAA117. For example, a capacitor will be connected between the BOOTSTRAPA pin and OUTPUTA pin, and another capacitor will be connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply levels externally supplied to the system while providing a low noise supply level for driving the high-side N-channel DMOS transistors. See application note SLAA117 for details. low-dropout voltage regulator Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for external circuitry. Each LDO is dedicated to an H-bridge and its gate driver. An LDO output capacitor is connected between the individual LDO output pin and the associated output return as described in the application note SLAA117. For example, a capacitor will be connected between the LDROUTA pin and PVSS pin, and another capacitor will be connected between the LDROUTB pin and PVSS pin. high-current H-bridge output stage The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output mapping section below. When the TAS5100 is in the normal mode, as seen in the H-bridge output mapping tables, the outputs are decoded from the inputs. However, the TAS5100 is immediately shut down if any of the following error conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal PWM input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified in the H-bridge output mapping section, and the SHUTDOWN pin is set low. H-bridge output mapping The A-side H-bridge output is designed to the following truth table: INPUTS OUTPUTS DESCRIPTIONRESET PWDN PWM_AP PWM_AM SHUTDOWN OUTPUTA DESCRIPTION X X X X 0 0 or Hi-Z† Shutdown X 0 X X 1 Hi-Z Powerdown 0 1 X X 1 0 Reset 1 1 0 0 0 0 Shutdown 1 1 0 1 1 0 Normal 1 1 1 0 1 1 Normal 1 1 1 1 0 0 Shutdown † Output is 0 for low voltage, over temperature, and illegal input. Hi-Z is for over current.

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 8 www.ti.com H-bridge output mapping (continued) The B-side H-bridge output is designed to the following truth table: INPUTS OUTPUTS DESCRIPTIONRESET PWDN PWM_BP PWM_BM SHUTDOWN OUTPUTB DESCRIPTION X X X X 0 0 or Hi-Z† Shutdown X 0 X X 1 Hi-Z Powerdown 0 1 X X 1 0 Reset 1 1 0 0 0 0 Shutdown 1 1 0 1 1 0 Normal 1 1 1 0 1 1 Normal 1 1 1 1 0 0 Shutdown † Output is 0 for low voltage, over temperature, or illegal input. Hi-Z is for over current. control/sense circuitry The control/sense circuitry consists of the following 3.3-V logic level pins: PWDN, RESET, ERR0, ERR1, and SHUTDOWN . The active-low PWDN input pin powers down all internal circuitry and forces the H-bridge outputs to the Hi-Z state. When the PWDN pin is low, the open drain ERR0, ERR1, and SHUTDOWN pins are also disabled so that their outputs can be pulled high. The active-low RESET input pin forces the H-bridge outputs to the low-low state and resets the over-current shutdown latch. The PWDN pin overrides the RESET pin. The ERR0 , ERR1, and SHUTDOWN outputs indicate the following conditions in the TAS5100 as shown in the table below. These three outputs are open-drain connections with internal pullup resistors so that wire-ORed connections can be made by the user with other external control devices. The short circuit protect error condition will latch the TAS5100 in this shutdown state and force the H-bridge outputs to the Hi-Z state until the device is reset by means of the RESET pin. The illegal PWM input state, over-temperature, and low regulator voltage error conditions will not latch the device in the shutdown condition. Instead the H-bridge outputs are forced to the low-low state and the TAS5100 will return to normal operation as soon as the error condition ends. Loss of clocking PWM signal is also considered an illegal PWM input state. SHUTDOWN ERR1 ERR0 FUNCTION OUTPUTA OUTPUTB 0 0 0 Illegal PWM input state Low Low 0 0 1 Short circuit protect (latch) Hi-Z Hi-Z 0 1 0 Over temperature protect Low Low 0 1 1 Low regulator voltage protect Low Low 1 0 0 Reserved — — 1 0 1 Reserved — — 1 1 0 High temperature − warning Normal Normal 1 1 1 Normal operation Normal Normal

are being applied. The RESET signal should remain LOW for at least 1 ms after output power is applied. † For most applications, it is recommended that pin 13 (PWDN) be connected directly to pin 6 (DVDD). Figure 3. Power-Up/Power-Down Sequence connected to the VALID signal from the TAS5000. accomplished by asserting the reset pin on the TAS5000 during the reset sequence (see Figure 3). information in the application note SLAA117. level for a given load resistance. See recommended operating conditions.

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 10 www.ti.com audio application considerations (continued) reconstruction output filter An output reconstruction filter is required between the H-bridge outputs and the loudspeaker load. This second order low-pass filter passes the audio information to the loudspeaker, while filtering out the high frequency out-of-band information contained in the H-bridge output PWM pulses. The values of the L and C components selected are dependent on the loudspeaker load impedance. See application note SLAA117. fault indicator usage The TAS5100 is a self-protecting device that provides device fault reporting, including over-temperature protect, under-voltage lockout (low-regulator voltage), and short circuit protection. The short circuit protection protects against short circuits that may occur at the loudspeaker load when configured according to the application note SLAA117. The TAS5100 is not recommended for driving loads less than 4 Ω, since the internal current limit protection might be activated. An under-voltage lockout signal occurs when an insufficient voltage level is present on the LDROUTA or LDROUTB pins. During this condition gate drive levels are not sufficient for driving the power MOSFETs. Normal operation is resumed when the minimum proper LDROUTA or LDROUTB level is obtained, and the low regulator voltage protect signal is de-asserted. See the control/sense circuitry section for error and warning conditions. A high temperature warning signal is asserted on pin ERR0 when the device temperature exceeds 110°C typical. If the internal device temperature exceeds 130°C typical, the over temperature protect signal is asserted and the TAS5100 is shut down. The device will re-enable once the temperature drops to 110°C typical. See the control/sense circuitry section for error and warning conditions. Detection of an illegal PWM input state or the loss of a clocking PWM input signal will cause an illegal PWM input state signal to be asserted on the ERR1and ERR0 pins and will set the SHUTDOWN pin to the low state. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 11www.ti.com recommended operating conditions (nominal output power = 30 W (RMS), TA = 25°C) thermal data† PARAMETER MIN NOM MAX UNIT Shutdown junction temperature, TJ(SD) 130 °C Warning junction temperature, TJ(W) 110 °C Operating ambient temperature, TA 0 25 70 °C Thermal resistance junction-to-case, θjc 2 oz. trace and copper pad with solder 0.32 °C/W Thermal resistance junction-to-ambient, θja 2 oz. trace and copper pad with solder 23.5 °C/W Thermal resistance junction-to-case, θjc 2 oz. trace and copper pad without solder 0.32 °C/W Thermal resistance junction-to-ambient, θja 2 oz. trace and copper pad without solder 44.3 °C/W † One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat dissipating abilities of the PowerPAD packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and solderable), deep downset pad. See Appendix A of the PowerPAD Thermally Enhanced Package application note, TI literature number SLMA002 and the Thermal Design of the PowerPad PCB Layout section of the System Design Considerations for True Digital Audio Power Amplifiers application note, TI literature number SLAA117. R L = 4 Ω to 8 Ω PARAMETER MIN NOM MAX UNIT Digital DVDD to DVSS 3 3.3 3.6 V PVDDA2 to PVSS 16.5 22 24 Supply voltage Regulator PVDDB2 to PVSS 16.5 22 24 V Supply voltage Regulator PVDDA2 to PVSS /C0125 10.5 16.5 V PVDDB2 to PVSS /C0125 10.5 16.5 ‡ Connect LDROUTA to PVDDA2 and connect LDROUTB to PVDDB2. Under this condition H-Bridge forward on-state resistance is increased. This will increase internal power dissipation. Maximum output power may need to be reduced to meet thermal conditions. R L = 8 Ω PARAMETER MIN NOM MAX UNIT Supply voltage Power PVDDA1 to DVSS 0 26 27 VSupply voltage Power PVDDB1 to PVSS 0 26 27 V R L = 6 Ω PARAMETER MIN NOM MAX UNIT Supply voltage Power PVDDA1 to DVSS 0 23 24 VSupply voltage Power PVDDB1 to PVSS 0 23 24 V R L = 4 Ω PARAMETER MIN NOM MAX UNIT Supply voltage Power PVDDA1 to DVSS 0 20 21 VSupply voltage Power PVDDB1 to PVSS 0 20 21 V

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 12 www.ti.com static digital specifications RESET , PWDN , PWM_AP, PWM_AM, PWM_BP, PWM_BM, T A = 25°C, DVDD = 3.3 V PARAMETERS MIN MAX UNIT High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V Input leakage current −10 10 µA ERR0 , ERR1, SHUTDOWN , (open drain with internal pullup resistor) TA = 25°C, DVDD = 3.3 V) PARAMETERS MIN MAX UNIT Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD 15 kΩ Low-level output voltage (IO = 4 mA), VOL 0.4 V TAS5000/TAS5100 system performance measured at the speaker terminals See the TI Literature Number SLAA117 for TAS5000/TAS5100 system performance.

electrical characteristics

supply, TA = 25°C (Fswitching = 384 kHz, OUTPUTA and OUTPUTB not connected, DVDD = 3.3 V, PVDDA1 = 25 V, PVDDB1 = 25 V, PVDDA2 = 22 V, PVDDB2 = 22 V, 50% input duty cycle) PARAMETER TYP MAX UNIT DVDD Operating 2 mA DVDD PWDN = 0 500 µA Supply current PVDDA1 Operating† 6.3 mA Supply current PVDDA1 PVDDB1 PWDN = 0 25 µA PVDDA2 Operating 6.5 mAPVDDA2 PVDDB2 PWDN = 0 250 µA † 13-kΩ resistor from BIAS_A (pin 11) to DVSS and 13-kΩ resistor from BIAS_B (pin 12) to DVSS. H-Bridge transistors, PVDDA2 = PVDDB2 = 22 V, DVDD = 3.3 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Drain-to-source breakdown voltage ID = 1 mA, PWDN = 0, Hi-Z state 28 V Forward on-state resistance, low side drivers OUTPUTA and OUTPUTB to PVSS ISINK = 2.5 A, See Notes 2, 3, and 4, PWM_AP = PWM_BP = 0, PWM_AM = PWM_BM = 1 0.2 Ω Forward on-state resistance, high side drivers PVDDA1 to OUTPUTA, PVDDB1 to OUTPUTB ISOURCE = 2.5 A, See Notes 2, 3, and 5, PWM_AP = PWM_BP = 1, PWM_AM = PWM_BM = 0 0.2 Ω On-state resistance matching low-side drivers 98% On-state resistance matching high-side drivers 98% NOTES: 1. Test time should be < 1 ms to avoid temperature change. 2. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 3. Connect PVDDA2 and PVDDB2 to 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA, and BOOTSTRAPB pins open. 4. Connect PVDDA2 to 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA and BOOTSTRAPB capacitors are connected respectively. Clock PWM inputs to allow bootstrap capacitors to charge. 93−99% modulation must be used on PWM_AP, PWM_AM, PWM_BP, and PWM_BM inputs to prevent the activity detector from shutting down the device during this measurement. Note that Fswitching = 384 kHz.

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 14 www.ti.com DISSIPATION DERATING TABLE PACKAGE TA ≤ 25°C † POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING DAP 5.3 W 42.5 mW/°C 3.4 W † See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report (literature number SLMA002), for more information on the PowerPAD package. The thermal data was measured on a PCB layout based on the information in the section entitled Texas Instruments Recommended Board for PowerPAD of the before mentioned document. Data in table is for specified layout. Under other conditions the thermal performance may vary. See Texas Instruments document SLAA117 for more detailed application information.

APPLICATION INFORMATION

_+dc PWM_AP PWM_AM ERR1 ERR0 SHUTDOWN DVDD DVSS DVSS DVSS VRFILT BIAS_A BIAS_B PWDN RESET PWM_BM PWM_BP PVDDA2 LDROUTA BOOTSTRAPA PVDDA1 PVDDA1 OUTPUTA OUTPUTA PVSS PVSS OUTPUTB OUTPUTB PVDDB1 PVDDB1 BOOTSTRAPB LDROUTB PVDDB2 C3 C4 C5 C6 3.3 V RESET PWM_M_L PWM_P_L VALID TAS5000 22 V 22 V Figure 5. Typical TAS5100 Application (One Channel Shown) See the application note, TI literature number SLAA117 for detailed application information.

/C0084/C0065/C0083/C0053/C0049/C0048/C0048 SLLS419B − MARCH 2001 − REVISED NOVEMBER 2001 15www.ti.com MECHANICAL DATA DAP (R-PDSO-G) PowerPAD  PLASTIC SMALL-OUTLINE PACKAGE 0,25 0,75 0,50 0,15 NOM Gage Plane NOM 6,20 8,40 7,80 Thermal Pad (see Note D) 12,6011,10 Seating Plane 12,4010,90 4073257/A 07/97 0,19 A 0,30 9,80 A MAX PINS 9,60A MIN DIM 1,20 MAX 10,90 11,10

38 PINS SHOWN

0,10 0,65 M0,13 0°−/C0257 8° 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. Thermal pad size is 3,86 mm X 3,91 mm for the 32-pin TAS5100 device. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments.

(TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for design. Customers are responsible for their products and components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Clocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrol Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony RF/IF and ZigBee Solutions www.ti.com/lprf Video Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2008, Texas Instruments Incorporated