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SLAS328 – SEPTEMBER 2001 TRUE DIGITAL AUDIO AMPLIFIER TAS5010 DIGITAL AUDIO PWM PROCESSOR 1www.ti.com

FEATURES

/C0068TAS5010 + TAS5100 TDAA System – High Quality Digital Audio Amplification /C006896-dB Dynamic Range (TAS5010 Device) /C006893-dB Dynamic Range (TAS5010 & TAS5100 System Measured at Speaker Terminals) /C0068THD+N < 0.08% (1 kHz, 1 to 30W RMS into 6 Ω ) /C0068Power Efficiency Is 90% Into 8-Ω Load /C006816-, 20-, or 24-Bit Input Data /C006844.1-kHz, 48-kHz, 88.2-kHz, 96-kHz, 176.4-kHz, 192-kHz Sampling Rates /C0068Economical 48-Pin TQFP Package /C0068Lower-Jitter Internal PLL /C00683.3-V Power Supply /C0068Mute /C0068Clicks and Pops Reduction (Patent Pending)

APPLICATIONS

/C0068DVD-Audio /C0068Home Theater /C0068Car Audio Amplifiers and Head Units /C0068Internet Music Appliance /C0068Mini/Micro Component Systems

DESCRIPTION

The true digital audio amplifier (TDAA) is a new paradigm in digital audio. One TDAA system consists of the TAS5010 PCM-PWM modulator device + a TAS5100 PWM power output device. This system accepts a serial PCM digital audio stream and converts it to a 3.3-V PWM audio stream (TAS5010). The TAS5100 device then provides a large-signal PWM output. This digital PWM signal is then demodulated providing power output for driving loudspeakers. This patented technology provides low-cost, high-quality, high- efficiency digital audio applicable to many audio systems developed for the digital age. The TAS5010 is an innovative, cost-effective, high-performance 24-bit stereo PCM-PWM modulator based on Equibit  technology. It has a wide variety of serial input options including right-justified (16, 20, or 24 bits), IIS (16, 20, or 24 bits), left-justified (16 bits), or DSP (16 bits) data formats. It is fully compatible with AES standard sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. The TAS5010 also provides a de-emphasis function for 44.1-kHz and 48-kHz sampling rates. TAS5010 TAS5100 Left

  • Volume
  • EQ
  • DRC
  • Bass
  • Treble
  • Serial Audio Input Port
  • Internal PLL
  • Equibit Modulator
  • Up to 192-kHz Sampling
  • TAS3001
  • DSP
  • S/PDIF
  • 1394 Digital Audio
  • H-Bridges Power Devices TAS5100 Right L-C Filter L-C Filter PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2001, Texas Instruments Incorporated Equibit is a trademark of Toccata Technology ApS, Denmark. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SLAS328 – SEPTEMBER 2001 2 www.ti.com terminal assignments 14 15 DVDD3_L PWM_AP_L PWM_AM_L NC NC DVDD2 DVSS2 PWM_AP_R PWM_AM_R NC NC DVDD3_R MCLK_IN AVDD2 PLL_FLT_OUT PLL_FLT_RET AVSS2 NC RESET PDN VALID_R M_S NC DVDD1 17 18 19 20 47 46 45 44 4348 42 40 39 3841 21 22 23 24 48-Pin TQFP PACKAGE (TOP VIEW) NC – No internal connection AVDD1 XTL_IN XTL_OUT OSC_CAP AVSS1 DEM_EN DEM_SEL FTEST STEST DBSPD MUTE DVSS3_L DVSS1 DVDD1 DVSS1 MCLK_OUT SCLK LRCLK SDIN MOD2 MOD1 MOD0 VALID_L DVSS3_R references /C0068True Digital Audio Amplifier TAS5100 Power Output Stage – Texas Instruments publication SLLS419A /C0068Design Considerations for TAS5000/TAS5100 True Digital Audio Power Amplifiers – Texas Instruments publication SLAA117 /C0068Digital Audio Measurements – Texas Instruments publication SLAA114 /C0068PowerPAD  Thermally Enhanced Package – Texas Instruments publication SLMA002 PowerPAD is a trademark of Texas Instruments.

SLAS328 – SEPTEMBER 2001 3www.ti.com functional block diagram PLL/Clock Generator OSC Serial Audio Port Digital Interpolation Filter Equibit Modulator Buffer Audio Port Configuration Control Section LRCLK SCLK SDIN PWM_AP_L PWM_AM_L PLL_FLT_RET PLL_FLT_OUT MCLK_IN MCLK_OUT XTL_IN XTL_OUT OSC_CAP MOD0 MOD1 MOD2 DEM_SEL DEM_EN MUTE RESET PDN FTEST STEST DBSPD M_S DVDD1 DVSS1 DVDD2 DVSS2 DVDD3_L DVSS3_L DVDD3_R DVSS3_R AVDD1 AVSS1 AVDD2 AVSS2 PWM_AP_R PWM_AM_R VALID_R VALID_L AVAILABLE OPTIONS TA PACKAGE † 0°C to 70°C TAS5010PFB –40°C to 85°C TAS5010IPFB † These packages are available taped and reeled. Add an R suffix to device type (e.g., TAS5010PFBR).

SLAS328 – SEPTEMBER 2001 4 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AVDD1 48 I Analog supply for oscillator AVDD2 2 I Analog supply for PLL AVSS1 44 I Analog ground for oscillator AVSS2 5 I Analog ground for PLL DBSPD 39 I Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high DEM_EN 43 I De-emphasis enable, active high DEM_SEL 42 I De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz) DVDD1 12, 14 I Digital voltage supply for logic DVDD2 31 I Digital voltage supply for PWM reclocking DVDD3_L 36 I Digital voltage supply for PWM output (left) DVDD3_R 25 I Digital voltage supply for PWM output (right) DVSS1 13, 15 I Digital ground for logic DVSS2 30 I Digital ground for PWM reclocking DVSS3_L 37 I Digital ground for PWM output (left) DVSS3_R 24 I Digital ground for PWM output (right) FTEST 41 I Tied to DVSS1 for normal operation LRCLK 18 I/O Left/right clock (input when M_S = 0; output when M_S = 1) MCLK_IN 1 I MCLK input MCLK_OUT 16 O Buffered system clock output if M_S = 1; otherwise set to 0 MOD0 22 I Serial interface selection pin, bit 0 MOD1 21 I Serial interface selection pin, bit 1 MOD2 20 I Serial interface selection pin, bit 2 (MSB) M_S 10 I Master/slave, master=1, slave=0 MUTE 38 I Muted signal = 0, normal mode = 1 NC 6, 11, 26, 27, 32, 33 No connection OSC_CAP 45 I Oscillator cap return PDN 8 I Power down, active low PLL_FLT_OUT 3 O Output terminal for external PLL filter PLL_FLT_RET 4 I Return for external PLL filter PWM_AM_L 34 O PWM left output (differential –) PWM_AM_R 28 O PWM right output (differential –) PWM_AP_L 35 O PWM left output (differential +) PWM_AP_R 29 O PWM right output (differential +) RESET 7 I Reset (active low) SCLK 17 I/O Shift clock (input when M_S = 0, output when M_S = 1) SDIN 19 I Stereo serial audio data input STEST 40 I Tied to DVSS1 for normal operation VALID_L 23 O PWM left outputs valid (active high) VALID_R 9 O PWM right outputs valid (active high) XTL_IN 47 I Crystal or clock input (MCLK input) XTL_OUT 46 O Crystal output (not for external usage).NC when XTL_IN is MCLK input

88.2 kHz, 96 kHz, 176.4kHz, or 192kHz) stereo. See serial interface formats section. MCLK_IN) to the TAS5010 (M_S = 0). The TAS5010 operates with LRCLK and SCLK synchronized to MCLK. or 24.576 MHz (Fs = 96 kHz). Table 1 explains the proper clock selection. Table 1. Oscillator, External Clock, and PLL Functions † Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN. ‡ MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided. ¶ SCLK and LRCLK are outputs when M_S=1, inputs when M_S=0. # MCLK_OUT is driven low when M_S=0. ||Quad speed mode is detected automatically.

time, the TAS5010 begins normal operation. Figure 3. Reset Timing the PDN pin goes low. Otherwise, the device may drain additional supply current. Figure 4. Power-Down Timing in which both sides of the differential PWM outputs have a 50% duty cycle (see Figure 5 for mute timing. Table 2. Mute Description

1 DATA DATA Normal operation

de-emphasis selection description. Table 3. De-Emphasis Selection 1 0 Forbidden modey. Do not use. Table 4. Hardware Selection of Serial Audio Modes

SLAS328 – SEPTEMBER 2001 12 www.ti.com absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: DVDD1, DVDD2, DVDD3_L, DVDD3_R. recommended operating conditions, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ± 10%, AVDD1 = AVDD2 = 3.3 V ± 10%, Fs = 44.1 kHz MIN TYP MAX UNIT Supply voltage Digital DVDDX ‡ 3 3.3 3.6 V Supply current Digital Operating 22 mA Supply current Digital Power down§ 10 20 µA Power dissipation Digital Operating 59.4 mW Power dissipation Digital Power down§ 6.6 72 µW Supply voltage Analog AVDDX ¶ 3 3.3 3.6 V Supply current Analog Operating 8 mA Supply current Analog Power down§ 10 100 µA Power dissipation Analog Operating 26.4 mW Power dissipation Analog Power down§ 33 360 µW ‡ DVDD1, DVDD2, DVDD3_L, DVDD3_R § If the clocks are turned off ¶ AVDD1, AVDD2 electrical characteristics, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ± 10%, AV DD1 = AVDD2 = 3.3 V ± 10% static digital specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage 2 DVDD1 V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage IO = –1 mA 2.4 V VOL Low-level output voltage IO = 4 mA 0.4 V Input leakage current –10 10 µA digital interpolation filter and PWM modulator, Fs = 44.1 kHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Pass band 0 20 kHz Pass band ripple ±0.012 dB Stop band 24.1 kHz Stop band attenuation 24.1 kHz to 152.3 kHz 50 dB Group delay 700 µS PWM modulation index (gain) 0.93

SLAS328 – SEPTEMBER 2001 13www.ti.com TAS5010/TAS5100 system performance measured at the speaker terminals See application note, literature number SLAA117. switching characteristics, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = AVDD1 = AVDD2 = 10% 3.3 V ± 10% serial audio ports slave mode PARAMETER MIN TYP MAX UNIT f(SCLK) SCLK frequency 12.288 MHz tsu(SDIN) SDIN setup time before SCLK rising edge 20 ns th(SDIN) SDIN hold time from SCLK rising edge 10 ns F(LRCLK) LRCLK frequency 44.1 48 192 kHz MCLK duty cycle 50% SCLK duty cycle 50% LRCLK duty cycle 50% tsu(LRCLK) LRCLK edge setup before SCLK rising edge 20 ns serial audio ports master mode, load conditions: 50 pF PARAMETER MIN TYP MAX UNIT t(MSD) MCLK to SCLK 0 5 ns t(MLRD) MLCK to LRCLK 0 5 ns DSP serial interface mode PARAMETER MIN TYP MAX UNIT f(SCLK) SCLK frequency 12.288 MHz tW(FSHIGH) Pulse duration, sync 1/(64×fs) ns tsu(SDIN), tsu(LRCLK) SDIN and LRCLK setup time before SCLK falling edge 20 ns th(SDIN), th(LRCLK) SDIN and LRCLK hold time from SCLK falling edge 10 ns SCLK duty cycle 50%

64 SCLKs

Figure 15. DSP Serial Port Expanded Timing Figure 16. DSP Absolute Timing Requirement

SLAS328 – SEPTEMBER 2001 16 www.ti.com

APPLICATION INFORMATION

PLL_FLT_RET PLL_FLT_OUT DEM_SEL DEM_EN DBSPD SDIN LRCLK SCLK MCLK_IN MOD0 MOD1 MOD2 M_S TAS5100 H-BridgePWM_AP_L PWM_AM_L RESET System Controller MUTE PDN

3.3 V DIG

XTL_IN C 2† R 1† C 1† RESET FTEST TAS5010 VALID_L TAS5100 H-Bridge PWM_AP_R PWM_AM_R RESETVALID_R STEST † See application note, literature number SLAA117 for values

SLAS328 – SEPTEMBER 2001 17www.ti.com MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–/C02577° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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