TAS3218PZP

TAS3218_1 TI | Alldatasheet

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(Typical Output Easy-to-Use Control Interface Level: Vrms) I C Serial Control Master and Slave Stereo Audio DACs Interface High-Quality DNR: dB (Typical) DAC Control Interface Operational Without Channel Performance Channels) External MCLK Input Stereo Headphone Amplifier mW Power Single 3.3-V Power Supply Output into 100 pF Integrated Regulators 100-Pin TQFP (PZP) Package Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

VREG_EN STEST TEST TEST GPIO4 GPIO3 MCLKOUT LRCLKOUT SCLKOUT SDOUT1 SDOUT2/SPDIFOUT DVDD2 VR_DIG1 DVSS2 SPDIF_IN TEST TEST TEST TEST SDIN3 SDIN2 SDIN1 LRCLKIN SCLKIN 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MCLKINDVSS3DVDD3 I2C_SDA2I2C_SCL2I2C_SDA1I2C_SCL1 CS GPIO1GPIO2MUTERESETDVSS4DVDD4DVSS5 VR_DIG2 A VSS_ESD LINEIN1LLINEIN1RA VDD_LILINEIN2LLINEIN2RA VSS_LILINEIN3LLINEIN3R V1P5_REF BG_REF BIAS_REF A VSS_ADC/REF A VDD_ADC LINEIN10R LINEIN10L A VSS_LI LINEIN9R LINEIN9L A VDD_LI LINEIN8R LINEIN8L A VSS_LI LINEIN7R LINEIN7L A VDD_LI LINEIN6R LINEIN6L A VSS_LI LINEIN5R LINEIN5L A VDD_LI LINEIN4R LINEIN4L 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DVDD1 A VDD_OSC VR_ANA XT AL_OUT XT AL_IN A VSS_ESD A VDD_HP HPOUTR AVSS_HPHPOUTL A VDD_HP A VDD_DAC AVSS_DACDACOUT2R DACOUT2L DACOUT1R DACOUT1L LINEIN1R LINEIN1L A VSS_LO LINEOUT2R LINEOUT2L LINEOUT3R LINEOUT3L A VDD_REF TAS3218 SLES235 JULY 2008 www.ti.com The TAS3218 is available in a 100-pin TQFP (PZP) package. PZP PACKAGE (TOP VIEW) ORDERING INFORMATION T A PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TAS3218IPZP C to C TAS3218IPZP TAS3218IPZPR TQFP PZP Tape and reel TAS3218PZP C to C TAS3218PZP TAS3218PZPR (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 TERMINAL FUNCTIONS TERMINAL I/O TERMINATION (1)

DESCRIPTION

NO. NAME DVSS1 P Digital ground VREG _EN DI Voltage regulator enable STEST DI Pulldown Test pin to reconfigure pins 17, 18, TEST Pulldown 19, GPIO4 DIO Pulldown General purpose input/output GPIO3 DIO Pulldown General purpose input/output MCLKOUT DO Master clock output LRCLKOUT DO Left/right (frame) clock output SCLKOUT DO Serial audio data clock output SDOUT1 DO Serial digital audio data output SDOUT2/ DO Serial digital audio data out or S/PDIF out SPDIF_OUT DVDD2 P 3.3-V digital power Pin out of internal regulator. A 4.7-F low ESR capacitor should be VR_DIG1 P connected between this pin and digital ground. This terminal must not be used to power external devices. DVSS2 P Digital ground SPDIF_IN DI S/PDIF input SDIN3 DI Serial digital audio data input SDIN2 DI Serial digital audio data input SDIN1 DI Serial digital audio data input LRCLKIN DI Left/right (frame) clock input SCLKIN DI Serial audio data clock input MCLKIN DI Master clock input DVSS3 P Digital ground DVDD3 P 3.3-V digital power master I2C_SDA2 DIO I C serial data master I2C_SCL2 DIO I C serial clock slave I2C_SDA1 DIO I C serial data slave I2C_SCL1 DIO I C serial clock CS DI Chip select GPIO1 DIO General purpose input/output GPIO2 DIO General purpose input/output MUTE DI Pullup Mute device RESET DI Pullup Reset DVSS4 P Digital ground DVDD4 P 3.3-V digital power DVSS5 P 3.3-V digital power Pin out of internal regulator. A 4.7-F low ESR capacitor should be VR_DIG2 P connected between this pin and digital ground. This terminal must not be used to power external devices. AVSS_ESD P Analog ESD ground LINEIN1L AI Left-channel analog input (1) All pullups are 20-A weak pullups, and all pulldowns are 20-A weak pulldowns (166 The pullups and pulldowns are included to ensure proper input logic levels if the terminals are left unconnected (pullups at logic input; pull-downs at logic input). Devices that drive inputs with pullups must be able to sink A while maintaining a logic drive level. Devices that drive inputs with pull-downs must be able to source A while maintaining a logic drive level. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL I/O TERMINATION (1) NO. NAME LINEIN1R AI Right-channel analog input 45, 53, AVDD_LI P 3.3-V analog power 59, LINEIN2L AI Left-channel analog input LINEIN2R AI Right-channel analog input 48, 56, AVSS_LI P Analog ground 62, LINEIN3L AI Left-channel analog input LINEIN3R AI Right-channel analog input LINEIN4L AI Left-channel analog input LINEIN4R AI Right-channel analog input LINEIN5L AI Left-channel analog input LINEIN5R AI Right-channel analog input LINEIN6L AI Left-channel analog input LINEIN6R AI Right-channel analog input LINEIN7L AI Left-channel analog input LINEIN7R AI Right-channel analog input LINEIN8L AI Left-channel analog input LINEIN8R AI Right-channel analog input LINEIN9L AI Left-channel analog input LINEIN9R AI Right-channel analog input LINEIN10L AI Left-channel analog input LINEIN10R AI Right-channel analog input AVDD_ADC P 3.3-V analog power AVSS_ADC/REF P Analog ground BIAS_REF AO Pin should be tied to analog ground with 22-k BG_REF AO Band gap output. Must be tied to ground with 1-F low ESR capacitor. V1P5_REF AO Common mode output. Must be tied to ground with 1-F low ESR capacitor. AVDD_REF P 3.3-V analog power LINEOUT3L AO Analog line output left channel LINEOUT3R AO Analog line output right channel LINEOUT2L AO Analog line output left channel LINEOUT2R AO Analog line output right channel AVSS_LO P Analog ground LINEOUT1L AO Left-channel analog output LINEOUT1R AO Right-channel analog output DACOUT1L AO Left-channel digital-to-analog converter output DACOUT1R AO Right-channel digital-to-analog converter output DACOUT2L AO Left-channel digital-to-analog converter output DACOUT2R AO Right-channel digital-to-analog converter output AVSS_DAC P Analog ground AVDD_DAC P 3.3-V analog power AVDD_HP P 3.3-V analog power HPOUTL AO Left-channel headphone output AVSS_HP P Analog ground HPOUTR AO Right-channel headphone output AVDD_HP P 3.3-V analog power Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 TERMINAL FUNCTIONS (continued) TERMINAL I/O TERMINATION (1) NO. NAME AVSS_ESD P Analog ground XTAL_IN DI External crystal input XTAL_OUT DO External crystal output Pin out of internal regulator. A 4.7-F low ESR capacitor should be VR_ANA P connected between this pin and digital ground. This terminal must not be used to power external devices. AVDD_OSC P 3.3-V analog power 100 DVDD1 P 3.3-V digital power TAS3218 is an audio system-on-a-chip (SOC) designed for digital television audio systems and mini/micro component applications. TAS3218 has a programmable audio DSP that preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single cycle x 48-bit multiplier. The programmability feature allows users to customize RAM. The TAS3218 is composed of seven functional blocks. Clock and serial data interface Analog input and output M8051 WARP controller, serial control interface, and device control Audio DSP digital audio processing Power supply Internal references Figure shows the functional structure of the TAS3218. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

10 :1 2CH ADC 10 ch□stereo Analog Inputs DAC Mod 6CH DAC SPDIF HP□AMP SDIN 1 SDIN 2 SDIN 3 HP□OUT□L / R SAP OUT SDOUT 1 SCL 1 SDA 1 SCL 2 SDA 2 GPIO 1- 4 CS SPDIF□OUT / SDOUT 2 3:1 MUX SPDIF□IN MUTEZ MCLKIN SCLKIN LRCLKIN MCLKOUT SCLKOUT LRCLKOUT SCLKI LRCLKI 0.8 uF

2.8 VRMS

10 K ohm

10 ch□stereo 10 ch□stereo Analog□line□Input 1VRMS

16 Ohm

2 LINEOUT 1L/R

10:1 LINEOUT 3L/R

2 LINEOUT 2L/R

Apply□to□all□Line□and DAC□outputs 2.2 uF 10K ohm

0.9 V RMS( MAX )

1V RMS ( MAX )Line□outputs DAC□outputs A-MUX 10:1 A-MUX 1 1:1 TAS3218 SLES235 JULY 2008 www.ti.com Figure Block Diagram Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

I C 8051 A - MUX 10 :1 2CH ADC 10 ch□stereo Analog Inputs DAC Mod 6CH DAC SPDIF HP□AMP SDIN 1 SDIN 2 SDIN 3 HP□OUT□L / R SAP OUT SDOUT 1 SCL 1 SDA1 SCL 2 SDA 2 GPIO 1-4 CS SPDIF□OUT / SDOUT 2 3 :1 MUX SPDIF□IN MUTEZ DACOUT 1L / R DACOUT 2 L/ R MCLKIN SCLKIN LRCLKIN MCLKOUT SCLKOUT LRCLKOUT A - MUX 1 1:1 SCLKI LRCLKI LINEOUT 1 L/R 10 ch□stereo Clock Control OSC512Fs A VSS TBD TBD Rbias 512 Fs 10 pf 10 pfA VSS R b i as External ASRC MCLKO SCLKO LRCLKO SDO 1 SDO 2 SDO 3 SDIN 1A SDIN 2B SDIN 3B SDIN 4B SCLKA LRCLKA MCLKA SCLKB LRCLKB MCLKB MUX MCLKI SCLKI LRCLKI MUX SDI1 SDI2 SDI3 MC LK OUT SC LK OUT LRC LK OUT Clocks TAS3218 www.ti.com SLES235 JULY 2008 Figure Interface to External ASRC The TAS3218 can be configured as either the clock master or clock slave depending on the settings in the clock configuration register. By default, the TAS3218 is configured as the clock master. Figure shows the block diagram of the TAS3218 clocks Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

(Transmitter ) LRCLKOUT (Recreation / Normalization ) DPLL (11x) DSP_CLK (135MHz)DIV□BY

4 MICRO_CLK

(33MHz) MCLKOUT 256Fs 2816Fs 64Fs Fs SCLKOUT 64Fs SCLKIN LRCLKOUT Fs LRCLKIN MCLKIN 128Fs MCLKIN DIV□BY 256Fs CMS (Clock□Master /Slave□Selection ) DIV□BY DIV□BY DIV□BY DIV□BY 512 CMS CMS SAP IN (Receiver ) SDIN 1 Data□to□DSP Ch 1[23:0] ON (Output□Normalization Enable) SDOUT 1 Data□from□DSP Ch 1[23:0] SDIN 2 SDIN 3 Data□to□DSP Ch 2[23:0] Data□to□DSP Ch 3[23:0] Data□to□DSP Ch 4[23:0] Data□to□DSP Ch 5[23:0] Data□to□DSP Ch 6[23:0] Data□from□DSP Ch 2[23:0] Data□from□DSP Ch 3[23:0] Data□from□DSP Ch 4[23:0] sdout2 SPDIF_CLK IM[1:0] (SAP Input□Mode ) OM[1:0]□(SAP Output□Mode ) SPDIF Transmitter Parallel□Data□from□DSP SPDIF _L[23:0] Parallel□Data□from□DSP SPDIF _R[23:0] SPDIF _CONTROL_REG_IN[□] spdif_tx_out SPDIF _IN I2C□Module DIV□by 10DIV□by (M+1) DIV□by 2^N I2C□Sampling□Clock (N = 0) SCLSDA I2C□Master□SCL Clock (M = 8) IM[1:0] Digital□Signal□Processor (DSP) 8051uC & Control N[2:0] M[2:0] CMS IW[1:0] (SAP Input□Word□Size ) OW[1:0]□(SAP Output□Word□Size ) OUTMUX [1:0] (Audio□Output□Select - Control□Bits [1:0] from□SPDIF□Control□Register : 0x16) SPDIF_OUT / SDOUT2 SPDIF_MUTE (Mute□Control□Register : 0x09) SAPOUT_MUTE [1:0] OSC 512Fs Digital Audio Interface TAS3218 SLES235 JULY 2008 www.ti.com Figure Clocking System The TAS3218 has three digital inputs that accept discrete I discrete left-justified, and discrete right-justified PCM data. The TAS3218 has two digital outputs that provide discrete I discrete left-justified, and discrete right-justified PCM data.The second digital output can also be configured to provide S/PDIF encoded PCM data. The TAS3218 has a SPDIF input which is capable of routing an S/PDIF encoded signal through the device. This input is not processed by the digital audio processor (DAP) The clocking system for the device is illustrated in Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

S Slave Addr Sub AddrAck Ack Ack AckAck AckIMRes ResRes Res OMRes Res ResON OW ResIW ResCMS 31 25 24 23 21 18 16 15 13 11 9 7 5 3 1 0 I C Sub Address x 01 S Slave Addr Sub AddrAck Ack NAckRes ResAck Ack Res Ack MRes 31 23 15 7 6 2 0 CLOCK MASTER SELECTCMS

0 Clock slave mode

1 Master mode

SAP OUTPUT NORMALIZATIONON

0 Normalization disable

1 Normalization enable

OW[1] OW[0]

1 Reserved

IW[1] IW[0] IM[1] IM[0] OM[1] OM[0] www.ti.com SLES235 JULY 2008 Figure Clocking System I C Mapping When configured as the device clock master, an external crystal is used as a reference to an internal oscillator. In this mode of operation, all internal clocks are generated by the oscillator. LRCLKOUT is fixed at kHz (Fs) SCLKOUT is fixed at Fs MCLKOUT is fixed 256 Fs When configured as the device clock Slave, the DAP, MCU, and I C interface are derived from the external crystal, however the digital audio clocks are supplied externally. Internal analog clocks for the analog to digital converter (ADC) and digital to analog converter (DAC) are derived from the MCLKIN input. As a result, analog performance will depend on the quality of MCLKIN. Degradation in analog performance is to be expected depending on the quality of MCLKIN. The TAS3218 device does not include any internal clock error or click/pop detection/management. The muting of the outputs at updating of sample rate dependent coefficients must be initiated by the host system controller. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

LRCLK (note reversed phase) SCLK 2-Channel I S (Philips Format) Stereo Input Left Channel Right Channel LSBMSB MSB LSB 32 clks 32 clks 24-Bit Mode 20-Bit Mode 16-Bit Mode 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 TAS3218 SLES235 JULY 2008 www.ti.com MCLKOUT, SCLKOUT, and LRCLKOUT are passed through from the clock inputs MCLKIN, SCLKIN, and LCLKIN. MCLKIN 256 Fs is supplied externally SCLKIN Fs is supplied externally LRCLKIN Fs is supplied externally NOTE: In slave mode all incoming serial audio data must be synchronous to an incoming LRCLKIN of 32, 44.1 or kHz. The TAS3218 does not support the use of an external (i.e., MHz) clock input through into XTALI Serial data is input on pins SDIN1-3 on the TAS3218, allowing up to channels of digital audio input. The TAS3218 supports 16-, 20-, or 24-bit data in left, right, or I S serial data format. By default, all TAS3218 serial digital inputs are configured in the 24-bit I S format. The serial data input format is configurable via the SAP/Clock Settings Register. Serial data is output on pins SDOUT1-2, allowing up to channels of digital audio output. By default, the SDOUT data format is 24-bit, I S format at the same data rate as the input. The SDOUT1-2 output uses the SCLKOUT and LRCLKOUT signals to provide synchronization. SDOUT2 is multiplexed with an SPDIF output. NOTE: To avoid audio artifacts, I C commands to reconfigure the serial audio port (SAP) should not be issued as standalone commands, rather should be accompanied by mute and unmute commands. The TAS3218 uses the SCLK as a reference for both input and output samples. The negative edge of SCLK is used to output a new data bit, where as the positive edge of SCLK is used to sample incoming serial data. Discrete I S Timing I S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is LOW for the left channel and HIGH for the right channel. A bit clock running at Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3218 will mask unused trailing data bit positions. All data are presented in 2's complement form with MSB first. Figure SAP I S Format Fs Format Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

2-Channel Left-Justified Stereo Input Left Channel Right Channel LSBMSB MSB LSB 32 clks 32 clks 24-Bit Mode 20-Bit Mode 16-Bit Mode 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 LRCLK SCLK 2-Channel Right-Justified (Sony Format) Stereo Input Left Channel Right Channel LSBMSB MSB LSB 32 clks 32 clks 24-Bit Mode 20-Bit Mode 16-Bit Mode 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 15 14 13 10 9 8 7 6 5 4 3 2 1 012 11 SAP Input and Output Normalization TAS3218 www.ti.com SLES235 JULY 2008 Discrete Left-Justified Left-justified (LJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at Fs is used to clock in the data. The first bit of data appears on the data lines at the same time the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3218 will mask unused trailing data bit positions. All data are presented in 2's complement form with MSB first. Figure SAP Left-Justified Fs Format Discrete Right-Justified Right Justified (RJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/RCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before L/RCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3218 will mask unused leading data bit positions. All data are presented in 2's complement form with MSB first. Figure SAP Right-Justified Fs Format The TAS3218 supports SAP input and SAP output normalization. This supports simultaneous output to left-justified and I S devices. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

I S, Left, or Right Justified I S, Left, or Right Justified MCLKIN SCLKIN LRCLKIN SDIN MCLKOUT SCLKOUT LRCLKOUT SDOUT TAS3218 SLES235 JULY 2008 www.ti.com NOTE: The normalization function is only available in Slave mode. Figure SAP Output Normal Configuration (No Normalization) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

Data□Source TAS3218 DAC□1 (Left□Justified) DAC□2 (I S) I S LRCLK MSB I S□LRCLK I S□SDIN SCLK MSB Left□Channel Right□Channel MSB Left-Justified□LRCLK Left-Justified□SDOUT MSB Left□Channel Right□Channel I S

2 Left□Justified

Left□Justified SDIN Left□Justified LRCLK TAS3218 www.ti.com SLES235 JULY 2008 Figure SAP Output Configuration S to Left Normalization ON) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

Left Channel Right Channel MSB I S LRCLK I S SDOUT MSB Left Channel Right Channel MSB Left Channel TAS3218 SLES235 JULY 2008 www.ti.com Figure 10. SAP Output Configuration S to Left Normalization OFF) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

(I2S) DAC2 (Left□Jusitified) Left□Justified I2S LRCLK I2S SDOUT I2SSDIN Left□Justified LRCLK MSB Left□Justified LRCLK SCLK Left□Justified SDIN MSB Left□Channel Right□Channel MSB I2S□LRCLK I2S□SDOUT MSB Left□Channel Right□Channel MSB Left□Channel TAS3218 www.ti.com SLES235 JULY 2008 Figure 11. SAP Output Configuration (Left to I S Normalization ON) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

I2 S□LRCLK SCLK I2 S□SDIN MSB Left□Channel Right□Channel MSB Left□Justified□LRCLK Left□Justified□SDOUT MSB Left□Channel Right□Channel SPDIF Encoder SPDIF Control Register DAP Serial Audio Port (Receiver) SDOUT2 SDOUT2/ SPDIF Serial Audio Port Transmitter Control Signals SPDIF Encoder Channel Mute Control Output Selector Analog Interface SCLKIN LRCLKIN SDIN SPDIF_IN ANALOGIN “0” TAS3218 SLES235 JULY 2008 www.ti.com Figure 12. SAP Output Configuration (Left to I S Normalization OFF) The SPDIF encoder is a digital audio transmitter designed for use in consumer audio applications. Transmit data rates up to kHz are supported. The SPDIF encoder complies with the IEC-60958 interface standard. The SPDIF encoder creates a multiplexed bit stream, containing audio, status, and user data. The multiplexed data format is shown in Figure The data is then bi-phase mark-encoded and output. The hardware architecture of the S/PDIF Encoder can is shown in Figure Figure 13. SPDIF Encoder Hardware Architecture Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

Start of Channel Status Block Audio DataPreamble Bits: 0 3 4 7 8 27 28 29 30 31 Aux Data LSB MSB V U C P Channel A Channel A Channel A Channel B Channel BChannel B Z Y Y XX Validity Data User Data Parity Bit Frame 191 Frame 0 Frame 1 One Sub-Frame Channel Status Data TAS3218 www.ti.com SLES235 JULY 2008 Figure 14. SPDIF Frame Format SPDIF Encoder Operation The SPDIF encoder performs the multiplexing of audio, channel status, user, and validity flag. It also performs bi-phase mark encoding of the multiplexed data stream. Audio data for both left and right channels from the DAP are latched at the rising edge of the internal LRCLK, which marks the beginning of next sample cycle. The SPDIF encoder then multiplexes these samples with internally generated preambles, channel status, user data, validity flag, and parity. The channel status and validity flag are generated based on the settings in the SPDIF control registers while the user data is fixed to all zero. The bi-phase mark encoded signal is then output starting at the next rising edge of the internal LRCLK. The generated SPDIF stream is fixed to consumer mode linear audio PCM format. While the RESET input is low, the transmitter output, SPDIF_OUT, is forced to logic low level. Upon setting RESET high, the SPDIF encoder will remain inactive until the module reset is removed by writing to the RST bit of the control register. Then this module will wait for synchronization with the internal frame clock and starts encoding audio data. It is recommended to set all other SPDIF control register bits before releasing the module reset. Transmitter Control Register Table shows the M8051 SFR register map for the S/PDIF module control. Table M8051 SFR Register Map ADDR xx00 RST CP EMP xx01 CATEGORY L xx10 SR VL VR SRCNUM xx11 CLKAC WORDLEN The relationship of the M8051 SFR register map with I C registers is described in Table Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com Table Relationship of M8051 SFR Register Map With I C Registers RST: Module reset Normal operation Reset SPDIF-TX module (default) CP: Copy permit Copy prohibit (default) Copy permit EMP: Pre-emphasis No pre-emphasis (default) s 2-channel pre-emphasis CATEGORY: Category code 7-bit device category code. Default: 0101010 (digital sound processor) Generation status Generation or higher (default) Original SR: Sampling rate 00: 44.1 kHz 01: kHz (default) 10: Reserved 11: kHz VL: Validity for left channel Left channel data is valid (default) Left channel data is invalid VR: Validity for right channel Right channel data is valid (default) Right channel data is invalid SRCNUM: Source channel number 0000: Not specified 0001: 0010: (default) 0011: 1000: CLKAC: Clock accuracy 00: Level II, 1000 ppm 01: Level III, variable pitch shifted 10: Level ppm (default) 11: Reserved WORDLEN: Sample bit size 0000: bits (default) 0001: bits 0010: bits bits 0100: 1000: bits Others: Reserved I C Register Map for SPDIF Figure shows system accessible I C register mapping for controlling the SPDIF module. The mute control (MTE) uses the same control bits for controlling SDOUT2 mute at subaddress 0x09 and the module reset (RST) is mapped to subaddress 0x10 together with other power down control bits. Other control bits are mapped to subaddress 0x16. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

“0” 00000000000000 0 x 09 S Slave Addr Sub AddrAck Ack DITAMUXes SDOUT2 SDOUT1 DACs 31 18 17 12 11 10 9 8 7 2 1 0 0 x 16 ESFR 31 28 29 2430 27 23 22 21 20 1619 15 9 8 7 2 1 0 0 . . . 0 0 x 10 S Slave Addr Sub AddrAck Ack DITRST PWRDN CTL 31 8 7 6 0 Decode MUTE RSTZ Decode X Mute Ctl Force Mute Off Force Mute On

0 Powerdown, disable

Powerup, enable SPDIF-TX SPDIF_IN SDOUT2 TX-SAP CPS Slave Addr Sub AddrAck Ack OUTMUXEMP CLKAC WORDLEN SR VL VR SRCNUM CATEGORY L 000000 CATEGORY L SR SRCNUMVL VR CLKAC WORDLEN RST CP EMP Specification Coverage TAS3218 www.ti.com SLES235 JULY 2008 Figure 15. I C Register to EFSR and Hardware Connection Map The TAS3218 is covered by the following specificaiotns: IEC60956-1: Second Edition, 2004-03 IEC60956-3: Second Edition, 2003-01 IEC958-2: First Edition, 1994-07 Specifcation coverage details can be found in Table Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com Table Specification Coverage for TAS3218 (1) SPECIFICATION SECTION SUPPORTED REMARKS Interface Format (4) Yes Auto frame formatting IEC60958-1 Channel Status (5) Yes First bits fixed to 00. (consumer, linear PCM) Mode (software info delivery using IEC958-2 No Bits 28191 are fixed to all zero. b32191 of channel stat) Channel Status General (5.1) Yes First channel status bit fixed to b01: Fixed (00) b2: Register settable Channel Status Application (5.2.1) Yes Byte0 (control) b35: Register settable b67: Fixed (00) Category code is register settable, with default value Channel Status Application (5.2.2) Yes, with restriction 0101010L (Digital Sound Processor), but user data is Byte1 (category) fixed to all zero. b1619: Register settable Channel Status Application (5.2.2) Yes Byte2 (source and channel number) b2023: H/W auto set for left, for right channel) b2427: Register settable (32,44.1,48 kHz only) Channel Status Application (5.2.2) Yes, with restriction Byte3 (sampling freq and clock accuracy) b2829: Register settable IEC60958-3 H/W auto set according to register setting Channel Status Application (5.2.2) b3235 24-bit original output sample is truncated Byte4 (word length, original sampling Yes, partially to the specified word length. rate, Byte0, b1, b3639 Fixed to all zero (not indicated) Specifying categories other than 0101010L (Digital Category Code Groups (5.3.2) Yes, with restriction Sound Processor), especially those require non-zero user data is not recommended. User Data (6) All zero Clock accuracy indication is register settable. Timing accuracy (7.2.1) Yes Expected to set level I (50 ppm) for master mode (XTAL source) or level II (1000 ppm) for slave mode. Standard output buffer. Needs external SPDIF driver Line driver characteristics (7.3.2) No (ex.: optical driver) (1) Other sections of the specification not mentioned here are either considered irrelevant or covered elsewhere. IEC60958-4 is specific for professional thus, irrelevant. The TAS3218 is has analog stereo inputs that are multiplexed to one analog to digital converter (ADC). Additionally, the TAS3218 has one line output that can source any of the analog stereo inputs. The TAS3218 has three stereo digital to analog converters (DAC). The outputs of of DAC3 are designed to be used as a mW headphone amplifier or line driver. The other two DAC outputs are configured as stereo line drivers. Both the ADC and DAC blocks can be placed in power down when not used. Figure shows a block diagram of the Analog interface. The TAS3218 has a analog 10:1 input multiplexer and a 11:1 output multiplexer. These can accept analog stereo inputs up to Vrms. The outputs of the multiplexers are the stereo ADC and the line output. The ADC supports a sampling rate of kHz as a Clock Master Mode. In Clock Slave Mode, 32, 44.1, and kHz sampling frequencies are supported, based upon the master clock frequency. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 The TAS3218 has three stereo digital to analog converters (DACs). Each DAC can operate a maximum of kHz. The DACs provide a kHz sampling frequency in master mode. In slave mode 32, 44.1, and kHz are supported, based upon the master clock frequency. Two of the DACs are configured for providing line outputs. One of the stereo DACs has the capability to drive either a line out or to be used as a headphone (HP) amplifier. The stereo headphone amplifier is designed to drive up to mW per channel into a headphone speaker load of Ω The headphone output is a single ended configuration using series 16- Ω resistors and AC-coupling capacitors. The TAS3218 includes three multiplexed stereo line driver outputs. The input to each of these line drives can be selected to use one of the ten stereo analog input channels. Additionally, line driver output can output the

contents

DAC. Each line driver is capable of driving up to a k Ω load. NOTE: To avoid audio aritifacts when using the line driver outputs, I C commands to reconfigure the lineout multiplexers should not be issued alone, rather should be accompanied by a mute/unmute sequence to all analog audio channels of the TAS3218. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

(Stereo) Amp MUX 10:1 LINEOUT 1 L/R (Stereo) Amp DAC 1–1 D2S Line Amp MUX1 MUX 11:1 VREF VREF and I BIAS ADCAmp Line Amp MUX 10:1 LINE IN 10 ch (Stereo)

1 V (single-ended)

DAC 2–1 D2S Line Amp D2S HP Amp DACOUT 1 L/R (Stereo) DACOUT 2 L/R (Stereo) HPOUT L/R (Stereo) Register Map for MUTE Control 0x09 DACOUT1 Pin Name DAC 1 MUTE Block LINEOUT1 13 12 BITPin Name MUX1 MUTE Block LINEOUT2 15 13 BITPin Name MUX2 MUTE Block LINEOUT3 17 14 BITPin Name MUX3 MUTE Block DACOUT2 BITPin Name DAC 2 MUTE Block 5 4 HPOUT BITPin Name DAC 3 MUTE Block 7 6 BIT * 1 HW Mute control www.ti.com Figure 16. Analog Input/Output Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 The embedded M8051 WARP microcontroller provides the overall control for the TAS3218 device. This control includes device initialization, memory loading, I C transactions, control pin operations, and participation in most processing tasks requiring multi-frame processing cycles. The microcontroller has its own data RAM for storing intermediate values and queuing I C commands, a fixed boot program ROM and a programmable program RAM. The microprocessors boot program cannot be altered. The microcontroller has specialized hardware for a master and slave interface operation, Volume Updates, and a programmable interval timer interrupt. The 256 bytes of Internal Data Memory address space is accessible using indirect addressing instructions (including stack operations). However, only the lower 128 bytes are accessible using direct addressing. The upper 128 bytes of direct address Data Memory space are used to access ESFRs. Register Banks There are four directly addressable register banks, only one of which may be selected at one time. The register banks occupy Internal Data Memory addresses from hex to hex. Bit Addressing The bytes of Internal Data Memory that occupy addresses from hex to hex are bit-addressable. SFRs that have addresses of the form 1XXXX000 binary are also bit-addressable. Scratchpad Internal data memory occupying direct addresses from hex to hex can be used as scratch pad registers or for the stack. External Data Memory External Data RAM occupies a 64K address space. This space contains the External Special Function Data Registers ESFRs. The ESFRs permit access and control of the hardware Processor. Figure shows the boot-up sequence. M8051 MCU ROM code follows this sequence after device reset release. After Micro completes boot up application code (RAM code), the microcontroller switches the program counter from ROM to RAM code by pc_source(esfr 0xFD). Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

DAP -> Idle uP -> Initialization I2C BUS -> HIGH uP Flushs Internal RAM uP -> Cmd to Flush Delay Memory uP Flushs External RAM uP Flushs DAP Coef/Data RAM uP Sets default H/W configuration Enable DAP Processing start RAM Flushed RESET = False RESET = True RAM Flushed Delay Memory Flush command issued Variables initialized RAM Flushed RAM Flushed Default Values Loaded Enable I2C Master mode Setup I2C Master I /F Initialize DPLL PLL Locked and Stable Successful Load Zero length data header has been read

3 Reads tried

SCL, SDA = LOW for 1ms detected Start-up Oscillator Any State uP initialize its variables uP Flushs DAP Instruction RAM uP Flushs uP Instruction RAM RAM Flushed EEPROM Load Process Disable I2C Master mode Switch ROM to RAM IDLE uP Start App uP Code Check GPIO 1 Load□default DAP Program and□coefficient GPIO1 = Low GPIO1 output Low Loaded Setup I2C Slave I/F GPIO1 = High Main IDLE loop Test Processing Routine Test command received I2C Slave download process Slave download command received Successful Load Zero length data header has been received TAS3218 SLES235 JULY 2008 www.ti.com Figure 17. Boot-Up Sequence Detailed information about the boot-up sequence is described in Table Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 Table Process I C bus high uP Flush Internal RAM Clear micro internal RAM (256 byte) uP Flush External RAM Clear micro external RAM (2048 byte) uP command to Flush Delay clr_dly_ram (0xc0 bit(3)) Memory uP initialize variables Initialize variables mute0_t mute1_t Default mutez control mute2_t reset_dac_mod 0xff reset_adc_sinc 0x03 uP set default H/W configuration clock_control1 0x0a clock_delay_control2 0x05 clock_delay_sel 0x80 i2s_word_byte 0x22 IW/OW: bit i2c_mode_byte 0x22 IM/OM: I S sap_en uP Flush uP Instruction RAM mem_sel 0x02 Clear uP Instruction RAM (16384Byte) uP Flush DSP Instruction RAM mem_sel 0x01 Clear DSP Instruction RAM (3328W) Clear DSP lower coefficient RAM (1024 and data uP flush DSP lower coef/data RAM mem_sel 0x00 (48 bit) RAM (768 Enable I C master I/F Setup I C master I/F mode (enable interrupt 10) EEPROM load Disable I C master mode and i2c_ms_ctl Switch control MUX to slave I C port enable slave I/F Switch ROM to RAM pc_source If (gpio_in_3_0 Host_dsp keep DSP turned off Load default DSP host_dsp else Program and coefficient Host_dsp turn on DSP GPIO1 output low Enable GPIO output mode, and output low. RESET is an asynchronous control signal that restores all TAS3218 components to the default configuration. When a reset occurs, the Digital Audio Processor (DAP) is put into an idle state and the M8051 MCU starts initialization. A reset can be initiated by inputting logic on the reset pin A reset will also be issued at power up sequencing by the internal 1.8V regulator power sub-system. NOTE: There is a 1.3-s de-glitch filter on the RESET pin. During a power up sequencing process, RESET should be held low until the DVDD and AVDD power inputs have reached a voltage of 3.0 As long as the RESET pin is held a logic the device is in the reset state. During this reset state, all I C and Serial Data bus operations are ignored. The I C interface SCL and SDA lines goes HIGH and remain in that state until device initialization has completed. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

I C Chip Select GPIO Pins TAS3218 SLES235 JULY 2008 www.ti.com Power-Up Sequence The rising edge of the RESET pin begins the initialization of housekeeping functions by clearing memory and setting the default register values. After housekeeping initialization is complete, the TAS3218 enables the master I C interface. The TAS3218 then uses the master I C interface to determine if an external memory device is present. External Memory Device Present Using the master I C interface, the TAS3218 will automatically test to see if an external memory device is at address 1010xxx. The value xxx can be chip selects, other information, or dont care depending on the EEPROM selected. If an external memory device is present and it contains the correct header information along with one or more blocks of program/memory data, the TAS3218 will automatically download the M8051 MCU program RAM, coefficient and/or data RAM from the external EEPROM. This download is considered complete when an end of program header is read by the TAS3218. The memory block structure of the external memory device is available in Master I2C Load RAM Block Formats At this point, the TAS3218 will disable the master I C interface, enable the slave I C interface, and start normal operation. After a successful download, the M8051 MCU program counter will be reset and the downloaded M8051 MCU and DSP application firmware will control execution. External Memory Device Not Present If no external EEPROM is present or if an error occurred during the external memory device read, the TAS3218 will disable the master I C interface, enable the slave I C interface. The default slave configuration will then be loaded from the ROM into the M8051 MCU and DSP. In this default configuration, the TAS3218 will stream audio from input to output if the GPIO1 pin pulled LOW. NOTE: The master and slave interfaces do not operate simultaneously, thus when one interface is enabled, the other is disabled. The CS pin on the TAS3218 allows up to two TAS3218 devices to be addressed by the I C bus via an external host controller without the need for external logic. Table and Table list the I C address for each I C interface. Table I C Slave Addressing SLAVE ADDRESS CS 0x68/69 0x6A/6B Table I C Master Addressing SLAVE ADDRESS CS 0xA0/A1 0xA2/A3 The TAS3218 has two level-sensitive GPIO pins, GPIO1 and GPIO2, that are firmware programmable. Upon power up or following a RESET the GPIO1 pin becomes an input, and has a special function as described in GPIO1 Pin Function Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 GPIO1 Pin Function After RESET or powerup initialization, if no EEPROM is present, a memory error occurs, or SDA and SCL are pulled LOW for ms, then TAS3218 will disable the master I C interface and enable the slave I C interface initialization, to load the slave default configuration. When GPIO1 has been pulled HIGH through a 1020-k resistor the TAS3218 will then initialize in the default configuration with the serial data outputs not active. Once the TAS3218 has completed its default initialization procedure, with the status register updated and the I C slave interface enabled, then the GPIO1 pin will become an output and will be driven LOW. Following the High to Low transition of the GPIO1 pin, the system controller can access the TAS3218 through the I C interface and read the status register to determine the load status. If a memory read error occurs the TAS3218 will report the error in the status register. When GPIO1 has been pulled LOW through a 1020-k resistor to permit a simple functional device test, the GPIO1 pin can be pulled low using external logic and a 1020-k resistor. In this case, once the TAS3218 has completed its default test initialization procedure, with the status register updated and the I C slave interface enabled, then the TAS3218 will stream audio from the input SDIN1 to outputs SDOUT1 and SDOUT2. At this point the GPIO1 pin will become an output and will be driven LOW. If the external logic is no longer driving the GPIO1 pin low after the load has completed (100 ms following a RESET if no EEPROM is present), then the state of the GPIO1 pin can be observed. At this point the system controller can access the TAS3218 through the I C interface and read the status register to determine the load status. NOTE: If the GPIO1 pin state is not observed, the only indication that the device has completed its initialization procedure is that the TAS3218 will stream audio and the I C slave interface has been enabled. NOTE: Some I C masters will hang when they receive a NAC during an I C transaction. Once the TAS3218 has been programmed either through a successful boot load or via slave I C download, the operation of GPIO1 can be programmed to be an input or an output. General Purpose I/O Ports (GPIOs) In I C slave mode, the GPIO ports can be used as true general-purpose ports. Each port can be individually programmed, via the I C bus, to be either an input or an output port. The default assignment for all GPIO ports, in I C slave mode, is an input port. When a given GPIO port is programmed as an output port, by setting the appropriate bit in the bit field GPIODIR of subaddress 0x0C to logic the logic level output is set by the logic level programmed into the appropriate bit in bit field GPIO IN OUT. The I C bus then controls the logic output level for those GPIO ports assigned as output ports. When a given GPIO port is programmed as an input port by setting the appropriate bit in bit field GPIODIR to logic the logic input level into the GPIO port is written to the appropriate bit in bit field GPIO IN OUT. The I C bus can then be used to read bit field GPIO IN OUT to determine the logic levels at the input GPIO ports. Whether a given bit in the bit field GPIO IN OUT is a bit to be read via the I C bus or a bit to be written to via the I C bus is strictly determined by the corresponding bit setting in bit field GPIODIR. In the I C slave mode, the GPIO input ports are read every GPIOMICROCOUNT Micro Clocks, as was the case in the I C master mode. However, parameter GPIO_samp_int does not have a role in the I C slave mode. If a GPIO port is assigned as an output port, a logic bit value is supplied by the TAS3218 for this GPIO port in response to a read transaction at subaddress 0x0C. If the GPIO ports are left in their power turn on default state, they are input ports with a weak pull-up on the input to VDSS. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

S Slave Addr Sub AddrAck Ack WDE See Note A Res Reset Reset “0” (default state) enables watchdog timer GPIO IN/OUT GPIO DIR 31 30 27 1 1 0 Ack Ack AckGPIOMICROCOUNT MS BYTE GPIOMICROCOUNT LS BYTE AckGPIO_samp_int0 24 23 15 7 0 Watchdog Timer MICRO_CLK MICRO_CLK Data_IN_OUT Data Path Switch Sampling Logic Decode 2^16Decode 2^16 8051 uC Firmware 8051 uControl Down Counter LD Q D GPIO1 ENB Q D GPIO1 ENB TAS3218 SLES235 JULY 2008 www.ti.com Watchdog Timer There is a hardware watchdog timer in the TAS3218 that can be programmed in the customer application code to monitor the microprocessor activity. If the watchdog timer expires it will generate a reset to the 8051 microprocessor. GPIOMICROCOUNT, in subaddress 0x0C, is used in order to trigger GPIO input/output and the monitoring to the DSP diagnostic count. Because of this, the value selected for GPIOMICROCOUNT must be chosen to provide a good tradeoff of between micro overheard and adequate execution frequency of these processes. The default value for this counter is 0x5820 which corresponds to a period of 1.25 ms. Figure shows the GPIO register, the GPOI interface, and a typical user application code implementation of the watchdog timer reset. Determines how many consecutive Logic samples (where each sample is spaced by GPIOMICROCOUNT Micro_clks) are required to read a Logic on a GPIO input port Figure 18. GPIO Ports Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

I C Control Interface General I C Transactions Start (by master) Acknowledge (by TAS3208) (See Note A) Start Condition I2C_SDA while I2C_SCL = 1↓ MSB MSB–1 MSBMSB LSBLSBAck AckAckR/WCS1CS0S S0 0 1 1 1 MSB–2 LSB Stop Condition I2C_SDA while I2C_SCL = 1↑ Acknowledge (by receiver) Acknowledge (by receiver) Read or Write (by master) Stop (by master) I2C_SDA I2C_SCL Data Byte (by transmitter) Slave Address (By master) Data Byte (by transmitter) TAS3218 www.ti.com SLES235 JULY 2008 The M8051 microprocessor receives and distributes I C data to the I C bus controllers, and participates in most I C processing tasks requiring multi-frame processing cycles. The master and slave interfaces do not operate simultaneously. The I C communication protocol for the I C slave mode is shown in Figure Bits CS1 and CS0 in the TAS3218 slave address are compared to the logic levels on pins CS0 and CS1 for address verification. This provides the ability to address up to four TAS3218 chips on the same I C bus. Figure 19. I C Slave Mode Communication Protocol The I C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data be transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. The master generate the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The slave holds SDA LOW during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit byte). All compatible devices share the same signals via a bi-directional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A read transaction requires that the master device first issue a write transaction to give the TAS3218 the sub address to be used in the read transaction that follows. This sub address assignment write transaction is then followed by the read transaction. For write transactions, the sub address is supplied in the first byte of data written, and this byte is followed by the data to be written. For write transactions, the sub address must always be included in the data written. There cannot be a separate write transaction to supply the sub address, as was required for read transactions. If a subaddress assignment only write transaction is followed by a second write transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted by the TAS3218 as another sub address replacing the one previously written. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

Read/ Write Bit Sub Address First Data Byte Other Data Bytes Last Data Byte Acknowledge Acknowledge Acknowledge R/W Ack A7 Ack Ack Ack AckD7 D0 D0 D0D7 D7A0A1A6A5A6 SS SS SS SS SSA1 A0 Stop Condition Acknowledge Acknowledge I C Device Address and Read/Write Bit I C Device Address and Read/Write Bit Sub Address First Data Byte Other Data Bytes Last Data Byte Acknowledge Acknowledge Acknowledge Not Acknowledge SS A0 A0 D0 AckR/W Ack D7 D7 D7D0 Ack AckD0SSA6AckA6 SS A0 SS SS SSR/W Ack Start Condition Repeat Start Condition TAS3218 SLES235 JULY 2008 www.ti.com Multiple Byte Write A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are transmitted by the master device to slave as shown in Figure After receiving each data byte, the TAS3218 will respond with an acknowledge bit. Figure 20. Multiple Byte Write Transfer Multiple Byte Read A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes are transmitted by the TAS3218 to the master device as shown in Figure Except for the last data byte, the master device will respond with an acknowledge bit after receiving each data byte. Figure 21. Multiple Byte Read Transfer Random I C Transactions Supplying a subaddress for each subaddress transaction is referred to as random I C addressing. For random I C read commands, the TAS3218 responds with data, a byte at a time, starting at the sub address assigned, as long as the master device continues to respond with acknowledges. If a given sub address does not use all bits, the unused bits are read as logic I C write commands, however, are treated in accordance with the data assignment for that address space. If a write command is received for a biquad sub address, for example, the TAS3218 expects to see five 32-bit words. If fewer than five data words have been received when a stop command (or another start command) is received, the data received is discarded. Sequential I C Transactions The TAS3218 supports sequential I C addressing. For write transactions, if a sub address is issued followed by data for that sub address and the fifteen sub addresses that follow, a sequential I C write transaction has taken place, and the data for all sub addresses is successfully received by the TAS3218. For I C sequential write transactions, the sub address then serves as the start address and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many sub addresses are written to. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last sub address, the data for the last sub address is discarded. However, all other data written is accepted; just the incomplete data is discarded. Sequential read transactions do not have restrictions on outputting only complete sub address data sets. If the master does not issue enough data received acknowledges to receive all the data for a given sub address, the master device simply does not receive all the data. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

I C Master Mode Operation Stop Condition Acknowledge Acknowledge I C Device Address and Read/Write Bit I C Device Address and Read/Write Bit Sub Address First Data Byte Other Data Bytes Last Data Byte Acknowledge Acknowledge Acknowledge Not Acknowledge SS A0 A0 D0 AckR/W Ack D7 D7 D7D0 Ack AckD0SSA6AckA6 SS A0 SS SS SSR/W Ack Start Condition Repeat Start Condition TAS3218 www.ti.com SLES235 JULY 2008 If the master device issues more data received acknowledges than required to receive the data for a given sub address, the master device simply receives complete or partial sets of data, depending on how many data received acknowledges are issued from the sub address(es) that follow. I C read transactions, both sequential and random, can impose wait states. For the standard I C mode (SCL 100 kHz), worst-case wait state times for an 8-MHz microprocessor clock is on the order of Nominal wait state times for the same 8-MHz microprocessor clock is on the order of For the fast I C mode (SCL 400 kHz) and the same 8-MHz microprocessor clock, worst-case wait state times can extend up to 10.5 s in duration. Nominal wait state times for this same case lie in a range from s to 4.6 Increasing the microprocessor clock frequency lowers the wait state times and for the standard I C mode, a higher microprocessor clock can totally eliminate the presence of wait states. For example, increasing the microprocessor clock to MHz results in no wait states. For the fast I C mode, higher microprocessor clocks shortens the wait state times encountered, but does not totally eliminate their presence. I C master mode operation is enabled following a reset or power on reset. The TAS3218 uses the master mode to download from EEPROM the memory following. Micro program memory Micro extended memory DSP program memory DSP coefficient memory DSP data memory The TAS3218, when operating as an I C master, can execute a complete download of any internal memory or any section of any internal memory without requiring any wait states. When the TAS3218 operates as an I C master, it generates a repeated start without an intervening stop command while downloading program and memory DATA from an external EEPROM. When a repeated start is sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to quickly transfer large blocks of data. Figure 22. Multiple Byte Read Transfer The TAS3218 will query the bus for an I C EEPROM at an address 1010xxx. The value xxx can be chip selects, other information, or dont cares depending on the EEPROM selected. The first act of the TAS3218 as master will be to transmit a start condition along with the device address of the I C EEPROM with the read/write bit cleared (0) to indicate a write. The EEPROM acknowledges the address byte, and the TAS3218 send a sub address byte, which the EEPROM will acknowledge. Most EEPROMs have at least 2-byte addresses and will acknowledge as many as are appropriate. At this point, the EEPROM sends a last acknowledge and becomes a slave transmitter. The TAS3218 acknowledges each byte repeatedly to continue reading each data byte that is stored in memory. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com The memory load information starts with reading the header and data information that starts at sub-address of the EEPROM. This information must be stored in a sequential memory addresses with no intervening gaps. The Data block is contiguous blocks of data that immediately follow the headers locations. The TAS3218 memory data can be stored and loaded in (almost) any order. Additionally this addressing scheme permits portions of the TAS3218 internal memories to be loaded. Figure 23. EEPROM Address Map The TAS3218 will sequentially read EEPROM memory and load its internal memory unless it does not find a valid memory header block, is not able to read the next memory location because the end of memory was reached, detects a check sum error, or reads a end of program header block. When it encounters a valid header or read error, the TAS3218 will attempt to read the header or memory location three times before it determines that it has an error. If the TAS3218 encounters a Check Sum error it will attempt to re-read the entire block of memory two more times before it determines that it has an error. NOTE: Once the micro program memory has been loaded, it can not be reloaded until the TAS3218 has been RESET. If an error is encountered TAS3218 terminates its memory load operation, loads the default configuration for both the M8051 MCU and DSP from the embedded ROM, and disables further master I C bus operations. If an end of program data block is read, the TAS3218 has completed the initial program load. The I C master mode utilizes the starting and ending I C check sums to verify a proper EEPROM download. The first 16-bit data word received from the EEPROM is the I C check sum at sub address 0x00, is stored and compared against the 16-bit data word received for last subaddress, the ending I C check sum and the check sum that is computed during the download. These three values must be equal. If the read and computed values do not match, the TAS3218 sets the memory read error bits in the Status register and repeats the download from the EEPROM two more times. If the comparison check again fails the third time, the TAS3218 sets the micro program to the default value. NOTE: When acting as an I C master, the data rate transfer is fixed at 375 kHz. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

I C Slave Mode Operation TAS3218 www.ti.com SLES235 JULY 2008 The I C slave mode is the mode that is used to change configuration parameters during operation and perform program and coefficient downloads from a master device. The latter can be used to replace the I C master mode EEPROM download. The TAS3218 uses the slave mode to load the memory the: Micro program memory Micro extended memory DSP program memory DSP coefficient memory DSP data memory Update coefficient and other control values Read status flags The TAS3218 support both random and sequential I C transactions. The TAS3218 I C slave address is 011010X, where the first bits are the TAS3218 device address and the final bit is set by the TAS3218 internal microprocessor at power-up. The internal microprocessor derives the last bit from an external pin (pin CS) which is pulled up or down to create two unique addresses for control of multiple-TAS3218 part applications. The pulldown resistance of CS creates a default address when no connection is made to the pin. The TAS3218 I C block does respond to the broadcast address (00h). NOTE: When acting as an I C slave, data rate transfer is determined by the master device on the bus. However, the setting of I C parameter N at sub-address 0x01 does play a role in setting the maximum possible data transfer rate. In the I C slave mode, bit rates other than (and including) the I C-specific 100 Kbps and 400 Kbps bit rates can be obtained, but N must always be set so that the over-sample clock into the I C master and slave controllers is at least a factor of higher in frequency than SCL. N is a special case. When N a mode is enabled that detects I C frames and enables the TAS3218 I C interface to reset and continue operation after receiving an invalid I C frame. Table I C Slave Addresses SLAVE ADDRESS CS 0x68/69 0x6A/6B Table I C Master Addresses SLAVE ADDRESS CS 0xA0/A1 0xA2/A3 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

(DSP) Arithmetic Unit Overview TAS3218 SLES235 JULY 2008 www.ti.com The arithmetic processor is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks. The primary are: Two pipe parallel processing architecture 48-bit datapath with 76-bit accumulator Hardware single cycle multiplier (28 48) Three 48-bit general purpose data registers One bit coefficient register 48-bit adder 28-bit adder Shift right, shift left Bi-modal clip Log2/Alog2 Magnitude truncation Read/read/write single-cycle memory access Data input is 48-bit complement multiplexed in from SAP immediately following FSYNC pulse Data output is four 32-bit complement busses Separate control for writing to delay memory Separate coefficient memory (28-bit) and data memory (48-bit) Linear Feedback Shift Register (LFSR) in the instruction register doubles as a random number generator in normal operating mode Coefficient RAM, Data RAM, LFSR seed, Program counter, and memory pointers are all mapped into the same memory space for convenient addressing by the micro Memory interface block contains four pointers, two for data memory and two for coefficient memory Data Format Figure shows the data word structure of the arithmetic unit. Eight bits of overhead or guard bits are provided at the upper end of the 48-bit word, and bits of computational precision or noise bits are provided at the lower end of the 48-bit word. The incoming digital audio words are all positioned with the most significant bit abutting the 8-bit overhead/guard boundary. The sign bit in bit indicates that all incoming audio samples are treated as signed data samples. The arithmetic engine is a 48-bit (25.23 format) processor consisting of a general-purpose 76-bit arithmetic logic unit and function-specific arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks) always involve 48-bit words and 28-bit coefficients (usually I C programmable coefficients). If a group of products are to be added together, the 76-bit product of each multiplication is applied to a 76-bit adder, where a DSP-like multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC operation to maintain precision in the intermediate computational stages. To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations, intermediate overflows are permitted, and it is assumed that subsequent terms in the computation flow will correct the overflow condition. The memory banks include a dual port data RAM for storing intermediate results, a coefficient RAM, and a fixed program ROM. Only the coefficient RAM, assessable via the I C bus, is available to the user. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

S S S S S S Precision/Noise Bits 16-bit audio 18-bit audio 20-bit audio 24-bit audio 32-bit audio 10110111 (–73) –73 10000100 (–124) –124 01010111 (57) –169 + 00111011 (59) + 59 10010010 (–110) –110 8-Bit ALU Operation (without saturation) Rollover TAS3218 www.ti.com SLES235 JULY 2008 Figure 24. Arithmetic Unit Data Word Structure Figure 25. DSP ALU Operation with Intermediate Overflow Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

0 ... 0 Scaling Headroom Data (24-Bits) 5 8 12 8 31 75–71 70–63 62–39 38–31 30–0 DAP Data Path Data Representation Fractional Noise 48-Bit Clipping POS48 = 0x7F_F FFF_FFFF _FF NEG48 = 0x80_0 000_0000 _00 32-Bit Clipping POS40 = 0xXX_ 7FFF_FFFF _XX NEG40 = 0 8000_0000 _XXxXX_ 28-Bit Clipping POS20 = 0xXXXXX_ 7FFF_FFF NEG20 = 0xXXXXX_ 8000_000 TAS3218 SLES235 JULY 2008 www.ti.com Figure 26. DSP Data Path Data Representation Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

LOG, ALOG, NEG, ABS, or THRU Barrel Shift NEG, ABS, or THRU Multiply Legend Register ADD Operand A Operand B “ZERO” VOL 28-bit data 48-bit data 76 76-bit data 32-bit data DATA RAM 1024 24X DATA RAM 768 48X 48 28 48 24-bit data Output Register File (DO8–DO8) Delay RAM VOL (5 LSBs) B L MD MC ACC BR LR MR COEF RAM

1.2 K 24

X DI (3 LSBs) LFS DL YO DL YI TAS3218 www.ti.com SLES235 JULY 2008 Figure 27. DSP Data Path Architecture Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Audio_out1 Audio_out2 Audio_out3 Audio_out4 SPDIF(L) SPDIF(R)DAC (TDM) Audio_out5 Audio_out6 Audio_out7 Audio_out8 Ext_mem (2nd Gen) SDOUT 1(L) SDOUT1(R ) SDOUT 2(L) SDOUT2(R ) Inside core Outside core Micro Data 48 -bit Datapath 28 x 48-bit Multiplier 76-bit Accumulator Coef RAM (1K x 28 ) Data RAM (768 x 48 ) Program RAM (3.25 K x 55 ) DSP Controller Memory Interface Delay Memory (17408 x 24 ) 8-bit MCU (8051 ) Internal Data RAM (256 x 8) External Data RAM (2K x 8) Program RAM (16 K x 8) DSP Delay Control MICRO Delay Memory TAS3218 SLES235 JULY 2008 www.ti.com Figure 28. DSP Output Register Configuration Memory size K 1024 Figure 29. DSP, MCU, and Memory Interfaces The Delay Memory Interface (DMIF) is the interface block between the DSP core and the delay memory. The DMIF blocks primary purpose is to keep track of twenty four sets of delay memory pointers that are initially set up by the micro controller through an I C command(s). Eight of the pointers are used to write/retrieve 48-bit data (full-precision intermediate) and the other sixteen for 24-bit data (post quantized). Thus to support 48-bit word reverb delay, two RAM locations must be used. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

Ext ALU First Stage ALU Second Stage Data Memory Load Coefficient Memory Load Memory Store P1OP 53–49 P2OP 48–42 MOP1 AD1 41–37 36–27 MOP2 AD2 23–1426–24 MOP3 AD3 9–013–10 TAS3218 www.ti.com SLES235 JULY 2008 The key (one pointer access per access cycle) Access cycle DSP clocks Self clearing INIT pin used to clear all memory to zero Fully synchronous DP1DP15: sixteen 24-bit pointers RP1RP8: eight 48-bit (full precision) pointers Since all of the pointers are contiguous, it is only necessary to write the address END point. For example, if DP1 is to be a three-sample delay, the register DP1 should be set to 0x003. If RP1 is to be a sample delay, the register RP1 should be set to the value of DP15 All of the DP1-16 and RP1-8registers must be set to a minimum of a one sample delay (one or two words). DP1 Start address is defined as 000x0 DP2 Start address is equal to DP1 end address ... RP1 Start address is equal to DP16 end address ... RP8 Start address is equal to RP7 end address Since the start/stop address for each pointer is programmable anywhere in the delay RAMs address space, the delay for any one channel can be anywhere in the delay RAM. There is, however, no address space collision avoidance logic to separate the pointers. The user (or micro) must take care to avoid overlapping the address spacing of each pointer. Pointer register address endpoint registers DP1-DP16 and RP 1-RP8 are typically written only during the initialization (fast load) mode of the device. Writing to these registers while the TAS3218 DSP core is accessing the pointers may cause the pointers to cross the address space of another pointer. To write to the delay RAM, the TAS3218 DSP core controller must present the data to be written on the PT_DATA bus (LS bit always in bit zero of the bus), select the pointer to be accessed by driving the PT_SEL pins, and assert the PT_WZ pin for a minimum of four clocks. The pointer will not increment until a write has been performed and the PT_WZ pin has been de-asserted. To perform a read, the PT_OUT bus may be read four clocks after PT_SEL is driven. TAS3218 has a 55-bit instruction word. Each instruction has five independent operations, which can load two operands from data memory and coefficient memory, store the result into data or coefficient memory and perform two parallel arithmetic operations. Figure 30. Instruction Word The TAS3218 instruction set is a superset of the TAS3218 instruction set, extending the DSP processing capabilities for improved efficiency of FIR operations as well as extending the addressable memory space. The Ext instruction bit (bit 54) has been added to extend the internal memory address space by bit, increasing the memory space from to words. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

Contains two dummy bits in every instruction word of the EEPROM. All TAS3208 tool compilers always ZERO to these dummy bits in the compile EEPROM image. DUM ALU First Stage ALU Second Stage Data Memory Load Coefficient Memory Load Memory Store P1OP P2OP MOP1 AD1 5 10 MOP2 AD2 103 MOP3 AD3 104 54–55 53–49 48–42 41–37 36–27 23–14 26–24 9–0 13–10 54-BIT INSTRUCTION New “Ext”-ended field Extension bit designates offset of 1K to these address references for LD/ST operations Ext ALU First Stage ALU Second Stage Data Memory Load Coefficient Memory Load Memory Store

0 P1OP P2OP MOP1 AD1 MOP2 AD2 MOP3 AD3

54 53–49 48–42 41–37 36–27 23–14 26–24 9–0 13–10 DSP Instruction Set TAS3218 SLES235 JULY 2008 www.ti.com The superset instruction word maintains backward compatibility with the 54-bit instruction word of the TAS3218 device, since the bit instruction word required dummy storage of bits in the EEPROM. Figure 31. Instruction Word As shown in Figure the extension bit designates an offset of to all three addresses in the instruction word. However, it should be noted that both data and coefficient memory addresses above the boundary are reserved for housekeeping processing tasks. Any attempt to write to these addresses may corrupt the audio output. Figure 32. Instruction Word Extension Field Please see the TAS3xxx Programmers Guide for detailed information regarding programming of this device. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

(1) PACKAGE DISSIPATION RATINGS (1) (2) RECOMMENDED OPERATING CONDITIONS TAS3218 www.ti.com SLES235 JULY 2008 MIN MAX UNIT DVDD Supply voltage range 0.5 3.8 V AVDD Supply voltage range 0.5 3.8 V 3.3-V TTL 0.5 VDDS 0.5 V I Input voltage range 3.3-V Analog 0.5 AVDDS 0.5 V 1.8-V LVCMOS 0.5 AVDD (2) 0.5 3.3-V TTL 0.5 VDDS 0.5 3.3-V Analog 0.5 AVDDS 0.5 V O Output voltage range V 0.5 DVDD (3) 0.5 1.8-V LVCMOS 0.5 AVDD (4) 0.5 I IK Input clamp current I or V I DVDD) mA I OK Output clamp current O or V O DVDD) mA T stg Storage temperature range 150 C Lead temperature 1.6 mm (1/16 inch) from case for seconds 260 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) AVDD is an internal 1.8-V supply derived from a regulator in the TAS3218 chip. Pin XTALI is the only TAS3218 input that is referenced to this 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALI. (3) DVDD is an internal 1.8-V supply derived from regulators in the TAS3218 chip. DVDD is routed to DVDD_BYPASS_CAP to provide access to external filter capacitors, but should not be used to source power to external devices. (4) Pin XTALO is the only TAS3218 output that is derived from the internal 1.8-V logic supply AVDD. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALO. AVDD is also routed to AVDD_BYPASS_CAP to provide access to external filter capacitors, but should not be used to source power to external devices. PACKAGE T A 25C POWER RATING DERATING FACTOR ABOVE T A 25C T A 70C POWER RATING TQFP PZP 2.78 W 28.7C/W 1.22 W (1) High-K Board, 105C junction (2) Refer to PowerPAD Thermally Enhanced Package Application Report (literature number SLMA002 PARAMETER MEASUREMENT MIN NOM MAX UNIT DVDD Digital supply voltage 3.3 3.6 V AVDD Analog supply voltage 3.3-V Analog 3.3 3.6 V 3.3-V TTL V IH High-level input voltage V 1.8-V LVCMOS (XTL_IN) 1.26 1.95 3.3-V TTL 0.8 V IL Low-level input voltage V 1.8-V LVCMOS (XTL_IN) 0.54 Operating ambient air temperature range T A C (guarantying parametric) T J Operating junction temperature range 105 C Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

CHANNEL, INPUT TO OUTPUT AUDIO SPECIFICATIONS DIGITAL FILTERS TAS3218 SLES235 JULY 2008 www.ti.com T A =25C, AVDD 3.3 DVDD 3.3 Fs (audio) kHz, Clock source from XTALI, AES17 filter, second order kHz low pass filter (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT A-in ADC DSP DAC Lineout WTD Overall dynamic dB range A-in MUX Lineout A-WTD T A =25C, AVDD 3.3 DVDD 3.3 Fs (audio) kHz, Clock source from XTALI, AES17 filter, second order kHz low pass filter (unless otherwise noted) PARAMETER MIN TYP MAX UNIT ADC Decimation Filter, Fs kHz Filter gain from to 0.39 Fs 0.1 dB Filter gain at 0.4125 Fs 0.25 dB Filter gain at 0.45 Fs dB Filter gain at 0.5 Fs 17.5 dB Filter gain from 0.55 Fs to Fs dB Filter group delay 17/Fs s DAC Interpolation Filter, Fs kHz Pass band 0.45 Fs Hz Pass band ripple 0.06 dB Transition band 0.45 Fs 0.5501 Fs Hz Stop band 0.5501 Fs 7.455 Fs kHz Stop band attenuation dB Filter group delay 21/Fs s Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

(1) TAS3218 www.ti.com SLES235 JULY 2008 T A =25C, AVDD 3.3 DVDD 3.3 Fs (audio) kHz, Clock source from XTALI, AES17 filter, second order 30-kHz low-pass filter (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Stereo MUX Input/ADC Channel 1-kHz sine wave input Full scale input voltage dB) 1.15 Vrms Input common mode voltage over recommended operating conditions 1.43 1.5 1.57 V DNR 60-dB full-scale input applied at Line inputs, A-weighted dBA THD N 1-kHz, 4-dB full-scale input dB PSRR kHz, 100 mVpp on AVDD dB Channel separation kHz dB Input resistance 14.6 18.33 k Input capacitance pF DAC Channel/DAC Output 1-kHz sine wave input, load pF Full scale output voltage dB) 0.81 0.9 Vrms Gain error Output common mode over recommended operating conditions 1.43 1.5 1.57 V DNR 60-dB full-scale input applied at Line inputs, A-weighted dBA THD N 1-dBFS input, dB gain dB PSRR kHz, 100 mVpp on AVDD, V GND powered down dB Load capacitance pF Load resistance k Channel separation dB 1-kHz sine wave input, Load external series resistance DAC Channel/ Headphone Output coupling capacitance F Full scale output voltage dB) 0.72 0.9 Vrms DNR 60-dB full-scale input applied at Line inputs, A-weighted dBA THD N 0-dBFS input, 0-dB gain dB PSRR kHz, 100 mVpp on AVDD V GND powered down dB Maximum output power (2) mW Load capacitance 100 pF Load resistance Channel separation dB (1) When the TAS3218 is operated in slave mode, the internal analog clocks for ADC and DAC are derived from external MCLKIN input. In this case, the analog performance will depend on MCLKIN quality (i.e., jitter, phase noise, etc.). (2) 16- series resistor required in L and R headphone outputs for short-circuit protection. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com ELECTRICAL SPECIFICATIONS ANALOG SECTIONS (continued) T A =25C, AVDD 3.3 DVDD 3.3 Fs (audio) kHz, Clock source from XTALI, AES17 filter, second order 30-kHz low-pass filter (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Channel/Headphone Output 1-kHz sine wave input, load pF Full scale output voltage dB) 0.81 0.9 Vrms DNR 60-dB full-scale input applied at Line inputs, A-weighted dBA THD N 0-dBFS input, dB gain dB PSRR kHz, 100 mVpp on AVDD, V GND powered down dB Channel separation dB Analog Mux in Bypass Mode 1-kHz sine wave input, load pF Mux switching noise LINEIN inputs floating mV Full scale input voltage dB) 1.15 Vrms Input common mode voltage 1.43 1.5 1.57 V Load capacitance pF Load resistance k Between Lch and Rch dB Channel separation Between each line input dB Full scale output voltage dB) 0.9 1.1 Vrms Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3-V TTL I OH mA 2.4 V OH High-level output voltage, V 1.8-V LVCMOS (XTL_OUT) I OH 0.55 mA 1.44 3.3-V TTL I OL mA 0.5 V OL Low-level output voltage V 1.8-V LVCMOS (XTL_OUT) I OL 0.75 mA 0.396 High-impedance output I OZ 3.3-V TTL A current, 1.8-V LVCMOS (XTL_IN) I IL Low-level input current (1) V I V IL A 3.3-V TTL 1.8-V LVCMOS (XTL_IN) I IH High-level input current (2) V I V IH A 3.3-V TTL DSP clock 135 MHz, LRCLKIN/LRCLKOUT I DVDD Digital supply current 200 mA KHz, XTALI 24.288 MHz DSP clock 135 MHz, LRCLKIN/LRCLKOUT I AVDD Analog supply current mA KHz, XTALI 24.288 MHz I DVDD Digital supply current RESET LOW 0.1 mA I AVDD Analog supply current RESET LOW mA (1) Value given is for those input pins that connect to an internal pullup resistor as well as an input buffer. For inputs that have a pulldown resistor or no resistor, I IL is (2) Value given is for those input pins that connect to an internal pulldown resistor as well as an input buffer. For inputs that have a pullup resistor or no resistor, I IH is over recommended operating conditions, see Figure PARAMETER MIN TYP MAX UNIT 24.576 f XTALI XTALI frequency (1/ t cyc1 (1) MHz (512 Fs) t cyc1 XTALI cycle time (2) 1/(512 Fs) ns f MCLKIN MCLKIN frequency (1/ t cyc2 256 Fs MHz tw MCLKIN MCLKIN pulse duration (3) 0.4 t cyc2 0.6 t cyc2 ns f MCLKOUT MCLKOUT frequency(1/ t cyc3 256 Fs MHz tr MCLKOUT MCLKOUT rise time C L pF ns tf MCLKOUT MCLKOUT fall time C L pF ns tw MCLKOUT MCLKOUT pulse duration (4) 0.4 t cyc3 0.6 t cyc3 ns XTALI master clock MCLKOUT jitter ps source Delay time, td MIMO MCLKIN rising edge to MCLKOUT rising MCLKOUT MCLKIN ns edge (5) (1) Frequency tolerance is 100 ppm (or better) at 25C. (2) t cyc1 fX TALI (3) t cyc2 f MCLKIN (4) t cyc3 f MCLKOUT (5) When MCLKOUT is derived from MCLKIN, MCLKOUT jitter MCLKIN jitter. MCLKOUT has the same duty cycle as MCLKIN when MCLKOUT MCLKIN. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com See Figure PARAMETER MIN TYP MAX UNIT t pgw(L) Minimum pulse duration, RESET low following DVDD 3.3 V 100 ms control signal parameters over recommended operating conditions (unless otherwise noted), see Figure PARAMETER MIN TYP MAX UNIT tr DMSTATE Time to outputs inactive 100 s tw RESET Pulse duration, RESET active 200 ns tr EMSTATE Time to enable I C ms over recommended operating conditions (unless otherwise noted), see Figure PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f LRCLK Frequency, LRCLKIN (FS) kHz tw SCLKIN Pulse duration, SCLKIN high (1) 0.4 t cyc 0.6 t cyc ns f SCLKIN Frequency, SCLKIN Fs MHz t cyc Cycle time, SCLKIN (1) Fs ns Propagation delay, SCLKIN falling edge to t pd1 ns SDOUT t su1 Setup time, LRCLK to SCLKIN rising edge ns t Hold time, LRCLK from SCLKIN rising edge ns t su2 Setup time, SDIN to SCLKIN rising edge ns t Hold time, SDIN from SCLKIN rising edge ns Propagation delay, SCLKIN falling edge to t pd2 SCLKOUT SCLKIN ns SCLKOUT falling edge (1) t cyc f SCLKIN over recommended operating conditions (unless otherwise noted), see Figure PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f LRCLK Frequency LRCLKOUT kHz tr LRCLK Rise time, LRCLKOUT C L pF ns tf LRCLK Fall time, LRCLKOUT C L pF ns f SCLKOUT Frequency, SCLKOUT (1) Fs MHz tr SCLKOUT Rise time, SCLKOUT C L pF ns tf SCLKOUT Fall time, SCLKOUT C L pF ns Propagation delay, SCLKOUT falling edge to t pd1 ns LRCLKOUT edge Propagation delay, SCLKOUT falling edge to t pd2 ns SDOUT12 t su Setup time, SDIN to SCLKOUT rising edge ns t h Hold time, SDIN from SCLKOUT rising edge ns (1) Typical duty cycle is 50/50. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

I C INTERFACE AND I/O CHARACTERISTICS OF THE SDA AND SCL BUS LINES FOR TAS3218 www.ti.com SLES235 JULY 2008 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Fs Encoded data sampling rate kHz R spdif SPDIF signal bitrate 128 Fs MHz UI Unit interval 1/R spdif ns T LO HI Low/high periods UI UI ns V OH High-level output voltage 3.3-V TTL, I OH mA 2.4 V V OL Low-level output voltage 3.3-V TTL, I OL mA 0.5 V STANDARD- AND FAST-MODE I C BUS DEVICES See Figure PARAMETER STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX f SCL SCL clock frequency 100 400 (1) kHz Hold time (repeated) START condition. After this period, t HD;STA 0.6 s the first clock pulse is generated. t LOW LOW period of the SCL clock 4.7 1.3 s tHI GH HIGH period of the SCL clock 0.6 s t su;STA Set-up time for a repeated START condition 4.7 0.6 s t su;DAT Data set-up time 250 100 (2) ns t r Rise time of both SDA and SCL signals 1000 0.1 C b (3) 300 ns t f Fall time of both SDA and SCL signals 300 0.1 C b (3) 300 ns t su;STO Set-up time for STOP condition 0.6 s t BUF Bus free time between a STOP and START condition 4.7 1.3 s C b Capacitive load for each bus line 400 400 pF Noise margin at the LOW level for each connected device V nL 0.1 V DD 0.1 V DD V (including hysteresis) Noise margin at the HIGH level for each connected device V nH 0.2 V DD 0.2 V DD V (including hysteresis) V hys Hysteresis of Schmitt trigger inputs 0.05 V DD V Pulse width of spikes which must be suppressed by the t SP ns input filter Input current each I/O pin with an input voltage between I i (4) (4) A 0.1 V DD and 0.9 V DD max C i Capacitance for each I/O pin pF Output fall time from V IH min to V IL max with a bus t of 250 (5) 0.1 C b (3) 250 (5) ns capacitance from pF to 400 pF (1) In Master mode the maximum I C clock rate is 375 kHz. (2) A Fast-mode I C bus device can be used in a Standard-mode I C bus system, but the requirement t SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. (3) C b total capacitance of one bus line in pF. (4) I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if V DD is switched off. (5) The maximum t f for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

tdMI–MO RESET D VD 3.3 V tpgw(L) RESET twRESET trEMSTATEtrDMSTATE= ~100 sµ Outputs Inactive Start of Boot Sequence TAS3218 SLES235 JULY 2008 www.ti.com Figure 33. Master Clock Signals Timing Waveforms Figure 34. Reset Timing During Power-On Figure 35. Reset Timing Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

(input) SDOUT1 SDOUT2 SDIN1 SDIN2 tsu2 tsu1 tfLRCLK,trLRCLK tpd1 tpd2 th2 th1 tcyc twSCLKIN SCLKOUT LRCLKOUT SDOUT1 SDOUT2 SDIN1 SDIN2 SDIN3 tsu tpd1, SC tfLRCLK,trLRCLK trSCLKOUT tfSCLKOUT tpd2 th TAS3218 www.ti.com SLES235 JULY 2008 PARAMETER MEASUREMENT INFORMATION (continued) Figure 36. Serial Audio Port Slave Mode Timing Waveforms Figure 37. Serial Audio Port Master Mode Timing Waveforms Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

S SCL tHD;DA T tSU;DA T tLOW tHD;ST A tHD;ST A tSP tBUF tf tf tr tr tHIGH tSU;ST A tSU;STO SDA SSr P Master I C Load RAM Block Formats Master I C Memory Block Header TAS3218 SLES235 JULY 2008 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Figure 38. I C SCL and SDA Timing Waveforms This section describes the format of the data that is stored in an external memory device and downloaded to the TAS3218 via the master I C bus. Table Memory Block Header STARTING DATA BLOCK FORMAT SIZE NOTES BYTE Checksum most significant byte (MSB) byte Checksum of byte through N Checksum least significant bye (LSB) Header ID byte 0x00 byte Must be 0x001F Header ID byte 0x1F 0x00: micro program RAM or termination header 0x01: micro external data RAM Memory to be loaded byte 0x02: DSP program RAM 0x03 DSP coefficient RAM 0x04: DSP data RAM 0x050x0F: reserved 0x00 byte Unused Start memory address MSB If this is a termination header, this byte value is 0000 Start memory address LSB Total number of byte transferred MSB Header size (12) data byte last byte checksum byte. If this is a termination Total number of byte transferred LSB header, this value is 0000 0x00 byte Unused 0x00 byte Unused Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

I C Download Memory Block Structure TAS3218 www.ti.com SLES235 JULY 2008 Table 10. M8051 MCU Program RAM and External Data RAM Block Structure STARTING DATA BLOCK FORMAT SIZE VALUE NOTES BYTE Checksum MSB Checksum of byte byte through N Checksum LSB Header ID byte 0x00 byte Must be 0x001F Header ID byte 0x1F 0x00 or Micro program RAM or Memory to be loaded byte 0x01 micro external data RAM 0x00 byte 0x00 Unused Start memory address MSB If this is a termination byte header, this value is 0000 Start memory address LSB Total number of byte transferred MSB Header (12) data (N) byte checksum (4) Total number of byte transferred LSB 0x00 byte 0x00 Unused 0x00 byte 0x00 Unused Data byte (LSB) Data byte byte microprocessor byte Data byte Data byte (MSB) Data byte (LSB) Data byte byte microprocessor byte Data byte Data byte (MSB) 0x00 0x00 Repeated checksum byte N byte through N +11 Checksum MSB Checksum LSB Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com Table 11. DSP Program RAM Block Structure STARTING DATA BLOCK FORMAT SIZE VALUE NOTES BYTE Checksum MSB byte Checksum of byte through N Checksum LSB Header ID byte 0x00 byte Must be 0x001F Header ID byte 0x1F Micro program RAM or micro external Memory to be loaded byte 0x02 data RAM 0x00 byte 0x00 Unused Start memory address MSB If this is a termination header, this byte value is 0000 Start memory address LSB Total number of byte transferred MSB byte Header (12) data (N) checksum (4) Total number of byte transferred LSB 0x00 byte 0x00 Unused 0x00 byte 0x00 Unused Program byte (LSB) Program word D7D0 Program byte D15D8 Program byte D23D16 Program byte byte D31D24 Program byte D39D32 Program byte D47D40 Program byte (MSB) D55D48 Program byte (LSB) Program byte Program byte Program byte byte Program word Program byte Program byte Program byte (MSB) 0x00 0x00 0x00 Repeated checksum byte N 0x00 byte through N +11 0x00 Checksum MSB Checksum LSB Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 Table 12. DSP Coefficient RAM Block Structure STARTING DATA BLOCK FORMAT SIZE VALUE NOTES BYTE Checksum MSB byte Checksum of byte through N Checksum LSB Header ID byte 0x00 byte Must be 0x001F Header ID byte 0x1F Micro program RAM or micro external Memory to be loaded byte 0x03 data RAM 0x00 byte 0x00 Unused Start memory address MSB If this is a termination header, this byte value is 0000 Start memory address LSB Total number of byte transferred MSB byte Header (12) data (N) checksum (4) Total number of byte transferred LSB 0x00 byte 0x00 Unused 0x00 byte 0x00 Unused Data byte (LSB) Coefficient word D7D0 Data byte D15D8 byte Data byte D23D16 Data byte (MSB) D31D24 Data byte (LSB) Data byte byte Coefficient word Data byte Data byte (MSB) 0x00 0x00 Repeated checksum byte through N N byte +11 Checksum MSB Checksum LSB Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

I C Load RAM Block Formats TAS3218 SLES235 JULY 2008 www.ti.com Table 13. DSP Data RAM Block Structure STARTING DATA BLOCK FORMAT SIZE VALUE NOTES BYTE Checksum MSB byte Checksum of byte through N Checksum LSB Header ID byte 0x00 byte Must be 0x001F Header ID byte 0x1F Micro program RAM or micro external Memory to be loaded byte 0x04 data RAM 0x00 byte 0x00 Unused Start memory address MSB If this is a termination header, this byte value is 0000 Start memory address LSB Total number of byte transferred MSB byte Header (12) data (N) checksum (4) Total number of byte transferred LSB 0x00 byte 0x00 Unused 0x00 byte 0x00 Unused Data byte (LSB) Data word D7D0 Data byte D15D8 Data byte D23D16 byte Data byte (MSB) D31D24 Data byte D39D32 Data byte (MSB) D47D40 Data byte (LSB) Data byte Data byte byte Data word Data byte Data byte Data byte (MSB) 0x00 0x00 Repeated checksum byte through N N byte +11 Checksum MSB Checksum LSB The slave I C bus permits the system controller to load the TAS3218 memories as an alternative to using the master download from an external memory device via the I C master bus. The transfer is performed by writing to two I C registers (0x04 and 0x05). The first register holds the header information, and the second register holds eight bytes of data. Figure shows the I C slave download flow. I C slave download register format are described in Table to Table The I C slave download process is terminated when a termination header with zero length byte count field is received. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

Status I = error IDLE Check num_byte Halt DSP host_dsp = 1 Mem_select NG OK YES YES YES 0 (= termination header) > 0 receive mem_load_ctrl (0x04) receive mem_load_data (0x05) receive mem_load_ctrl (0x04) Invalid Valid Num_byte OK? Initialize Header Information Clear Invalid Memory Select Status pc_source = 1 PCON = 0x01 RAM Switch Num_byte? Status Error? NO NO NO Load Received Data to Specified Memory Calculate Checksum Check Checksum Clear Error Status Load Data End Checksum? Checksum Error? TAS3218 www.ti.com SLES235 JULY 2008 Figure 39. I C Slave Download Flow Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com Table 14. M8051 Microcontroller Program RAM and External Data RAM Block Structure (1) CALC TOTAL REG BYTE DATA BLOCK FORMAT CHECK NUM NOTE SUM BYTE Checksum MSB Checksum LSB Memory to be loaded 0x00 or 0x01 0x00 Control register Start memory address MSB 0x04 Start memory address LSB Total number of byte transferred MSB Total number of byte transferred LSB Datum D7D0 Datum D7D0 Datum D7D0 Data Datum 4D7D0 Register Datum D7D0 0x05 Datum D7D0 Datum D7D0 Datum D7D0 Datum D7D0 Datum D7D0 Datum 11D7D0 Data Datum D7D0 Register Datum D7D0 0x05 Datum D7D0 Datum D7D0 Datum D7D0 Datum N-3 D7D0 If the last data register datum Datum N-2 D7D0 is less than byte, zero data Datum N-1 D7D0 should be filled. Data Datum N D7D0 Register 0x00 0x05 Should be zero 0x00 Checksum MSB End checksum is always located here Checksum LSB (1) Shades cells indicate the values included in the checksum/total number of bytes calculation. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 Table 15. DSP Program RAM Block Structure (1) CALC TOTAL REG BYTE DATA BLOCK FORMAT CHECK NUM NOTE SUM BYTE Checksum MSB Checksum LSB Memory to be loaded 0x02 0x00 Control Start memory address MSB register 0x04 Start memory address LSB Total number of byte transferred MSB Total number of byte transferred LSB 0x00 D55D48 D47D40 Data D39D32 Register Program word D31D24 0x05 D23D16 D15D8 D7D0 0x00 D55D48 D47D40 Data D39D32 Register Program word D31D24 0x05 D23D16 D15D8 D7D0 0x00 0x00 0x00 Should be zero Data 0x00 Register 0x00 0x05 0x00 Checksum MSB End checksum is always located here Checksum LSB (1) Shades cells indicate the values included in the checksum/total number of bytes calculation. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com Table 16. DSP Coefficient RAM Block Structure (1) CALC TOTAL REG BYTE DATA BLOCK FORMAT CHECK NUM NOTE SUM BYTE Checksum MSB Checksum LSB Memory to be loaded 0x03 0x00 Control Start memory address MSB register 0x04 Start memory address LSB Total number of byte transferred MSB Total number of byte transferred LSB D31D24 D23D16 Coefficient word D15D8 Data D7D0 Register D31D24 0x05 D23D16 Coefficient word D15D8 D7D0 D31D24 D23D16 Coefficient word D15D8 Data D7D0 Register D31D24 0x05 D23D16 Coefficient word D15D8 D7D0 D31D24 D23D16 Coefficient word N or zero D15D8 Data D7D0 Register 0x00 0x05 Should be zero 0x00 Checksum MSB End checksum is always located here Checksum LSB (1) Shades cells indicate the values included in the checksum/total number of bytes calculation. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 Table 17. DSP Data Block Structure (1) CALC TOTAL REG BYTE DATA BLOCK FORMAT CHECK NUM NOTE SUM BYTE Checksum MSB Checksum LSB Memory to be loaded 0x04 0x00 Control Start memory address MSB register 0x04 Start memory address LSB Total number of byte transferred MSB Total number of byte transferred LSB 0x00 0x00 Coefficient word D47D40 Data D39D32 Register D31D24 0x05 D23D16 Coefficient word D15D8 D7D0 0x00 0x00 Coefficient word D47D40 Data D39D32 Register D31D24 0x05 D23D16 Coefficient word D15D8 D7D0 0x00 0x00 0x00 Should be zero Data 0x00 Register 0x00 0x05 0x00 Checksum MSB End checksum is always located here Checksum LSB (1) Shades cells indicate the values included in the checksum/total number of bytes calculation. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

I C Register Map TAS3218 SLES235 JULY 2008 www.ti.com Table 18. Termination Header Block Structure (1) CALC TOTAL REG BYTE DATA BLOCK FORMAT CHECK NUM NOTE SUM BYTE Checksum MSB Checksum LSB Memory to be loaded 0x00 Control Start memory address MSB register 0x04 Start memory address LSB Total number of byte transferred MSB Total number of byte transferred LSB (1) Shades cells indicate the values included in the checksum/total number of bytes calculation. The I C register map for ROM advanced code is described in Table Table 19. I C Register Map (1) SUB REGISTER BYTES u(31:24), u(23:16), u(15:8), u(7)M(6:3)N(2:0) 0x00, 0x00, 0x00, 0x00 I C M and N 0x00, 0x00, 0x00, 0x00 0x02 Status Register See Status Register 0x00, 0x00, 0x00, 0x00 0x03 Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 See Load Memory Control and Data 0x00, 0x00, 0x00, 0x00 0x04 I C RAM Load Control Register 0x00, 0x00, 0x00, 0x00 See Load Memory Control and Data 0x00, 0x00, 0x00, 0x00 0x05 I C RAM Load Data Register 0x00, 0x00, 0x00, 0x00 0x06 PEEK/POKE Control See PEEK and POKE 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x07 PEEK/POKE Data See PEEK and POKE 0x00, 0x00, 0x00, 0x00 0x08 Silicon Version ver(31:24), ver(23:16), ver(15:8), ver(7:0) 0x00, 0x00, 0x00, 0x02 0x09 Mute Control See Mute Control 0x00, 0x00, 0x00, 0x00 0x0a Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0b Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0c GPIO Control See GPIO Control 0x00, 0x00, 0x00, 0x00 0x0d Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0e Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0f Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x10 Powerdown Control See Powerdown Control 0x00, 0x00, 0x00, 0x00 0x11 Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x12 A-MUX Control See A-MUX Control 0x00, 0x00, 0x00, 0x00 0x13 Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x14 Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x15 Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 (1) Shades cells indicate common to basic and advanced modes. Unshaded cells indicate advanced mode only. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 Table 19. I C Register Map (continued) SUB REGISTER BYTES 0x00, 0x00, 0x00, 0x00 0x17 Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x18 Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x19 Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x1a Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x1b Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x01 0x1c Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x47, 0xae, 0x00, 0x00 0x1d DC Dither See DC Dither 0x00, 0x00, 0x00, 0x01 0x1e DSP Program Start Address See DSP Program Start Address 0x00, 0x00, 0x00, 0x00 0x1f Reserved u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x20 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x21 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x22 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x23 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x24 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x25 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x26 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x27 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x28 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x29 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2a Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2b Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2c Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2d Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2e Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2f Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x30 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x31 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x32 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x33 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x34 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x35 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x36 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x37 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x38 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x39 Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x3a Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x3b Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x3c Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x3d Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0xfe Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0xff Unused u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

(0x00) TAS3218 SLES235 JULY 2008 www.ti.com The SAP/Clock Setting register is used to configure the device as a Clock Master/Slave as well as specify the desired format of the digital audio ports. This register is four bytes in length. Table 20. SAP/Clock Setting BIT

1. Clock Master/Slave Select (1) CLOCK MASTER/SLAVE SELECT CMS Master Slave (1) Default values are shown in italics. Table 22. Digital Audio Port Normalization (1) DIGITAL AUDIO PORT NORMALIZATION ON Enable Disable (1) Default values are shown in italics. Bits (IW1 and IW0) define the data word size for the input SAP. Bits 1312 (OW1 and OW0) define the data word size for the output SAP. Table 23. Audio Data Word Size (1) DIGITAL AUDIO I/O WORD SIZE IW1/OW1 IW0/OW0 bit bit bit (1) Default values are shown in italics. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

(0x02) TAS3218 www.ti.com SLES235 JULY 2008 Table 24. Audio Data Format (1) DIGITAL AUDIO I/O FORMAT IM1/OM1 IM0/OM0 Left-justified Right-justified I S (1) Default values are shown in italics. Status register provide memory load information. When a memory load error for a particular memory occurs, the memory load error bit for that memory is set to When a memory load is successful for a particular memory the memory load error bit for that memory is set to Host needs to check this load status after memory load. Host can clear all load error status by writing to bits D40D32 of this register. Table 25. SAP/Clock Setting BIT x x x x x x x x Micro program memory load error x x x x x x x x Micro external memory load error x x x x x x x x DAP program memory load error x x x x x x x x DAP coefficient memory load error x x x x x x x x DAP data memory load error x x x x x x x x DAP upper data memory load error DAP upper coefficient memory load x x x x x x x x error x x x x x x x x Invalid memory select x x x x x x x x End of load header error No EEPROM No error BIT Reserved BIT Reserved BIT Reserved BIT Reserved ABSY Analog busy flag Reserved Reserved Reserved Reserved BUSE I C bus error Reserved Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

(0x04 and 0x05) TAS3218 SLES235 JULY 2008 www.ti.com Bits 4032 define the memory load error status on EEPROM download and slave download. Table 26. Analog Busy (1) ANALOG BUSY FLAG ABSY Analog is busy Analog not busy (1) Default values are shown in italics. Analog control sequence takes time (maximum around 500 ms for headphone power up). This busy flag indicate whether analog control sequence is running or not. Table 27. I C Bus Error (1) I C BUS ERROR BUSE Bus error No bus error (1) Default values are shown in italics. If I C bus error occurs, this flag will be set. Only host uC can clear this flag by writing to this bit. I C bus error status is read from ESFR (0xC5, bit 6), and is cleared by ESFR (0xC7, bit 6). The I C Memory Load port permits the system controller to load the TAS3218 memories as an alternative to having the TAS3218 load its memory from an external EEPROM. The transfer is performed by writing to two I C registers. The first register is a eight byte register than holds the check sum, the memory to be written, the starting address, the number of data bytes to be transferred. The second register holds eight bytes of data. The memory load operation starts with the first register being set. Then the data is written into the second register using the format shown. After the last data byte is written into the second register, an additional two bytes are written which constrain the two byte checksum. At that point, the transfer is complete and status of the operation is reported in the status register. NOTE: Once the micro program memory has been loaded, further updates to this memory are inhibited until the device is RESET. When the first I C slave down load register is written by the system controller the TAS3218 will update the status register by setting a error bit to indicate an error for the memory type that is being loaded. This error bit is reset when the operation complete and a valid checksum has been received. For example when the Micro program memory is being loaded, the TAS3218 will set a Micro program memory error indication in the status register at the start of the sequence. When the last byte of the micro program memory and checksum is received, the TAS3218 will clear the micro program memory error indication. This enables the TAS3218 to preserve any error status indications that occur as a result of incomplete transfers of data/ checksum error during a series of data and program memory load operations. The checksum is always contained in the last two bytes of the data block. The I C slave download is terminated when a termination header with a zero length byte count filed is received. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

(0x06 and 0x07) TAS3218 www.ti.com SLES235 JULY 2008 Table 28. Load Memory Control Register (0x04) BYTE DATA BLOCK FORMAT SIZE NOTES Checksum code bytes Checksum of bytes through N+8, If this is a termination header, this value is 00. Memory to be loaded byte Micro Program memory Micro External Data memory DSP Program memory DSP Coefficient memory DSP Data Memory 515: Reserved Unused byte Reserved Starting TAS3218 bytes If this is a termination header, this value is Memory address Number of data bytes to be transferred bytes If this is a termination header, this value is Table 29. Load Memory Data Register (0x05) BYTE 8-BIT DATA 24-BIT DATA 28-BIT DATA 48-BIT DATA 55-BIT DATA Datum D7D0 XXXX D27D24 Datum D7D0 D23D16 D23D16 X D54D48 Datum D7D0 D15D8 D15D8 D47D40 D47D40 Datum D7D0 D7D0 D7D0 D39D32 D39D32 Datum D7D0 XXXX D27D24 D31D24 D31D24 Datum D7D0 D23D16 D23D16 D23D16 D23D16 Datum D7D0 D15D8 D15D8 D15D8 D15D8 Datum D7D0 D7D0 D7D0 D7D0 D7D0 Registers 0x06 Table and 0x07 Table allow the user to access the internal resources of TAS3218. Figure shows the I C transaction for PEEK and POKE register. Table 30. Memory Select and Address (0x06) BIT 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

+ W ACK Sub address (0x07) ACK D63–D56 ACK D55–D48 ACK D47–D40 ACK D39–D32 ACK Poke (Write) D31–D24 ACK D23–D16 ACK D15–D8 ACK D7–D0 NAK P Peek (Read) S Slave address + W ACK D63–D56 ACK D55–D48 ACK D47–D40 ACK D39–D32 ACK S Slave address + W ACK Sub address (0x07) ACK D31–D24 ACK D23–D16 ACK D15–D8 ACK D7–D0 NAK P P S Slave address + W ACK Sub address (0x06) ACK 00000000 ACK memory section ACK address (MS Byte) ACK address (LS Byte) ACK P Memory Select and Address TAS3218 SLES235 JULY 2008 www.ti.com Table 31. Data Register (0x07) BIT

1. I C Transaction for PEEK and POKE Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

(0x0c) TAS3218 www.ti.com SLES235 JULY 2008 Table 32. Mute Control BI T Unused BI T Unused AMX3 AMX3 AMUX03 (LINEOUT3) BI T AMX2 AMX2 Analog MUX out (LINEOUT2) AMX1 AMX0 Analog MUX out (LINEOUT1) SD2 SD2 SDOUT2/SPDIFOUT SD1 SD1 SDOUT1 BI T DAC1 DAC1 DAC1 (DACOUT1) DAC2 DAC2 DAC2 (DACOUT2) DAC3 DAC3 DAC3 (HPOUT) DIT DIT DIT (BiPhase) Table 33. MUTE (1) MUTE MUTE[1] MUTE[0] HW Mute Control Force mute off x Force mute on (1) Default values are shown in italics. Table 34. GPIO Control (0x0c) BIT x x x x x x x x GPIOMICROCOUNT MSB BIT x x x x x x x x GPIOMICROCOUNT LSB BIT y y y y y y y y GPIO_Sampling_Interval GPIOMICROCOUNT sets the number of micro clock cycles for Timer interrupt. In Timer interrupt service routine, watchdog timer is reset if it is enabled. The default value for this counter is 0x5820 which correspond to a period 1.25 ms. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

(0x10) TAS3218 SLES235 JULY 2008 www.ti.com Table 35. Watchdog Timer Enable (1) WATCHDOG TIMER WDE Enable Disable (1) Default values are shown in italics. Table 36. GPIO Direction (1) GPIOx DIRECTION DIRx Output Input (1) Default values are shown in italics. Table 37. Powerdown Control BIT (HPOUT) DAC2 DAC2 (DACOUT2) DAC1 DAC1 (DACOUT1) ADC AMUX AAF ADC AMX3 AMUX3 Line Amp AMX2 AMUX2 Line Amp AMX1 AMUX1 LineAmp1 Table 38. Powerdown (1) POWERDOWN PD Powerdown and disable Powerup and enable (1) Default values are shown in italics. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

(0x12) TAS3218 www.ti.com SLES235 JULY 2008 Table 39. A-MUX Control (0x12) BIT x x x x Reserved x x x x Reserved x x x x Reserved x x x x Reserved x x x x DAC x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select MUTE BIT x x x x Reserved x x x x Reserved x x x x Reserved x x x x Reserved x x x x Reserved x x x x AMUX2 IN x x x x AMUX2 IN x x x x AMUX2 IN x x x x AMUX2 IN x x x x AMUX2 IN x x x x AMUX2 IN x x x x AMUX2 IN x x x x AMUX2 IN x x x x AMUX2 IN x x x x AMUX2 IN MUTE BIT x x x x Reserved x x x x Reserved x x x x Reserved x x x x Reserved x x x x Reserved x x x x AMUX3 IN x x x x AMUX3 IN x x x x AMUX3 IN x x x x AMUX3 IN x x x x AMUX3 IN x x x x AMUX3 IN Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

www.ti.com Table 39. A-MUX Control (0x12) (continued) BIT x x x x AMUX3 IN x x x x AMUX3 IN x x x x AMUX3 IN x x x x AMUX3 IN MUTE BIT x x x x Reserved x x x x Reserved x x x x Reserved x x x x Reserved x x x x DAC x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select x x x x Analog MUX line select MUTE Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

(0x16) TAS3218 www.ti.com SLES235 JULY 2008 Table 40. PDIF Control (0x16) BIT SRC# SRC# SRC# SRC# Source channel number b19 b18 b17 b16 BIT Cat Cat Cat Cat Cat Cat Cat Category code b10 b11 b12 b13 b14 L Generation status BIT Unused MUX1 MUX0 SPDIF MUX Table 41. Copyright Flag (1) COPYRIGHT FLAG CP Copy prohibited Copy permitted (1) Default values are shown in italics. Table 42. Pre-Emphasis Flag (1) PRE-EMPHASIS FLAG EMP No pre-emphasis s pre-emphasis (1) Default values are shown in italics. Table 43. Sample Word Length SAMPLE WORD LENGTH WLx 24-bit sample word length Table 44. Sampling Rate SAMPLING RATE b24 b25 kHz Table 45. Validity Flag (1) VALIDITY FLAG Vx Valid Not valid (1) Default values are shown in italics. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

(0x1d) DSP Program Start Address (0x1e) TAS3218 SLES235 JULY 2008 www.ti.com Table 46. Channel Source Number CHANNEL SOURCE NUMBER b19 b18 b17 b16 Channel Table 47. Category Code CATEGORY CODE b10 b11 b12 b13 b14 Digital sound processor Table 48. Generation Status GENERATION STATUS Vx Gen or higher Original Table 49. SDOUT/SPDIF MUX (1) SDOUT/SPDIF MUX MUX1 MUX2 SDOUT2 SPDIF Tx SPDIF In (1) Default values are shown in italics. Table 50. DC Dither (0x1d) BIT

1. DC Dither Enable (1) DC DITHER ENABLE ON Disable Enable (1) Default values are shown in italics. The DSP instruction execution loops each Fs cycle. At the beginning of the Fs cycle, the DSP instruction pointer is set to the starting address specified in the LSBs. The maximum address is the end address of DSP instruction address 3327. Table 52. DSP Program Start Address (0x1e) BIT

2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

www.ti.com SLES235 JULY 2008 Table 52. DSP Program Start Address (0x1e) (continued) BIT x x x x Starting address MSB BIT x x x x x x x x Starting address LSB Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3218

AVDD_HP SDIN2 DAC□1□L Line□Out□1□R Line□Out□1□L SDIN1 AVDD_REF TAS3218PZP RESERVED5 LINEIN6L 57 VR_ANA DVSS11 RESERVED6 MCLKOUT8 LRCLKOUT9 SCLKOUT10 SDOUT111 SDOUT2/SPDIF_OUT12 DVDD213 VR_DIG114 DVSS215 SPDIF_IN16 RESERVED17 RESERVED18 RESERVED20 SCLKIN25 DVDD3 I2C_SDA2 I2C_SCL2 I2C_SCL1 CS GPIO2 /MUTE /RESET DVDD4 DVSS5 VR_DIG2 AVSS_ESD LINEIN3L LINEIN3R LINEIN4R 52 AVDD_LI 53 LINEIN5L 54 AVDD_LI 65 LINEIN9L 66 LINEIN9R 67 AVSS_LI 68 LINEIN10R 70 AVDD_ADC 71 AVSS_ADC/REF 72 BG_REF 74 AVDD_REF LINEOUT3L LINEOUT3R LINEOUT2L XTAL_IN XTAL_OUT AVSS_LI AVDD_LI LINEIN2R LINEOUT1R SDIN222 SDIN123 DVSS3 AVDD_OSC RESERVED3 RESERVED4 LINEIN5R 55 AVSS_LI 56 LINEIN6R 58 AVDD_LI 59 LINEIN7L 60 LINEIN7R 61 LINEIN8L 63 LINEIN8R 64 SDIN321 I2C_SDA1 LINEIN1R AVSS_LI 62 LINEIN10L 69 V1P5_REF 75DACOUT1L DVDD1 100 MCLKIN DVSS4 LINEIN4L 51 AVSS_DAC AVSS_LO LINEOUT1L DACOUT1R DACOUT2L DACOUT2R AVDD_DAC AVDD_HP HPOUTL AVSS_HP HPOUTR AVDD_HP AVSS_ESD /VREG_EN2 LINEOUT2R BIAS_REF 73 RESERVED7 RESERVED19 LRCLKIN24 GPIO1 LINEIN1L LINEIN2L Power_P AD 101 33K 1 2 AVDD_ADC L/RCLK_IN AVDD_LI SCLK_IN 4.7uF AVDD_LI AVDD_LI GPIO1 DVDD1 4.7uF 2 0.1□uF2 33K 1 2 4.7uF GPIO2 Line□In□1□R 24k1 2 DVDD Line□In□1□L DVDD1 47uF12 DVDD2 4.7uF 10uF 2 0.1□uF2 0.1□uF2 24.576MHz 0.1□uF2 47uF 1uF21 0.1□uF2 0.1□uF2 DVDD 4.7uF DVDD2 0.1□uF2 22uF 1 2 4.7uF DVDD 22uF 1 2 DVDD3 AVDD_DAC AVDD 0.1□uF2 10K 1 2 DVDD 4.7uF DVDD4 1.00M Line□Out□2□R Line□Out□2□L 22uF 1 2 22uF 1 2 33K 1 2 10K 1 2 4.7uF Chip_Select 33K 1 2 Line□In□2□R 4.7uF 10K 1 2 4.7uF Line□In□2□L DVDD3 22uF 1 2 22uF 1 2 10K 1 2 10K 1 2 AVDD_HP SPDIF AVDD_HP DVDD4 33K 1 2 4.7uF 33K 1 2 4.7uF Line□In□4□R Line□In□4□L 33K 1 2 4.7uF

21 Line□In□3□R

4.7uF 1uF21 Line□In□3□L 10pF 2 1 AVDD_ADC 10pF 2 1 nMUTE SDOUT2/SPDIFOUT 4.7uF nRESET 33K 1 2 10K 1 2 4.7uF Line□In□5□R 33K 1 2 Line□In□5□L MCLK_IN 22uF 1 2 22uF 1 2 10K 1 2 10K 1 2 SDOUT1 4.7uF 4.7uF 33K 1 2 4.7uF 33K 1 2 Line□In□6□R Line□In□6□L 4.7uF 33K 1 2 4.7uF 33K 1 2 Line□In□7□R Line□In□7□L Headphone□R Headphone□L SCLK_OUT AVDD_REF 4.7uF AVDD_LI 33K 1 2 4.7uF Line□In□8□R 33K 1 2 Line□In□8□L 4.7uF 33K 1 2 AVDD_HP 4.7uF 33K 1 2 Line□In□9□R Line□In□9□L L/RCLK_OUT AVDD_LI 4.7uF 33K 1 2 4.7uF 33K 1 2 Line□In□10□R AVDD_LI Line□In□10□L MCLK_OUT MASTER_SDA AVDD_LI MASTER_SCL 10K 1 2 SLAVE_SDA SDIN3 10K 1 2 SLAVE_SCL 0.1□uF2 0.1□uF2 4.7uF AVDD_HP AVDD AVDD_DAC DAC□1□R 0.1□uF2 DAC□2□R DAC□2□□L 0.1□uF2 4.7uF Line□Out□3□R Line□Out□3□L 22uF 1 2 22uF 1 2 10K 1 2 10K 1 2 TAS3218 SLES235 JULY 2008 www.ti.com Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TAS3218IPZP ACTIVE HTQFP PZP 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS3218IPZPR ACTIVE HTQFP PZP 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS3218PZPR ACTIVE HTQFP PZP 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 Addendum-Page 1

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