TAS5012_06 TI | Alldatasheet

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Technical content

SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001 TRUE DIGITAL AUDIO AMPLIFIER TAS5012 DIGITAL AUDIO PWM PROCESSOR 1www.ti.com

FEATURES

/C0068TAS5012 + TAS5110 TDAA System – High Quality Digital Audio Amplification /C0068102-dB Dynamic Range (TAS5012 Device) /C0068THD+N < 0.06% /C0068Power Efficiency Is 90% Into 8-Ω Load /C006816-, 20-, or 24-Bit Input Data /C006832-kHz, 44.1-kHz, 48-kHz, 88.2-kHz, 96-kHz, 176.4-kHz, 192-kHz Sampling Rates /C0068Economical 48-Pin TQFP Package /C0068Lower-Jitter Internal PLL /C00683.3-V Power Supply /C0068Mute /C0068Clicks and Pops Reduction (Patent Pending)

APPLICATIONS

/C0068DVD-Audio /C0068Home Theater /C0068Car Audio Amplifiers and Head Units /C0068Internet Music Appliance /C0068Mini/Micro Component Systems

DESCRIPTION

True digital audio amplifier (TDAA) is a new paradigm in digital audio. One TDAA system consists of the TAS5012 PCM-PWM modulator device + TAS5110 PWM power output device. This system accepts a serial PCM digital audio stream and converts it to a 3.3-V PWM audio stream (TAS5012). The TAS5110 device then provides a large-signal PWM output. This digital PWM signal is then demodulated providing power output for driving loudspeakers. This patented technology provides low-cost, high-quality, high-efficiency digital audio applicable to many audio systems developed for the digital age. The TAS5012 is an innovative, cost-effective, high-performance 24-bit stereo PCM-PWM modulator based on Equibit technology. It has a wide variety of serial input options including right-justified (16, 20, or 24 bits), IIS (16, 20, or 24 bits), left-justified (16 bits), or DSP (16 bits) data formats. It is fully compatible with AES standard sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. The TAS5012 also provides a de-emphasis function for 44.1-kHz and 48-kHz sampling rates. TAS5012 TAS5110 Left

  • Volume
  • EQ
  • DRC
  • Bass
  • Treble
  • Serial Audio Input Port
  • Internal PLL
  • Equibit Modulator
  • Up to 192-kHz Input Sampling Rate
  • TAS3001
  • DSP
  • S/PDIF
  • 1394 Digital Audio
  • H-Bridges Power Devices
  • Improved Performance From TAS5100 TAS5110 Right L-C Filter L-C Filter Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2001, Texas Instruments Incorporated Equibit is a trademark of Toccata Technology ApS, Denmark. All other trademarks are the property of their respective owners.

SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001 2 www.ti.com terminal assignments 14 15 DVDD3_L PWM_AP_L PWM_AM_L PWM_BM_L PWM_BP_L DVDD2 DVSS2 PWM_AP_R PWM_AM_R PWM_BM_R PWM_BP_R DVDD3_R MCLK_IN AVDD2 PLL_FLT_OUT PLL_FLT_RET AVSS2 NC RESET PDN VALID_R M_S NC DVDD1 17 18 19 20 47 46 45 44 4348 42 40 39 3841 21 22 23 24 48-Pin LQFP PACKAGE (TOP VIEW) NC – No internal connection AVDD1 XTL_IN XTL_OUT OSC_CAP AVSS1 DEM_EN DEM_SEL FTEST STEST DBSPD MUTE DVSS3_L DVSS1 DVDD1 DVSS1 MCLK_OUT SCLK LRCLK SDIN MOD2 MOD1 MOD0 VALID_L DVSS3_R references /C0068True Digital Audio Amplifier TAS5100 PWM Power Output Stage data sheet – Texas Instruments literature number SLLS419 /C0068Design Considerations for TAS5000/TAS5110 True Digital Audio Power Amplifiers data sheet – Texas Instruments literature number SLAA117 /C0068Digital Audio Measurements application note – Texas Instruments literature number SLAA114 /C0068PowerPAD  Thermally Enhanced Package application note – Texas Instruments literature number SLMA002 PowerPAD is a trademark of Texas Instruments.

SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001 3www.ti.com functional block diagram PLL/Clock Generator OSC Serial Audio Port Digital Interpolation Filter Equibit Modulator Buffer Audio Port Configuration Control Section LRCLK SCLK SDIN PWM_AP_L PWM_AM_L PLL_FLT_RET PLL_FLT_OUT MCLK_IN MCLK_OUT XTL_IN XTL_OUT OSC_CAP MOD0 MOD1 MOD2 DEM_SEL DEM_EN MUTE RESET PDN FTEST STEST DBSPD M_S DVDD1 DVSS1 DVDD2 DVSS2 DVDD3_L DVSS3_L DVDD3_R DVSS3_R AVDD1 AVSS1 AVDD2 AVSS2 PWM_AP_R PWM_AM_R VALID_R VALID_L PWM_BP_L PWM_BM_L PWM_BP_R PWM_BM_R

ordering information

0°C to 70°C TAS5012PFB –40°C to 85°C TAS5012IPFB NOTE: These packages are available taped and reeled. Add R suffix to ordering number (e.g., TAS5012PFBR).

SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001 4 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AVDD1 48 I Analog supply for oscillator AVDD2 2 I Analog supply for PLL AVSS1 44 I Analog ground for oscillator AVSS2 5 I Analog ground for PLL DBSPD 39 I Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high DEM_EN 43 I De-emphasis enable, active high DEM_SEL 42 I De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz) DVDD1 12, 14 I Digital voltage supply for logic DVDD2 31 I Digital voltage supply for PWM reclocking DVDD3_L 36 I Digital voltage supply for PWM output (left) DVDD3_R 25 I Digital voltage supply for PWM output (right) DVSS1 13, 15 I Digital ground for logic DVSS2 30 I Digital ground for PWM reclocking DVSS3_L 37 I Digital ground for PWM output (left) DVSS3_R 24 I Digital ground for PWM output (right) FTEST 41 I Tied to DVSS1 for normal operation LRCLK 18 I/O Left/right clock (input when M_S = 0; output when M_S = 1) MCLK_IN 1 I MCLK input MCLK_OUT 16 O Buffered system clock output if M_S = 1; otherwise set to 0 MOD0 22 I Serial interface selection pin, bit 0 MOD1 21 I Serial interface selection pin, bit 1 MOD2 20 I Serial interface selection pin, bit 2 (MSB) M_S 10 I Master/slave, master=1, slave=0 MUTE 38 I Muted signal = 0, normal mode = 1 NC 6, 11 No connection OSC_CAP 45 I Oscillator cap return PDN 8 I Power down, active low PLL_FLT_OUT 3 O Output terminal for external PLL filter PLL_FLT_RET 4 I Return for external PLL filter PWM_AM_L 34 O PWM left output A (differential –) PWM_AM_R 28 O PWM right output A (differential –) PWM_AP_L 35 O PWM left output A (differential +) PWM_AP_R 29 O PWM right output A (differential +) PWM_BM_L 33 O PWM left output B (differential –) PWM_BM_R 27 O PWM right output B (differential –) PWM_BP_L 32 O PWM left output B (differential +) PWM_BP_R 26 O PWM right output B (differential +) RESET 7 I Reset (active low) SCLK 17 I/O Shift clock (input when M_S = 0, output when M_S = 1) SDIN 19 I Stereo serial audio data input STEST 40 I Tied to DVSS1 for normal operation VALID_L 23 O PWM left outputs valid (active high) VALID_R 9 O PWM right outputs valid (active high) XTL_IN 47 I Crystal or clock input (MCLK input) XTL_OUT 46 O Crystal output (not for external usage). NC when XTL_IN is MCLK input

88.2 kHz, 96 kHz, 176.4 kHz, or 192 kHz) stereo. See the serial interface formats section. (Fs = 176.4 kHz or 192 kHz), the device works in slave mode only with MCLK_IN = 128 Fs. modes. Table 1 explains the proper clock selection. Table 1. Oscillator, External Clock, and PLL Functions † Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN. ‡ MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided. ¶ SCLK and LRCLK are outputs when M_S = 1, inputs when M_S = 0. # MCLK_OUT is driven low when M_S = 0. ||Quad speed mode is detected automatically. when DBSPD = 0. low. Note that VALID_L and VALID_R can go low for other conditions as well. See the error status reporting section.

Figure 3. Reset Timing asynchronous operation. To place the device in total power-down mode, both RESET and PDN must be held low. pin goes low. Otherwise, the device may drain additional supply current. Figure 4. Power-Down Timing both sides of the differential PWM outputs have a 50% duty cycle (see Figure 5 for mute timing). Table 2. Mute Description

1 DATA DATA Normal operation

Table 3. De-Emphasis Selection 1 0 Forbidden state. Do not use. justified, and DSP frame. Table 4 indicates how these options are selected using the MOD0, MOD1, and MOD2 pins. Table 4. Hardware Selection of Serial Audio Modes interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with binary 0s.

SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001 12 www.ti.com absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: DVDD1, DVDD2, DVDD3_L, DVDD3_R. recommended operating conditions, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ± 10%, AVDD1 = AVDD2 = 3.3 V ± 10%, Fs = 44.1 kHz MIN TYP MAX UNIT Supply voltage Digital DVDDX ‡ 3 3.3 3.6 V Supply current Digital Operating 22 mA Supply current Digital Power down§ 10 20 µA Power dissipation Digital Operating 59.4 mW Power dissipation Digital Power down§ 6.6 72 µW Supply voltage Analog AVDDX ¶ 3 3.3 3.6 V Supply current Analog Operating 8 mA Supply current Analog Power down§ 10 100 µA Power dissipation Analog Operating 26.4 mW Power dissipation Analog Power down§ 33 360 µW ‡ DVDD1, DVDD2, DVDD3_L, DVDD3_R § If the clocks are turned off ¶ AVDD1, AVDD2 electrical characteristics, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ± 10%, AVDD1 = AVDD2 = 3.3 V ± 10% static digital specifications MIN MAX UNIT VIH High-level input voltage 2 DVDD1 V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage, (IO = –1 mA) 2.4 V VOL Low-level output voltage, (IO = 4 mA) 0.4 V Input leakage current –10 10 µA digital interpolation filter and PWM modulator, Fs = 44.1 kHz MIN TYP MAX UNIT Pass band 0 20 kHz Pass-band ripple ±0.012 dB Stop band 24.1 kHz Stop-band attenuation (24.1 kHz to 152.3 kHz) 50 dB Group delay 700 µS PWM modulation index (gain) 0.93

SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001 13www.ti.com TAS5012/TAS5110 system performance measured at the speaker terminals See application note SLAA117. switching characteristics, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = AVDD1 = AVDD2 = 10% 3.3 V ± 10% serial audio ports slave mode PARAMETER MIN TYP MAX UNIT f(SCLK) SCLK frequency 12.288 MHz tsu(SDIN) SDIN setup time before SCLK rising edge 20 ns th(SDIN) SDIN hold time from SCLK rising edge 10 ns f(LRCLK) LRCLK frequency 32 48 192 kHz MCLK duty cycle 50% SCLK duty cycle 50% LRCLK duty cycle 50% tsu(LRCLK) LRCLK edge setup before SCLK rising edge 20 ns serial audio ports master mode, load conditions = 50 pF PARAMETER MIN TYP MAX UNIT t(MSD) MCLK to SCLK 0 5 ns t(MLRD) MLCK to LRCLK 0 5 ns DSP serial interface mode PARAMETER MIN TYP MAX UNIT f(SCLK) SCLK frequency 12.288 MHz tw(FSHIGH) Pulse duration, sync 1/(64×Fs) ns tsu(SDIN), tsu(LRCLK) SDIN and LRCLK setup time before SCLK falling edge 20 ns th(SDIN), th(LRCLK) SDIN and LRCLK hold time from SCLK falling edge 10 ns SCLK duty cycle 50%

64 SCLKs

Figure 15. DSP Serial Port Expanded Timing Figure 16. DSP Absolute Timing Requirement

SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001 16 www.ti.com

APPLICATION INFORMATION

PLL_FLT_RET PLL_FLT_OUT DEM_SEL DEM_EN DBSPD SDIN LRCLK SCLK MCLK_IN MOD0 MOD1 MOD2 M_S TAS5110 H-BridgePWM_AP_L PWM_AM_L RESET System Controller MUTE PDN

3.3 V DIG

XTL_IN C 2† R 1† C 1† RESET FTEST TAS5012 VALID_L TAS5110 H-BridgePWM_AP_R PWM_AM_R RESETVALID_R STEST PWM_BP_L PWM_BM_L PWM_BP_R PWM_BM_R † See application note SLAA117 for values.

SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001 17www.ti.com MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–/C02577° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TAS5012IPFB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS5012IPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS5012PFB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS5012PFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS5012PFBR ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS5012PFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 Addendum-Page 1

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