TAS2521IRGER

TAS2521 TAOS | Alldatasheet

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Technical content

www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 DigitalInputClass-DSpeakerAmplifierwithEmbeddedminiDSPandmonoheadphone amplifier Check forSamples: TAS2521

1 INTRODUCTION

1.1 Features

• DigitalInputMono Speaker Amp 1.2 Applications
• Instruction-ProgrammableEmbedded miniDSP • PortableAudio Devices• Supports 8-kHz to192-kHz Sample Rates
• White goods• Mono Class-DBTL Speaker Driver(2W Into
• PortableNavigationDevices4 Ω or 1.7W Into8 Ω)
• Mono Headphone Driver

1.3 Description• Two Single-EndedInputsWith Output Mixing

and LevelControl The TAS2521 is a low power digitalinputspeaker• Embedded Power-on-Reset amp withsupportfor24-bitdigitalI2S data mono• IntegratedLDO playback.• Built-inDigitalAudio ProcessingBlocks With In additionto drivinga speaker amp upto 4-Ω, theUser-Programmable Biquad Filters devicealsofeaturesa mono headphone driverand a• IntegratedPLL Used forProgrammable Digital fullyprogrammable miniDSP forsignalprocessing.Audio Processor The digitalaudio data formatis programmable to• I2S,Left-Justified,Right-Justified,DSP, and work with popular audio standard protocols(I2S,TDM Audio Interfaces left/right-justified)in master,slave,DSP and TDM• I2C and SPI controlwithauto-increment modes. The fullyprogrammableminiDSP can support• FullPower-Down Control severalfunctionssuch equalizationforaudio,multi-• Power Supplies:

• 24-PinQFN Package (4mm × 4mm) I2C ™ serialbus or SPI bus.The deviceincludesan on-boardLDO thatrunsoffthespeakerpower supply tohandleallinternaldeviceanalogand digitalpower needs. The includedPOR as power-on-resetcircuit reliablyresetsthe deviceintoitsdefaultstateso no externalresetisrequiredatnormalusage;however, the devicedoes have a resetpinformore complex system initializationneeds.The devicealsoincludes two analog inputsformixing and muxing in both speakerand headphone analogpaths. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2013,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.

SPI_SEL SCLK SPKVDD AVDD LDO_SEL DAC Signal Proc. Data Interface SPI/I2C Control Block PLL Interrupt Control Primary I2S Interface Pin Muxing / Clock Routing LDO POR Supplies Mono 6 'DAC DVDD IOVDD Secondary I2S Interface Dig Vol miniDSP 6 dB to +24 dB (6 dB steps) -6 dB to +29 dB and Mute (1 dB steps) 0 dB to -78 dB and Mute (Min 0.5 dB steps) 0 dB to -78 dB and Mute (Min 0.5 dB steps) 0 dB to -78 dB and Mute (Min 0.5 dB steps) TAS2521 SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. Figure1-1.SimplifiedBlock Diagram NOTE Thisdatamanual isdesignedusingPDF document-viewingfeaturesthatallowquickaccess toinformation.For example,performinga globalsearchon "page 0 /register27" produces allreferencestothispage and registerina list.Thismakes iseasy totraversethelistand findallinformationrelatedtoa page and register.Note thatthesearchstringmust be ofthe indicatedformat.Also,thisdocument includesdocument hyperlinksto allowthe user to quicklyfinda document reference.To come back to the originalpage, clickthe green left arrownearthePDF page number atthebottomofthefile.The hot-keyforthisfunctionisalt- leftarrow on the keyboard.Another way to findinformationquicklyis to use the PDF bookmarks.

2 INTRODUCTION Copyright© 2013,Texas InstrumentsIncorporated

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SPI_SEL LDO_SEL AINL A VSS HPOUT SPKM SPKVSS A VDD WCLK SPKVDD SPKP BCLK MCLK MISO SDA/MOSI DIN GPIO/DOUT IOVDD SCL/SSZ DVSS SCLK DVDD 23 2124 22 20 19 1 11098 127 TAS2521 www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013

2 PACKAGE AND SIGNAL DESCRIPTIONS

2.1 Package/OrderingInformation

OPERATINGPACKAGE TRANSPORT MEDIA,PRODUCT PACKAGE TEMPERATURE ORDERING NUMBERDESIGNATOR QUANTITYRANGE TAS2521IRGET Tape and reel,250 TAS2521 QFN-24 RGE –40°C to85°C TAS2521IRGER Tape and reel,3000

2.2 Device Information

(TOP VIEW) Table2-1.RGE PIN FUNCTIONS PIN I/O(1) DESCRIPTION NAME NO. SPI_SEL 1 I Selectsbetween SPI and I2C digitalinterfacemodes; (1= SPI mode) (0= I2C mode) RST 2 I Resetforlogic,statemachines,and digitalfilters;assertedLOW. AINL 3 I Analogsingle-endedlineleftinput AINR 4 I Analogsingle-endedlinerightinput HPOUT 5 O Headphone and LineoutDriverOutput AVSS 6 GND AnalogGround,0V AVDD 7 PWR AnalogCore SupplyVoltage,1.5V-1.95V,tiedinternallytotheLDO output LDO_SEL 8 I SelectPinforLDO; tiestoeitherSPKVDD orSPKVSS SPKM 9 O Class-Dspeakerdriverinvertingoutput SPKVDD 10 PWR Class-Dspeakerdriverpower supply SPKVSS 11 PWR Class-Dspeakerdriverpower supplygroundsupply SPKP 12 O Class-Dspeakerdrivernon-invertingoutput DIN 13 I AudioSerialData Bus InputData WCLK 14 I/O AudioSerialData Bus Word Clock BCLK 15 I/O AudioSerialData Bus BitClock MCLK 16 I MasterCLK Input/ReferenceCLK forCLK Multiplier-PLL (On startupPLLCLK = CLKIN) (1) I= Input,O = Output,GND = Ground,PWR = Power,Z = HighImpedance Copyright© 2013,Texas InstrumentsIncorporated PACKAGE AND SIGNAL DESCRIPTIONS 3 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com Table2-1.RGE PIN FUNCTIONS (continued) PIN I/O(1) DESCRIPTION NAME NO. MISO 17 O SPI SerialData Output GPIO/DOUT 18 I/O/Z GPIO /AudioSerialBus Output SCL/SSZ 19 I EitherI2C InputSerialClockorSPI ChipSelectSignaldependingon SPI_SEL state SDA/MOSI 20 I EitherI2C SerialData InputorSPI SerialData Inputdependingon SPI_SEL state. SCLK 21 I SerialclockforSPI interface IOVDD 22 PWR I/OPower Supply,1.1V-3.6V DVDD 23 PWR DigitalPower Supply,1.65V-1.95V DVSS 24 GND DigitalGround,0V

3 ELECTRICAL SPECIFICATIONS

3.1 AbsoluteMaximum Ratings

overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) VALUE UNIT MIN MAX AVDD toAVSS –0.3 2.2 V DVDD toDVSS –0.3 2.2 V SPKVDD toSPKVSS –0.3 6 V IOVDD toIOVSS –0.3 3.9 V Digitalinputvoltage IOVSS – 0.3 IOVDD + 0.3 V Analoginputvoltage AVSS – 0.3 AVDD + 0.3 V Operatingtemperaturerange –40 85 °C Storagetemperaturerange –55 150 °C Junctiontemperature(TJ Max) 105 °C QFN Power dissipation(withthermalpad solderedtoboard) (TJ Max – TA)/θJA W (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderRecommended Operating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability.

3.2 THERMAL INFORMATION

THERMAL METRIC (1) UNITS RGE (24PINS) θJA Junction-to-ambientthermalresistance 32.2 θJCtop Junction-to-case(top)thermalresistance 30.0 θJB Junction-to-boardthermalresistance 9.2 °C/W ψJT Junction-to-topcharacterizationparameter 0.3 ψJB Junction-to-boardcharacterizationparameter 9.2 θJCbot Junction-to-case(bottom)thermalresistance 2.2 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953

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www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013

3.3 Recommended OperatingConditions

overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT AVDD (1) ReferencedtoAVSS (2) 1.5 1.8 1.95 Power-supplyvoltagerange DVDD ReferencedtoDVSS (2) 1.65 1.8 1.95 V SPKVDD (1) ReferencedtoSPKVSS (2) 2.7 5.5 IOVDD ReferencedtoIOVSS (2) 1.1 1.8 3.6 Speakerimpedance Load appliedacrossclass-Doutputpins(BTL) 4 Ω Headphone impedance AC-coupledtoR L 16 Ω Analogaudiofull-scaleinputVI AVDD = 1.8V,single-ended 0.5 VRMSvoltage Lineoutputloadimpedance AC-coupledtoR L 10 kΩ(inhalfdriveabilitymode) MCLK (3) Masterclockfrequency IOVDD = DVDD = 1.8V 50 MHz SCL SCL clockfrequency 400 kHz TA Operatingfree-airtemperature –40 85 °C (1) To minimizebattery-currentleakage,theSPKVDD voltagelevelshouldnotbe belowtheAVDD voltagelevel. (2) Allgroundson boardaretiedtogether,so theyshouldnotdifferinvoltageby more than0.2V maximum forany combinationofground signals.By use ofa widetraceorgroundplane,ensurea low-impedanceconnectionbetween AVSS and DVSS. (3) The maximum inputfrequencyshouldbe 50 MHz forany digitalpinused as a general-purposeclock.

3.4 ElectricalCharacteristics

At25°C, AVDD = 1.8V,IOVDD = 1.8V,SPKVDD = 3.6V,DVDD = 1.8V,fS (audio)= 48 kHz,CODEC_CLKIN = 256 × fS, PLL = Off PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL OSCILLATOR — RC_CLK Oscillatorfrequency 8.48 MHz Audio DAC – StereoSingle-EndedHeadphone Output Load = 16Ω (single-ended),Input& OutputCM = 0.9V,DOSR = 128,DeviceSetupMCLK = 256*fs, DeviceSetup ChannelGain = 0dB word length= 16 bits; ProcessingBlock= PRB_P1 Power Tune = PTM_P3 Full-scaleoutputvoltage(0dB) 0.5 Vrms ICN Idlechannelnoise Measured as idle-channelnoise,A-weighted(1)(2) 20.7 μVms THD+N Totalharmonicdistortion+ noise 0-dBFS input,1-kHzinputsignal -78.2 dB Mute attenuation Mute 103.7 dB PSRR Power-supplyrejectionratio(3) Rippleon AVDD (1.8V) = 200 mV PP at1 kHz 47.2 dB DR Dynamic range,A-weighted(1)(2) –60dB 1kHz inputfull-scalesignal 88.1 Gain error 0dB,1kHz inputfullscalesignal ±0.3 dB R L = 32 Ω,THD+N ≤ –40 dB 11 PO Maximum outputpower mW R L = 16 Ω,THD+N ≤ –40 dB 18 (1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measured A-weightedovera 20-Hz to20-kHzbandwidthusingan audioanalyzer. (2) Allperformancemeasurements done with20-kHzlow-passfilterand,where noted,A-weightedfilter.Failuretouse such a filtermay resultinhigherTHD+N and lowerSNR and dynamicrangereadingsthanshown intheElectricalCharacteristics.The low-passfilter removes out-of-bandnoise,which,althoughnotaudible,may affectdynamicspecificationvalues. (3) DAC toheadphone-outPSRR measurement iscalculatedas PSRR = 20 X log(∆VHP /∆VAVDD ). Copyright© 2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 5 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com ElectricalCharacteristics(continued) At25°C, AVDD = 1.8V,IOVDD = 1.8V,SPKVDD = 3.6V,DVDD = 1.8V,fS (audio)= 48 kHz,CODEC_CLKIN = 256 × fS, PLL = Off PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Audio DAC – StereoSingle-EndedHeadphone Output Load = 16Ω (single-ended),Input& OutputCM = 0.75V,DOSR = 128,DeviceSetupMCLK = 256* DeviceSetup fs,ChannelGain = 0dB word length= 16 bits; ProcessingBlock= PRB_P1 Power Tune = PTM_P3 Full-scaleoutputvoltage(0dB) 0.375 Vrms ICN Idlechannelnoise Measured as idle-channelnoise,A-weighted(1)(2) 18.1 μVms THD+N Totalharmonicdistortion+ noise 0-dBFS input,1-kHzinputsignal -78.2 dB Mute attenuation Mute 105.5 dB PSRR Power-supplyrejectionratio(3) Rippleon AVDD (1.8V) = 200 mV PP at1 kHz 48.4 dB DR Dynamic range,A-weighted(1)(2) –60dB 1kHz inputfull-scalesignal 86.8 Gain error 0dB,1kHz inputfullscalesignal ±0.3 dB R L = 32 Ω,THD+N ≤ –40 dB 8 PO Maximum outputpower mW R L = 16 Ω,THD+N ≤ –40 dB 16 DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS See forDAC interpolationfiltercharacteristics. DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 4 Ω (DIFFERENTIAL) BTL measurement,class-Dgain= 6 dB,MeasuredICN Idlechannelnoise 37 μVmsas idle-channelnoise,A-weighted(1)(2) BTL measurement,class-Dgain= 6 dB,-3dBFSOutputvoltage 1.4 Vrmsinput BTL measurement,DAC input= –6 dBFS, class-DTHD+N Totalharmonicdistortion+ noise –73.9 dBgain= 6 dB BTL measurement,rippleon SPKVDD = 200 mV PPPSRR Power-supplyrejectionratio 55 dBat1 kHz Mute attenuation Mute 103 dB SPKVDD = 3.6V,BTL measurement,CM = 0.9V, 1.1class-Dgain= 18 dB,THD = 10% SPKVDD = 4.2V,BTL measurement,CM = 0.9V, 1.4class-Dgain= 18 dB,THD = 10% SPKVDD = 3.6V,BTL measurement,CM = 0.9V,PO Maximum outputpower 0.8 Wclass-Dgain= 18 dB,THD = 1% SPKVDD = 4.2V,BTL measurement,CM = 0.9V, 1.1class-Dgain= 18 dB,THD = 1% SPKVDD = 5.5V,BTL measurement,CM = 0.9V, 2class-Dgain= 18 dB (1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measured A-weightedovera 20-Hz to20-kHzbandwidthusingan audioanalyzer. (2) Allperformancemeasurements done with20-kHzlow-passfilterand,where noted,A-weightedfilter.Failuretouse such a filtermay resultinhigherTHD+N and lowerSNR and dynamicrangereadingsthanshown intheElectricalCharacteristics.The low-passfilter removes out-of-bandnoise,which,althoughnotaudible,may affectdynamicspecificationvalues. (3) DAC toheadphone-outPSRR measurement iscalculatedas PSRR = 20 X log(∆VHP /∆VAVDD ).

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www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 ElectricalCharacteristics(continued) At25°C, AVDD = 1.8V,IOVDD = 1.8V,SPKVDD = 3.6V,DVDD = 1.8V,fS (audio)= 48 kHz,CODEC_CLKIN = 256 × fS, PLL = Off PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 8 Ω (DIFFERENTIAL) BTL measurement,class-Dgain= 6 dB,MeasuredICN Idlechannelnoise 35.2 μVmsas idle-channelnoise,A-weighted(1)(2) BTL measurement,class-Dgain= 6 dB,-3dBFSOutputvoltage 1.4 Vrmsinput BTL measurement,DAC input= –6 dBFS, class-DTHD+N Totalharmonicdistortion+ noise –73.6 dBgain= 6 dB SPKVDD = 3.6V,BTL measurement,CM = 0.9V, 0.7class-Dgain= 18 dB,THD = 10% SPKVDD = 4.2V,BTL measurement,CM = 0.9V, 1class-Dgain= 18 dB,THD = 10% SPKVDD = 5.5V,BTL measurement,CM = 0.9V, 1.7class-Dgain= 18 dB,THD = 10% PO Maximum outputpower W SPKVDD = 3.6V,BTL measurement,CM = 0.9V, 0.5class-Dgain= 18 dB,THD = 1% SPKVDD = 4.2V,BTL measurement,CM = 0.9V, 0.8class-Dgain= 18 dB,THD = 1% SPKVDD = 5.5V,BTL measurement,CM = 0.9V, 1.3class-Dgain= 18 dB,THD = 1% ANALOG BYPASS TO HEADPHONE AMPLIFIER AC-COUPLED LOAD = 16 Ω (SINGLE-ENDED), DeviceSetup DRIVER GAIN = 0 dB,Inputand outputcommon- mode = 0.9V,inputsignalfrequencyfi= 1kHz VoltageGain Inputcommon-mode = 0.9V 1 V/V Gain Error -1dBFS (446mVrms),1-kHzinputsignal ±0.8 dB Idlechannel,IN1L and IN1R ac-shortedtoground,ICN Idlechannelnoise 10.2 μVmsMeasured as idle-channelnoise,A-weighted(1)(2) THD+N Totalharmonicdistortion+ noise -1dBFS (446mVrms),1-kHzinputsignal -80.4 dB (1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measured A-weightedovera 20-Hz to20-kHzbandwidthusingan audioanalyzer. (2) Allperformancemeasurements done with20-kHzlow-passfilterand,where noted,A-weightedfilter.Failuretouse such a filtermay resultinhigherTHD+N and lowerSNR and dynamicrangereadingsthanshown intheElectricalCharacteristics.The low-passfilter removes out-of-bandnoise,which,althoughnotaudible,may affectdynamicspecificationvalues. Copyright© 2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 7 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com ElectricalCharacteristics(continued) At25°C, AVDD = 1.8V,IOVDD = 1.8V,SPKVDD = 3.6V,DVDD = 1.8V,fS (audio)= 48 kHz,CODEC_CLKIN = 256 × fS, PLL = Off PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG BYPASS TO CLASS-D SPEAKER AMPLIFIER BTL measurement,DRIVER GAIN = 6 dB,LOAD DeviceSetup = 4 Ω (DIFFERENTIAL),50 pF,inputsignal frequencyfi= 1 KHz VoltageGain Inputcommon-mode = 0.9V 4 V/V Gain Error -1dBFS (446mVrms),1-kHzinputsignal ±0.7 dB Idlechannel,IN1L and IN1R ac-shortedtoground,ICN Idlechannelnoise 32.6 μVmsMeasured as idle-channelnoise,A-weighted(1)(2) THD+N Totalharmonicdistortion+ noise -1dBFS (446mVrms),1-kHzinputsignal -73.7 dB LOW DROPOUT REGULATOR (AVDD) SPKVDD = 2.7V,Page 1,Reg 2,D5-D4 = 00,IO =AVDD OutputVoltage1.8V 1.79 V50mA SPKVDD = 3.6V,Page 1,Reg 2,D5-D4 = 00,IO = 1.79 V50mA SPKVDD = 5.5V,Page 1,Reg 2,D5-D4 = 00,IO = 1.79 V50mA OutputVoltageAccuracy SPVDD = 2.7V ±2 % Load Regulation SPVDD = 2.7V,0A to50mA 7 mV LineRegulation InputSupplyRange 2.7Vto5.5V 0.6 mV DecouplingCapacitor 1.0 uF BiasCurrent 55 uA Noise@0A Load A-weighted,20Hz to20kHz bandwidth 166 uV Noise@50mA Load A-weighted,20Hz to20kHz bandwidth 174 uV SHUTDOWN POWER CONSUMPTION Power down POR, /RST heldlow,AVDD = 1.8V,DeviceSetup IOVDD = 1.8V,SPKVDD = 4.2V,DVDD = 1.8V I(AVDD) 1.32 µA I(DVDD) 0.04 µA I(IOVDD) 0.68 µA I(SPKVDD) 2.24 µA DIGITAL INPUT/OUTPUT Logicfamily CMOS 0.7×IIH = 5 μA,IOVDD ≥ 1.6V IOVDDVIH V IIH = 5 μA,IOVDD < 1.6V IOVDD 0.3×IIL= 5 μA,IOVDD ≥ 1.6V –0.3 IOVDDVIL Logiclevel V IIL= 5 μA,IOVDD < 1.6V 0 0.8×VOH IOH = 2 TTL loads VIOVDD VOL IOL = 2 TTL loads 0.25 V Capacitiveload 10 pF (1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measured A-weightedovera 20-Hz to20-kHzbandwidthusingan audioanalyzer. (2) Allperformancemeasurements done with20-kHzlow-passfilterand,where noted,A-weightedfilter.Failuretouse such a filtermay resultinhigherTHD+N and lowerSNR and dynamicrangereadingsthanshown intheElectricalCharacteristics.The low-passfilter removes out-of-bandnoise,which,althoughnotaudible,may affectdynamicspecificationvalues.

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t (WS)d t (DI)S t (DI)h tr tf TAS2521 www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013

3.5 Timing Characteristics

3.5.1 I2S/LJF/RJF Timing inMaster Mode

Allspecificationsat25°C, DVDD = 1.8V Note:Alltimingspecificationsaremeasured atcharacterizationbutnottestedatfinaltest. PARAMETER IOVDD = 1.8V IOVDD = 3.3V UNIT MIN MAX MIN MAX td(WS) WCLK delay 45 45 ns ts(DI) DIN setup 8 6 ns th(DI) DIN hold 8 6 ns tr Risetime 25 10 ns tf Falltime 25 10 ns Figure3-1.I2S/LJF/RJF Timing inMaster Mode Copyright© 2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 9 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

t (WS)h t (BCLK)H t (DI)S t (BCLK)L t (DI)h t (WS)S tr tf TAS2521 SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com

3.5.2 I2S/LJF/RJF Timing inSlaveMode

Allspecificationsat25°C, DVDD = 1.8V Note:Alltimingspecificationsaremeasured atcharacterizationbutnottestedatfinaltest. IOVDD = 1.8V IOVDD = 3.3VPARAMETER UNITMIN MAX MIN MAX tH (BCLK) BCLK highperiod 35 35 ns tL(BCLK) BCLK lowperiod 35 35 ns ts(WS) WCLK setup 8 6 ns th(WS) WCLK hold 8 6 ns ts(DI) DIN setup 8 6 ns th(DI) DIN hold 8 6 ns tr Risetime 4 4 ns tf Falltime 4 4 ns Figure3-2.I2S/LJF/RJF Timing inSlaveMode

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t (WS)d t (WS)d t (DI)S t (DI)h tf tr TAS2521 www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013

3.5.3 DSP Timing inMaster Mode

Allspecificationsat25°C, DVDD = 1.8V Note:Alltimingspecificationsaremeasured atcharacterizationbutnottestedatfinaltest. IOVDD = 1.8V IOVDD = 3.3VPARAMETER UNITMIN MAX MIN MAX td(WS) WCLK delay 45 45 ns ts(DI) DIN setup 8 6 ns th(DI) DIN hold 8 6 ns tr Risetime 25 10 ns tf Falltime 25 10 ns Figure3-3.DSP Timing inMaster Mode Copyright© 2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 11 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

t (WS)h t (WS)h t (BCLK)L tr tf t (DI)St (BCLK)H t (DI)h t (WS)S t (WS)S TAS2521 SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com

3.5.4 DSP Timing inSlaveMode

Allspecificationsat25°C, DVDD = 1.8V Note:Alltimingspecificationsaremeasured atcharacterizationbutnottestedatfinaltest. IOVDD = 1.8V IOVDD = 3.3VPARAMETER UNITMIN MAX MIN MAX tH (BCLK) BCLK highperiod 35 35 ns tL(BCLK) BCLK lowperiod 35 35 ns ts(WS) WCLK setup 8 8 ns th(WS) WCLK hold 8 8 ns ts(DI) DIN setup 8 8 ns th(DI) DIN hold 8 8 ns tr Risetime 4 4 ns tf Falltime 4 4 ns Figure3-4.DSP Timing inSlaveMode

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tSU;ST A tHIGH tHD;ST A tr tHD;ST A tHD;DA T tSU;DA T tSU;STO tf T0295-02 TAS2521 www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013

3.5.5 I2C InterfaceTiming

Allspecificationsat25°C, DVDD = 1.8V Note:Alltimingspecificationsaremeasured atcharacterizationbutnottestedatfinaltest. PARAMETER Standard-Mode Fast-Mode UNITS MIN TYP MAX MIN TYP MAX fSCL SCL clockfrequency 0 100 0 400 kHz Holdtime(repeated)START condition. tHD;STA Afterthisperiod,thefirstclockpulseis 4 0.8 μs generated. tLOW LOW periodoftheSCL clock 4.7 1.3 μs tHIGH HIGH periodoftheSCL clock 4 0.6 μs Setuptimefora repeatedSTARTtSU;STA 4.7 0.8 μscondition tHD;DAT Data holdtime:ForI2C bus devices 0 3.45 0 0.9 μs tSU;DAT Data setuptime 250 100 ns tr SDA and SCL risetime 1000 20 + 0.1C b 300 ns tf SDA and SCL falltime 300 20 + 0.1C b 300 ns tSU;STO Set-uptimeforSTOP condition 4 0.8 μs Bus freetimebetween a STOP andtBUF 4.7 1.3 μsSTART condition C b Capacitiveloadforeach bus line 400 400 pF Figure3-5.I2C InterfaceTiming Copyright© 2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 13 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

MSB OUT BIT 6 . . . 1 LSB OUT tscktLead tLag tsckh tsckl trtf tv(DOUT) tdis MSB IN BIT 6 . . . 1 LSB IN thit su SS SCLK MISO MOSI TAS2521 SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com

3.5.6 SPI InterfaceTiming

Figure3-6.SPI InterfaceTiming Diagram Timing Requirements At25°C, DVDD = 1.8V Table3-1.SPI InterfaceTiming PARAMETER TEST CONDITION IOVDD=1.8V IOVDD=3.3V UNITS MIN TYP MAX MIN TYP MAX tsck SCLK Period(1) 100 50 ns tsckh SCLK PulsewidthHigh 50 25 ns tsckl SCLK PulsewidthLow 50 25 ns tlead EnableLead Time 30 20 ns tlag EnableLag Time 30 20 ns td SequentialTransferDelay 40 20 ns ta SlaveDOUT accesstime 40 40 ns tdis SlaveDOUT disabletime 40 40 ns tsu DIN datasetuptime 15 15 ns thi DIN dataholdtime 15 10 ns tv;DOUT DOUT datavalidtime 25 18 ns tr SCLK RiseTime 4 4 ns tf SCLK FallTime 4 4 ns (1) These parametersarebased on characterizationand arenottestedinproduction.

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0.01 0.10 1.00 10.00 100.00 0 0.5 1 1.5 2 2.5 THDN (%) Output Power (W) Series1 Series2 Series4 Series5 C005 Gain = 6 dB Gain = 12 dB Gain = 18 dB Gain = 24 dB 0.01 0.1 100 0 0.5 1 1.5 2 2.5 THDN (%) Output Power (W) Series1 Series2 Series4 Series5 Series6 Series7 C006 SPKVDD = 2.7 V SPKVDD = 3 V SPKVDD = 3.3 V SPKVDD = 3.6 V SPKVDD = 4.2 V SPKVDD = 5.5 V 0.01 0.1 100 0 0.5 1 1.5 2 2.5 3 THDN (%) Output Power (W) Gain = 6 dB Gain = 12 dB Gain = 18 dB Gain = 24 dB C003 0.01 0.10 1.00 10.00 100.00 0 0.5 1 1.5 2 2.5 3 THDN (%) Output Power (W) Series1 Series2 Series4 Series5 Series6 Series7 C004 SPKVDD=2.7V SPKVDD=3V SPKVDD=3.3V SPKVDD=3.6V SPKVDD=4.2V SPKVDD=5.5V ±180 ±160 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 4000 8000 12000 16000 20000 Amlitude (dB) Frequency (Hz) C001 ±180 ±160 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 4000 8000 12000 16000 20000 Amplitude (dB) Frequency (Hz) C002 TAS2521 www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013

4 TypicalPerformance

4.1 Class D Speaker DriverPerformance

Figure4-1.DAC To Speaker Amplitude at0 dBFS vs Frequency (4 Figure4-2.AINL To Speaker FFT Amplitude at0 dBFS vs Ω Load) Frequency (4Ω Load) Figure4-3.TotalHarmonic Distortion+ Noise vs 4 Ω Speaker Figure4-4.TotalHarmonic Distortion+ Noise + NOISE vs 4 Ω Power (SPKVDD = 5.5V) Speaker Power (Gain= 18 dB) Figure4-5.TotalHarmonic Distortion+ Noise + NOISE vs 8 Ω Figure4-6.TotalHarmonic Distortion+ Noise + NOISE vs 8 Ω Speaker Power (SPKVDD = 5.5V) Speaker Power (Gain= 18 dB) Copyright© 2013,Texas InstrumentsIncorporated TypicalPerformance 15 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

0 200 400 600 800 1000 1200 1400 1600 1800 Efficiency (%) Output Power (mWatt) SPKVDD = 2.7 V SPKVDD = 3 V SPKVDD = 3.3 V SPKVDD = 3.6 V SPKVDD = 4.2 V SPKVDD = 5.5 V C007 TAS2521 SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com Figure4-7.TotalPower Consumption vs Output Power Consumption (Gain= 18 dB, Load = 4 Ω)

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±90 ±80 ±70 ±60 ±50 ±40 ±30 ±20 ±10 THDN (%) Output Power (mW) CM=0.75V,AVDD=1.5V CM=0.75V,AVDD=1.8V CM=0.75V,AVDD=1.95V CM=0.9V,AVDD=1.8V CM=0.9V,AVDD=1.95V C010 ±90 ±80 ±70 ±60 ±50 ±40 ±30 ±20 ±10 THDN (dB) Output Power (mW) Series1 Series2 Series4 Series5 Series6 C011 CM=0.75V, AVDD=1.5V CM=0.75V, AVDD=1.8V CM=0.75V, AVDD=1.95V CM=0.9V, AVDD=1.8V CM=0.9V, AVDD=1.95V ±180 ±160 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 4000 8000 12000 16000 20000 Amplitude ( dB) Frequency (Hz) C008 0dBFS ±180 ±160 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 4000 8000 12000 16000 20000 Amplitude ( dB) Frequency (Hz) C008 0dBFS TAS2521 www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013

4.2 HP DriverPerformance

Figure4-8.DAC TO HP FFT Amplitude at0 dBFS vs Frequency Figure4-9.AINL TO HP FFT Amplitude at0 dBFS vs Frequency (16Ω Load) (16Ω Load) Figure4-10.TotalHarmonic Distortion+ Noise vs HP Power Figure4-11.TotalHarmonic Distortion+ Noise vs HP Power (Gain= 9 dB) (Gain= 32 dB) Copyright© 2013,Texas InstrumentsIncorporated TypicalPerformance 17 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

SPKVSSAVDDAVSS LDO_SEL SPKVDD SCL/SSZ SDA/MOSI GPIO/DOUT RST DVDD DVSS IOVDD IOVSS AINL SPKP SPKM HOST PROCESSOR 0.1PF 22PF SVDD 0.1PF22PF +1.8VA 8-: or 4-: Speaker +1.8VD IOVDD AINR Analog Input TAS2521 HPOUT Headphone jack MISO SPI_SEL SCLK IOVDD 0.1PF 0.1PF 2.7k 2.7k 47PF 0.1PF 10PF 0.1PF 10PF TAS2521 SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com

5 ApplicationOverview

The TAS2521 offersa wide range of configurationoptions.Figure1-1 shows the simplifiedfunctional blocksofthedevice.

5.1 TypicalCircuitConfiguration

Figure5-1.TypicalCircuitConfiguration

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SPKVSSAVDDAVSS LDO_SEL SPKVDD SCL/SSZ SDA/MOSI GPIO/DOUT RST IOVDD IOVSS AINL SPKP SPKM HOST PROCESSOR 0.1PF 22PF SVDD 0.1PF22PF 8-: or 4-: Speaker IOVDD AINR Analog Input TAS2521 HPOUT MISO SPI_SEL SCLK IOVDD 0.1PF 0.1PF 2.7k 2.7k 47PF DVDDDVSS 0.1PF10PF 0.1PF 10PF TAS2521 www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013

5.2 CircuitConfigurationwithInternalLDO

Figure5-2.ApplicationSchematics forLDO

5.3 Device Connections

5.3.1 DigitalPins

Only a smallnumber ofdigitalpinsarededicatedtoa singlefunction;whenever possible,thedigitalpins have a defaultfunction,and also can be reprogrammed to cover alternativefunctionsforvarious applications. The fixed-functionpinsareRST LDO_SEL and theSPI_SEL pin,which are HW controlpins.Depending on thestateofSPI_SEL, thetwo control-buspinsSCL/SSZ and SDA/MOSI are configuredforeitherI2C orSPI protocol. OtherdigitalIO pinscan be configuredforvariousfunctionsviaregistercontrol.An overviewofavailable functionalityisgiveninSection5.3.3.

5.3.2 Analog Pins

Analog functionscan alsobe configuredto a largedegree.For minimum power consumption,analog blocksarepowered down by default.The blockscan be powered up withfinegranularityaccordingtothe applicationneeds. Copyright© 2013,Texas InstrumentsIncorporated ApplicationOverview 19 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

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5.3.3 MultifunctionPins

Table5-1shows thepossibleallocationofpinsforspecificfunctions.The PLL input,forexample,can be programmed tobe any of4 pins(MCLK, BCLK, DIN,GPIO). Table5-1.MultifunctionPin Assignments 1 2 3 4 5 6 7 Pin Function MCLK BCLK WCLK DIN GPIO SCLK MISO /DOUT A PLL Input S (1) S (2) E S (3) B Codec ClockInput S (1),D(4) S (2) S (3) C I2S BCLK input S (2),D D I2S BCLK output E (5) E I2S WCLK input E,D F I2S WCLK output E G I2S DIN E,D H I2S DOUT E I GeneralPurposeOutputI E I GeneralPurposeOutputII E J GeneralPurposeInputI E J GeneralPurposeInputII E J GeneralPurposeInputIII E K INT1 output E E L INT2 output E E M SecondaryI2S BCLK input E E N SecondaryI2S WCLK input E E O SecondaryI2S DIN E E P SecondaryI2S BCLK OUT E E Q SecondaryI2S WCLK OUT E E R SecondaryI2S DOUT E S Aux ClockOutput E E (1) S(1):The MCLK pincan drivethePLL and Codec Clockinputssimultaneously. (2) S(2):The BCLK pincan drivethePLL and Codec Clockand audiointerfacebitclockinputssimultaneously. (3) S(3):The GPIO/DOUT pincan drivethePLL and Codec Clockinputssimultaneously. (4) D: DefaultFunction (5) E:The pinisexclusivelyused forthisfunction,no otherfunctioncan be implementedwiththesame pin.(IfGPIO/DOUT has been allocatedforGeneralPurposeOutput,itcannotbe used as theINT1 outputatthesame time.)

5.4 Audio Analog I/O

The TAS2521 featuresa mono audio DAC. Itsupportsa wide range of analog interfacesto support differentheadsetssuch as 16-Ω to200-Ω impedance and analoglineoutputs.TheTAS2521 can drivea speakerupto4-Ω impedance.

5.5 Analog Signals

The TAS2521 analogsignalsconsistof:

• Analog inputsAINR and AINL, which can be used to pass-throughor mix analogsignalsto output stages
• Analogoutputsclass-Dspeakerdriverand headphone/lineoutdriverprovidingoutputcapabilityforthe DAC, AINR, AINL,ora mix ofthethree

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5.5.1 Analog InputsAINL and AINR

AINL (pin3 orC2) and AINR (pin4 orB2) areinputstoMixerP and MixerM alongwiththeDAC output. AlsoAINL and AINR can be configuredinputstoHP driver.Page1 /register12 providescontrolsignalsfor determiningthe signalsroutedthroughMixer P, Mixer M and HP driver.Inputof Mixer P can be attenuatedby Page1 /register24,inputofMixerM can be attenuatedby Page1 /register25 and inputof HP drivercan be attenuatedby Page1 /register22.AlsoAINL and AINR can be configuredtoa monaural differentialinputwithuse MixerP and MixerM by Page1 /register12 setting. Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ).

5.6 Audio DAC and Audio Analog Outputs

The mono audioDAC consistsof a digitalaudioprocessingblock,a digitalinterpolationfilter,a digital delta-sigmamodulator,and an analogreconstructionfilter.The highoversamplingratio(normallyDOSR is between 32 and 128) exhibitsgood dynamic range by ensuringthatthe quantizationnoisegenerated withinthedelta-sigmamodulatorstaysoutsideoftheaudiofrequencyband.Audioanalogoutputsinclude mono headphone and lineoutand mono class-Dspeakeroutputs.Because theTAS2521 containsa mono DAC, itinputsthe mono data from the leftchannel,the rightchannel,or a mix of the leftand right channelsas [(L+ R) ÷ 2],selectedby page 0,register63,bitsD5 –D4. Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ).

5.6.1 DAC

The TAS2521 mono audioDAC supportsdata ratesfrom 8 kHz to 192 kHz. The audiochannelof the mono DAC consistsofa signal-processingenginewithfixedprocessingblocks,a programmableminiDSP, a digitalinterpolationfilter,multibitdigitaldelta-sigmamodulator,and an analogreconstructionfilter.The DAC isdesignedtoprovideenhanced performanceatlow samplingratesthroughincreasedoversampling and image filtering,therebykeepingquantizationnoisegeneratedwithinthe delta-sigmamodulatorand observedinthesignalimages stronglysuppressedwithintheaudioband tobeyond 20 kHz. To handle multipleinputratesand optimizepower dissipationand performance,the TAS2521 allowsthe system designerto program the oversamplingratesover a wide range from 1 to 1024 by configuringpage 0, register13 and page 0 /register14.The systemdesignercan choose higheroversamplingratiosforlower inputdataratesand loweroversamplingratiosforhigherinputdatarates. The TAS2521 DAC channelincludesa built-indigitalinterpolationfiltertogenerateoversampleddatafor thedelta-sigmamodulator.The interpolationfiltercan be chosen fromthreedifferenttypes,dependingon requiredfrequencyresponse,groupdelay,and samplingrate. The DAC pathoftheTAS2521 featuresmany optionsforsignalconditioningand signalrouting:

• Digitalvolume controlwitha rangeof-63.5to+24dB
• Mute function InadditiontothestandardsetofDAC featurestheTAS2521 alsooffersthefollowingspecialfeatures:
• Digitalautomute
• Adaptivefiltermode

5.6.1.1 DAC ProcessingBlocks — Overview

The TAS2521 implementssignal-processingcapabilitiesand interpolationfilteringviaprocessingblocks. These fixedprocessingblocksgiveusersthechoiceofhow much and what typeofsignalprocessingthey may use and whichinterpolationfilterisapplied. The choicesamong theseprocessingblocksallowsthesystem designertobalancepower conservation and signal-processingflexibility.Table5-2givesan overviewofallavailableprocessingblocksoftheDAC channel and theirproperties.The resource-classcolumn gives an approximateindicationof power consumptionforthedigital(DVDD) supply;however,based on theout-of-bandnoisespectrum,theanalog power consumptionofthedrivers(AVDD) may differ. Copyright© 2013,Texas InstrumentsIncorporated ApplicationOverview 21 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com The signal-processingblocksavailableare:

• First-orderIIR
• Scalablenumber ofbiquadfilters The processingblocksare tunedforcommon cases and can achievehighimage rejectionor low group delayincombinationwithvarioussignal-processingeffectssuch as audioeffectsand frequencyshaping. The availablefirst-orderIIRand biquadfiltershave fullyuser-programmablecoefficients. Table5-2.Overview – DAC PredefinedProcessingBlocks Processing First-Order Number of ResourceInterpolationFilter ChannelBlock No. IIRAvailable Biquads Class PRB_P1 A Mono Yes 6 6 PRB_P2 A Mono No 3 4 PRB_P3 B Mono Yes 6 4 Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ).

5.6.2 DigitalMixingand Routing

The TAS2521 has fourdigitalmixingblocks.Each mixercan provideeithermixingor multiplexingofthe digitalaudiodata.The firstmixer/multiplexercan be used toselectinputdataforthemono DAC fromleft channel,rightchannel,or(leftchannel+ rightchannel)/2 mixing.Thisdigitalroutingcan be configuredby writingtopage 0,register63,bitsD5 –D4.

5.6.3 Analog Audio Routing

The TAS2521 has thecapabilitytoroutetheDAC outputtoeithertheheadphone orthespeakeroutput.If desirable,bothoutputdriverscan be operatedatthesame timewhileplayingatdifferentvolume levels. The TAS2521 providesvariousdigitalroutingcapabilities,allowingdigitalmixing or even channel swappinginthedigitaldomain.Allanalogoutputsotherthantheselectedones can be powered down for optimalpower consumption. Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ). 5.6.4 5V LDO The TAS2521 has a built-inLDO which can generatethe analogsupply(AVDD) alsothe digitalsupply (DVDD) from inputvoltagerange of2.7V to5.5V withhighPSRR. Ifcombined power supplycurrentis 50 mA or less,then thisLDO can deliverpower to both analogand digitalpower supplies.Ifthe only speakerpower supplyispresentand LDO Selectpinisenabled,theLDO can power up withoutrequiring othersupplies.ThisLDO requiresa minimum dropoutvoltageof300 mV and can supportloadcurrentsup to50 mA. For stabilityreasonstheLDO requiresa minimum decouplingcapacitorof1 µF (±50%) on the analogsupply(AVDD) pinand thedigitalsupply(DVDD) pin.Ifuse thisLDO outputvoltageforthedigital supply(DVDD) pin,the analogsupply(AVDD) pinconnectedto the digitalsupply(DVDD) externallyis required. The LDO is by defaultpowered down forlow sleep mode currentsand can be enabled drivingthe LDO_SELECT pintoSPKVDD (Speakerpower supply).When theLDO isdisabledtheAVDD pinistri- statedand thedeviceAVDD needs tobe powered usingexternalsupply.Inthatcase theDVDD pinis alsotri-statedand thedeviceDVDD needs tobe powered usingexternalsupply.The outputvoltageofthis LDO can be adjustedtoa few differentvaluesas givenintheTable5-3.

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www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 Table5-3.AVDD LDO Settings Page-1,Register2,D(5:4) LDO Output 00 1.8V 01 1.6V 10 1.7V 00 1.5V Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ).

5.6.5 POR

TAS2521 has a POR (Power On Reset)function.Thisfunctioninsuresthatallregistersareautomatically settodefaultswhen a properpower up sequence isexecuted. Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ).

5.6.6 CLOCK Generationand PLL

The TAS2521 supportsa wide range of optionsforgeneratingclocksforthe DAC sectionsas wellas interfaceand othercontrolblocks.The clocksfortheDAC requirea sourcereferenceclock.Thisclockcan be providedon a varietyofdevicepins,such as theMCLK, BCLK, or GPIO pins.The sourcereference clockforthecodec can be chosen by programmingtheCODEC_CLKIN valueon page 0,register4,bits D1 –D0. The CODEC_CLKIN can then be routedthroughhighly-flexibleclockdividersshown in to generatethevariousclocksrequiredfortheDAC and theminiDSP section.Intheeventthatthedesired audioclockscannotbe generatedfromthereferenceclockson MCLK, BCLK, orGPIO, theTAS2521 also providesthe optionof usingthe on-chipPLL which supportsa wide range of fractionalmultiplication valuesto generatethe requiredclocks.Startingfrom CODEC_CLKIN, the TAS2521 providesseveral programmable clockdividerstohelpachievea varietyofsamplingratesfortheDAC and clocksforthe miniDSP sections. Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ).

5.6.7 DigitalAudio and ControlInterface

5.6.7.1 DigitalAudio Interface

Audio dataistransferredbetween thehostprocessorand theTAS2521 viathedigitalaudiodataserial interface,or audio bus. The audio bus on thisdeviceis flexible,includingleft-or right-justifieddata options,support for I2S or PCM protocols,programmable data-lengthoptions,a TDM mode for multichanneloperation,flexiblemaster/slaveconfigurabilityforeach bus clockline,and the abilityto communicatewithmultipledeviceswithina systemdirectly. The audiobus oftheTAS2521 can be configuredforleft-or right-justified,I2S, DSP, or TDM modes of operation,where communicationwithstandardtelephonyPCM interfacesissupportedwithinthe TDM mode. These modes are allMSB-first,withdata widthprogrammable as 16, 20, 24, or 32 bitsby configuringpage 0,register27,bitsD5 –D4. Inaddition,theword clockand bitclockcan be independently configuredineithermaster or slavemode forflexibleconnectivityto a wide varietyof processors.The word clockisused todefinethebeginningofa frame,and may be programmed as eithera pulseor a square-wave signal.The frequencyof thisclockcorrespondsto the maximum of the selectedDAC samplingfrequencies. Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ).

5.6.7.2 ControlInterface

The TAS2521 controlinterfacesupportsSPI orI2C communicationprotocols,withtheprotocolselectable usingtheSPI_SEL pin.For SPI,SPI_SEL shouldbe tiedhigh;forI2C,SPI_SEL shouldbe tiedlow.Itis notrecommended tochange thestateofSPI_SEL duringdeviceoperation. Copyright© 2013,Texas InstrumentsIncorporated ApplicationOverview 23 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com 5.6.7.2.1I2C ControlMode The TAS2521 supportstheI2C controlprotocol,and willrespondtotheI2C addressof0011 000.I2C isa two-wire,open-draininterfacesupportingmultipledevicesand masterson a singlebus.Deviceson the I2C bus onlydrivethebus linesLOW by connectingthem toground;theyneverdrivethebus linesHIGH. Instead,thebus wiresarepulledHIGH by pullupresistors,so thebus wiresareHIGH when no deviceis drivingthem LOW. Thisway, two devicescannotconflict;iftwo devicesdrivethe bus simultaneously, thereisno drivercontention. 5.6.7.2.2SPI DigitalInterface In the SPI controlmode,the TAS2521 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO, SDA/MOSI=MOSI as a standardSPI portwithclockpolaritysettingof 0 (typicalmicroprocessorSPI controlbitCPOL = 0).The SPI portallowsfull-duplex,synchronous,serialcommunicationbetween a host processor(themaster)and peripheraldevices(slaves).The SPI master(inthiscase,thehostprocessor) generatesthesynchronizingclock(drivenontoSCLK) and initiatestransmissions.The SPI slavedevices (suchas theTAS2521) depend on a mastertostartand synchronizetransmissions.A transmissionbegins when initiatedby an SPI master.Thebytefrom theSPI masterbeginsshiftinginon theslaveMOSI pin under thecontrolofthemasterserialclock(drivenontoSCLK). As thebyteshiftsinon theMOSI pin,a byteshiftsouton theMISO pintothemastershiftregister. Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ).

5.6.7.3 Power Supply

The TAS2521 integratesa largeamount ofdigitaland analogfunctionality,and each oftheseblockscan be powered separatelytoenablethesystem toselectappropriatepower suppliesfordesiredperformance and power consumption.The devicehas separatepower domains fordigitalIO,digitalcore,analogcore, analoginput,headphone driver,and speakerdrivers.Ifdesired,allofthesupplies(exceptforthesupplies forspeakerdrivers,whichcan directlyconnecttothebattery)can be connectedtogetherand be supplied from one sourceinthe range of 1.65 to 1.95V.Individually,the IOVDD voltagecan be suppliedinthe rangeof1.1V to3.6V.For improvedpower efficiency,thedigitalcorepower supplycan rangefrom1.26V to 1.95V.The analogcore supplycan eitherbe derivedfrom the internalLDO acceptingan SPKVDD voltageintherangeof2.7V to5.5V,ortheAVDD pincan directlybe drivenwitha voltageintherangeof Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ).

5.6.7.4 Device SpecialFunctions

• Interruptgeneration
• Flexiblepinmultiplexing Formore detailedinformationsee theTAS2521 ApplicationReferenceGuide (SLAU456 ). 5.6.7.5 miniDSP The TAS2521 featuresa miniDSP core which istightlycoupledto the DAC. The fullyprogrammable algorithmsfortheminiDSP must be loadedintothedeviceafterpower up.The miniDSP has directaccess tothedigitalaudiostream,offeringthepossibilityforadvanced,verylow-group-delayDSP algorithms.The miniDSP has 512 programmable instructions,896 data memory locations,and 512 programmable coefficients(intheadaptivemode, each bank has 256 programmablecoefficients).

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www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 5.6.7.5.1Software Softwaredevelopment forthe TAS2521 is supportedthroughTI'scomprehensivePurePath™ Studio softwaredevelopmentenvironment,a powerful,easy-to-usetooldesignedspecificallytosimplifysoftware developmenton Texas InstrumentsminiDSP audio platforms.The graphicaldevelopmentenvironment consistsofa libraryofcommon audiofunctionsthatcan be draggedand droppedintoan audiosignalflow and graphicallyconnectedtogether.The DSP code can thenbe assembled fromthegraphicalsignalflow withtheclickofa mouse. See theTAS2521 productfolderon www.ti.comtolearnmore aboutPurePath Studioand thelateststatuson available,ready-to-useDSP algorithms. Copyright© 2013,Texas InstrumentsIncorporated ApplicationOverview 25 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

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6 RegisterMap

6.1 RegisterMap Summary

Table6-1.Summary ofRegisterMap Decimal Hex DESCRIPTION 0 0 0x00 0x00 Page SelectRegister 0 1 0x00 0x01 SoftwareResetRegister 0 2 -3 0x00 0x02 -0x03 ReservedRegisters 0 4 0x00 0x04 ClockSettingRegister1,Multiplexers 0 5 0x00 0x05 ClockSettingRegister2,PLL P and R Values 0 6 0x00 0x06 ClockSettingRegister3,PLL J Values 0 7 0x00 0x07 ClockSettingRegister4,PLL D Values(MSB) 0 8 0x00 0x08 ClockSettingRegister5,PLL D Values(LSB) 0 9 -10 0x00 0x09 -0x0A ReservedRegisters 0 11 0x00 0x0B ClockSettingRegister6,NDAC Values 0 12 0x00 0x0C ClockSettingRegister7,MDAC Values 0 13 0x00 0x0D DAC OSR SettingRegister1,MSB Value 0 14 0x00 0x0E DAC OSR SettingRegister2,LSB Value 0 15 0x00 0x0F miniDSP_D InstructionControlRegister1 0 16 0x00 0x10 miniDSP_D InstructionControlRegister2 0 17 0x00 0x11 miniDSP_D InterpolationFactorSettingRegister 0 18 -24 0x00 0x12 -0x18 ReservedRegisters 0 25 0x00 0x19 ClockSettingRegister10,Multiplexers 0 26 0x00 0x1A ClockSettingRegister11,CLKOUT M dividervalue 0 27 0x00 0x1B AudioInterfaceSettingRegister1 0 28 0x00 0x1C AudioInterfaceSettingRegister2,Data offsetsetting 0 29 0x00 0x1D AudioInterfaceSettingRegister3 0 30 0x00 0x1E ClockSettingRegister12,BCLK N Divider 0 31 0x00 0x1F AudioInterfaceSettingRegister4,SecondaryAudioInterface 0 32 0x00 0x20 AudioInterfaceSettingRegister5 0 33 0x00 0x21 AudioInterfaceSettingRegister6 0 34 0x00 0x22 ReservedRegister 0 35 -36 0x00 0x23 -0x24 ReservedRegisters 0 37 0x00 0x25 DAC FlagRegister1 0 38 0x00 0x26 DAC FlagRegister2 0 39-41 0x00 0x27-0x29 ReservedRegisters 0 42 0x00 0x2A StickyFlagRegister1 0 43 0x00 0x2B InterruptFlagRegister1 0 44 0x00 0x2C StickyFlagRegister2 0 45 0x00 0x2D ReservedRegister 0 46 0x00 0x2E InterruptFlagRegister2 0 47 0x00 0x2F ReservedRegister 0 48 0x00 0x30 INT1 InterruptControlRegister 0 49 0x00 0x31 INT2 InterruptControlRegister 0 50-51 0x00 0x32-0x33 ReservedRegisters 0 52 0x00 0x34 GPIO/DOUT ControlRegister 0 53 0x00 0x35 DOUT FunctionControlRegister

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www.ti.com SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 Table6-1.Summary ofRegisterMap (continued) Decimal Hex DESCRIPTION 0 54 0x00 0x36 DIN FunctionControlRegister 0 55 0x00 0x37 MISO FunctionControlRegister 0 56 0x00 0x38 SCLK/DMDIN2 FunctionControlRegister 0 57-59 0x00 0x39-0x3B ReservedRegisters 0 60 0x00 0x3C DAC InstructionSet 0 61 0x00 0x3D ReservedRegisters 0 62 0x00 0x3E miniDSP_D ConfigurationRegister 0 63 0x00 0x3F DAC ChannelSetupRegister1 0 64 0x00 0x40 DAC ChannelSetupRegister2 0 65 0x00 0x41 DAC ChannelDigitalVolume ControlRegister 0 66 -80 0x00 0x42 -0x50 ReservedRegisters 0 81 0x00 0x51 Dig_MicControlRegister 0 82 -127 0x00 0x52 -0x7F ReservedRegisters 1 0 0x01 0x00 Page SelectRegister 1 1 0x01 0x01 REF, POR and LDO BGAP ControlRegister 1 2 0x01 0x02 LDO ControlRegister 1 3 0x01 0x03 PlaybackConfigurationRegister1 1 4 -7 0x01 0x04 -0x07 ReservedRegisters 1 8 0x01 0x08 DAC PGA ControlRegister 1 9 0x01 0x09 OutputDrivers,AINL,AINR, ControlRegister 1 10 0x01 0x0A Common Mode ControlRegister 1 11 0x01 0x0B HP Over CurrentProtectionConfigurationRegister 1 12 0x01 0x0C HP RoutingSelectionRegister 1 13 -15 0x01 0x0D -0x0F ReservedRegisters 1 16 0x01 0x10 HP DriverGain SettingRegister 1 17 -19 0x01 0x11 -0x13 HPR DriverGain SettingRegister 1 20 0x01 0x14 Headphone DriverStartupControlRegister 1 21 0x01 0x15 ReservedRegister 1 22 0x01 0x16 HP Volume ControlRegister 1 23 0x01 0x17 ReservedRegister 1 24 0x01 0x18 AINL Volume ControlRegister 1 25 0x01 0x19 AINR Volume ControlRegister 1 26 -44 0x01 0x1A -0x2C ReservedRegisters 1 45 0x01 0x2D SpeakerAmplifierControl1 1 46 0x01 0x2E SpeakerVolume ControlRegister 1 47 0x01 0x2F ReservedRegister 1 48 0x01 0x30 SpeakerAmplifierVolume Control2 1 49 -62 0x01 0x31 -0x3E RightMICPGA PositiveTerminalInputRoutingConfigurationRegister 1 64 -121 0x01 0x40 -0x79 ReservedRegisters 1 122 0x01 0x7A ReferencePower Up Delay 1 123 -127 0x01 0x7B -0x7F ReservedRegisters 2 -43 0 -127 0x02 -0x2B 0x00 -0x7F ReservedRegisters 44 0 0x2C 0x00 Page SelectRegister 44 1 0x2C 0x01 DAC AdaptiveFilterConfigurationRegister 44 2 -7 0x2C 0x02 -0x07 Reserved 44 8 -127 0x2C 0x08 -0x7F DAC CoefficientsBuffer-AC(0:29) Copyright© 2013,Texas InstrumentsIncorporated RegisterMap 27 SubmitDocumentationFeedback ProductFolderLinks:TAS2521

SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com Table6-1.Summary ofRegisterMap (continued) Decimal Hex DESCRIPTION 45 -52 0 0x2D-0x34 0x00 Page SelectRegister 45 -52 1 -7 0x2D-0x34 0x01 -0x07 Reserved. 45 -52 8 -127 0x2D-0x34 0x08 -0x7F DAC CoefficientsBuffer-AC(30:255) 53 -61 0 -127 0x35 -0x3D 0x00 -0x7F ReservedRegisters 62 -70 0 0x3E-0x46 0x00 Page SelectRegister 62 -70 1 -7 0x3E-0x46 0x01 -0x07 ReservedRegisters 62 -70 8 -127 0x3E-0x46 0x08 -0x7F DAC CoefficientsBuffer-BC(0:255) 71 -151 0 -127 0x47 -0x97 0x00 -0x7F ReservedRegisters 152 -169 0 0x98-0xA9 0x00 Page SelectRegister 152 -169 1 -7 0x98-0xA9 0x01 -0x07 ReservedRegisters 152 -169 8 -127 0x98-0xA9 0x08 -0x7F miniDSP_D Instructions 170 -255 0 -127 0xAA -0x7F 0x00 -0x7F ReservedRegisters spacer RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from Original(February2013)toRevisionA Page

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www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TAS2521IRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TAS 2521 TAS2521IRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TAS 2521 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS2521IRGET VQFN RGE 24 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 Pack Materials-Page 2

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