TAS2505IRGETG4.A

TAS2505 TI | Alldatasheet

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Technical content

TAS2505 2.6W Digital/Analog Input Class-D Speaker Amplifier With Audio Processing

1 Features

• Mono class-D BTL speaker amplifier – 2.6W at 10% THD_N (4Ω, 5.5V) – 1.7W at 10% THD+N (8Ω, 5.5V)
• Supports both digital and analog input
• Single supply 2.7V to 5.5V
• Load diagnostic functions: – Output-to-GND Short – Terminal-to-terminal short – Output-to-power short – Over temperature – Input DC
• Supports 9kHz to 96kHz sample rates
• Two single-ended inputs with output mixing and level control
• Embedded power-on-reset
• Programmable digital audio processing: – Bass boost – Treble – EQ (up to 6 biquads)
• I2S, Left-justified, right-justified, DSP, and TDM audio interfaces
• I2C and SPI Control With Auto-Increment
• 24-Pin, VQFN package

2 Applications

• Instrument Cluster
• Automotive Emergency Call (eCall)
• Telematics

3 Description

The TAS2505 is a mono Class-D speaker amp that supports both Digital and Analog inputs. The device is designed for automotive instrument cluster, emergency call (eCall), and telematics applications. Direct I 2S input removes the need for an external DAC in the audio signal path. In addition to integration, the device features programmable audio processing. The onboard DSP supports bass boost, treble, and EQ (up to 6 biquads). An on-chip PLL provides the high-speed clock needed by the DSP. The volume level is register controlled. Device Information (1) PART NUMBER PACKAGE PACKAGE SIZE (2) TAS2505 VQFN (24) 4.00mm × 4.00mm TAS2505A-Q1 VQFN (24) 4.00mm × 4.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. DIN BCLK WCLK MCLK SPKVSS AVSS SCL/SSZ SDA/MOSI GPIO/DOUT DVSS AINL AINR SPKP SPKM HPOUT RST MISO SPI_SEL SCLK S S SPKVDD AVDD DAC Signal Proc.Data Interface SPI/I2C Control Block PLL Interrupt ControlPrimary I2S Interface Pin Muxing / Clock Routing POR Supplies Mono S-D DAC DVDD IOVDD Secondary I2S Interface Dig Vol 6 dB to +24 dB (6 dB steps) -6 dB to +29 dB and Mute (1 dB steps) 0 dB to -78 dB and Mute (Min 0.5 dB steps) 0 dB to -78 dB and Mute (Min 0.5 dB steps) 0 dB to -78 dB and Mute (Min 0.5 dB steps) Simplified Block Diagram TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10.3 Receiving Notification of Documentation Updates..26

12 Mechanical, Packaging, and Orderable

SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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4 Pin Configuration and Functions

SPI_SEL LDO_SEL AINL A VSS HPOUT SPKM SPKVSS A VDD WCLK SPKVDD SPKP BCLK MCLK MISO SDA/MOSI DIN GPIO/DOUT IOVDD SCL/SSZ DVSS SCLK DVDD 23 2124 22 20 19 1 11098 127 Figure 4-1. RGE Package 24-Pin VQFN Top View Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME

1 SPI_SEL I Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode)

2 RST I Reset for logic, state machines, and digital filters; asserted LOW.

3 AINL I Analog single-ended line left input

4 AINR I Analog single-ended line right input

5 NC O No Connect (Leave unconnected)

6 AVSS GND Analog Ground, 0V

7 AVDD PWR Analog Core Supply Voltage, 1.5V to 1.95V 8 LDO_SEL I Connect to ground.

9 SPKM O Class-D speaker driver inverting output

10 SPKVDD PWR Class-D speaker driver power supply

11 SPKVSS PWR Class-D speaker driver power supply ground supply

12 SPKP O Class-D speaker driver noninverting output

13 DIN I Audio Serial Data Bus Input Data

14 WCLK I/O Audio Serial Data Bus Word Clock

15 BCLK I/O Audio Serial Data Bus Bit Clock

16 MCLK I Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)

17 MISO O SPI Serial Data Output

18 GPIO/DOUT I/O/Z GPIO / Audio Serial Bus Output

19 SCL/SSZ I Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state

20 SDA/MOSI I Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.

21 SCLK I Serial clock for SPI interface

22 IOVDD PWR I/O Power Supply, 1.1V to 3.6V 23 DVDD PWR Digital Power Supply, 1.65V to 1.95V

24 DVSS GND Digital Ground, 0V

(1) I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TAS2505

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT AVDD to AVSS –0.3 2.2 V DVDD to DVSS –0.3 2.2 V SPKVDD to SPKVSS –0.3 6 V IOVDD to IOVSS –0.3 3.9 V Digital input voltage IOVSS – 0.3 IOVDD + 0.3 V Analog input voltage AVSS – 0.3 AVDD + 0.3 V Operating temperature –40 85 °C Junction temperature, TJ Max 105 °C Power dissipation for VQFN package (with thermal pad soldered to board) (TJ Max – TA) / θJA W Storage temperature, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±500 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD(2) Power-supply voltage Referenced to AVSS(1) 1.5 1.8 1.95 V DVDD Referenced to DVSS (1) 1.65 1.8 1.95 SPKVDD(2) Referenced to SPKVSS (1) 2.7 5.5 IOVDD Referenced to IOVSS (1) 1.1 1.8 3.6 Speaker impedance Load applied across class-D output pins (BTL) 4 Ω VI Analog audio full-scale input voltage AVDD = 1.8V, single-ended 0.5 VRMS MCLK(3) Master clock frequency IOVDD = DVDD = 1.8V 50 MHz SCL SCL clock frequency 400 kHz TA Operating free-air temperature –40 85 °C (1) All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS. (2) To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level. (3) The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.

5.4 Thermal Information

THERMAL METRIC(1) TAS2505 UNITRGE (QFN)

24 PINS

θJA Junction-to-ambient thermal resistance 32.2 °C/W θJCtop Junction-to-case (top) thermal resistance 30 °C/W TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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THERMAL METRIC(1) TAS2505 UNITRGE (QFN) θJB Junction-to-board thermal resistance 9.2 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 9.2 °C/W θJCbot Junction-to-case (bottom) thermal resistance 2.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

At 25°C, AVDD = 1.8V, IOVDD = 1.8V, SPKVDD = 3.6V, DVDD = 1.8V, fS (audio) = 48kHz, CODEC_CLKIN = 256 × fS, PLL = Off PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL OSCILLATOR—RC_CLK Oscillator frequency 8.48 MHz DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS See TAS2505 Application Reference Guide (SLAU472) for DAC interpolation filter characteristics. DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 4Ω (DIFFERENTIAL) ICN Idle channel noise BTL measurement, class-D gain = 6dB, Measured as idle-channel noise, A-weighted(2) (1) 37 μVms Output voltage BTL measurement, class-D gain = 6dB, –3dBFS input 1.4 Vrms THD+N Total harmonic distortion + noise BTL measurement, DAC input = –6dBFS, class-D gain = 6dB –73.9 dB PSRR Power-supply rejection ratio BTL measurement, ripple on SPKVDD = 200mVPP at 1kHz 55 dB Mute attenuation Mute 103 dB PO Maximum output power SPKVDD = 3.6V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 10% 1.1 W SPKVDD = 4.2V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 10% 1.4 SPKVDD = 3.6V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 1% 0.8 SPKVDD = 4.2V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 1% 1.1 SPKVDD = 5.5V, BTL measurement, CM = 0.9V, class-D gain = 18dB 2 DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 8Ω (DIFFERENTIAL) ICN Idle channel noise BTL measurement, class-D gain = 6dB, measured as idle-channel noise, A-weighted(2) (1) 35.2 μVms Output voltage BTL measurement, class-D gain = 6dB, –3dBFS input 1.4 Vrms THD+N Total harmonic distortion + noise BTL measurement, DAC input = –6dBFS, class-D gain = 6dB –73.6 dB www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TAS2505

At 25°C, AVDD = 1.8V, IOVDD = 1.8V, SPKVDD = 3.6V, DVDD = 1.8V, fS (audio) = 48kHz, CODEC_CLKIN = 256 × fS, PLL = Off PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PO Maximum output power SPKVDD = 3.6V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 10% 0.7 W SPKVDD = 4.2V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 10% 1 SPKVDD = 5.5V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 10% 1.7 SPKVDD = 3.6V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 1% 0.5 SPKVDD = 4.2V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 1% 0.8 SPKVDD = 5.5V, BTL measurement, CM = 0.9V, class-D gain = 18dB, THD = 1% 1.3 ANALOG BYPASS TO CLASS-D SPEAKER AMPLIFIER Device setup BTL measurement, driver gain = 6dB, load = 4Ω (differential), 50pF, input signal frequency fi = 1KHz Voltage gain Input common-mode = 0.9V 4 V/V Gain error –1dBFS (446mVrms), 1kHz input signal ±0.7 dB ICN Idle channel noise Idle channel, IN1L and IN1R ac-shorted to ground, measured as idle-channel noise, A-weighted(2) (1) 32.6 μVms THD+N Total harmonic distortion + noise –1dBFS (446mVrms), 1kHz input signal –73.7 dB SHUTDOWN POWER CONSUMPTION Device setup Power down POR, /RST held low, AVDD = 1.8V, IOVDD = 1.8V, SPKVDD = 4.2V, DVDD = 1.8V I(AVDD) 1.32 µA I(DVDD) 0.04 µA I(IOVDD) 0.68 µA I(SPKVDD) 2.24 µA DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level IIH = 5μA, IOVDD ≥ 1.6V 0.7 × IOVDD V IIH = 5μA, IOVDD < 1.6V IOVDD VIL IIL = 5μA, IOVDD ≥ 1.6V –0.3 0.3 × IOVDD V IIL = 5μA, IOVDD < 1.6V 0 VOH IOH = 2 TTL loads 0.8 × IOVDD V VOL IOL = 2 TTL loads 0.25 V Capacitive load 10 pF (1) All performance measurements were done with a 20kHz low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. (2) Ratio of output level with 1kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer.

5.6 I2S/LJF/RJF Timing in Master Mode

All specifications at 25°C, DVDD = 1.8V(1) PARAMETER IOVDD = 1.8V IOVDD = 3.3V UNIT MIN MAX MIN MAX td(WS) WCLK delay 45 45 ns TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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All specifications at 25°C, DVDD = 1.8V(1) PARAMETER IOVDD = 1.8V IOVDD = 3.3V UNIT MIN MAX MIN MAX ts(DI) DIN setup 8 6 ns th(DI) DIN hold 8 6 ns tr Rise time 25 10 ns tf Fall time 25 10 ns (1) ll timing specifications are measured at characterization but not tested at final test.

5.7 I2S/LJF/RJF Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8V(1) PARAMETER IOVDD = 1.8V IOVDD = 3.3V UNIT MIN MAX MIN MAX tH(BCLK) BCLK high period 35 35 ns tL(BCLK) BCLK low period 35 35 ns ts(WS) WCLK setup 8 6 ns th(WS) WCLK hold 8 6 ns ts(DI) DIN setup 8 6 ns th(DI) DIN hold 8 6 ns tr Rise time 4 4 ns tf Fall time 4 4 ns (1) All timing specifications are measured at characterization but not tested at final test.

5.8 DSP Timing in Master Mode

All specifications at 25°C, DVDD = 1.8V(1) PARAMETER IOVDD = 1.8V IOVDD = 3.3V UNIT MIN MAX MIN MAX td(WS) WCLK delay 45 45 ns ts(DI) DIN setup 8 6 ns th(DI) DIN hold 8 6 ns tr Rise time 25 10 ns tf Fall time 25 10 ns (1) All timing specifications are measured at characterization but not tested at final test.

5.9 DSP Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8V(1) PARAMETER IOVDD = 1.8V IOVDD = 3.3V UNIT MIN MAX MIN MAX tH(BCLK) BCLK high period 35 35 ns tL(BCLK) BCLK low period 35 35 ns ts(WS) WCLK setup 8 8 ns th(WS) WCLK hold 8 8 ns ts(DI) DIN setup 8 8 ns th(DI) DIN hold 8 8 ns tr Rise time 4 4 ns tf Fall time 4 4 ns (1) All timing specifications are measured at characterization but not tested at final test. www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TAS2505

5.10 I2C Interface Timing

All specifications at 25°C, DVDD = 1.8V(1) PARAMETER STANDARD MODE FAST MODE UNIT MIN TYP MAX MIN TYP MAX fSCL SCL clock frequency 0 100 0 400 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 0.8 μs tLOW LOW period of the SCL clock 4.7 1.3 μs tHIGH HIGH period of the SCL clock 4 0.6 μs tSU;STA Setup time for a repeated START condition 4.7 0.8 μs tHD;DAT Data hold time for I2C bus devices 0 3.45 0 0.9 μs tSU;DAT Data setup time 250 100 ns tr SDA and SCL rise time 1000 20 + 0.1 Cb 300 ns tf SDA and SCL fall time 300 20 + 0.1 Cb 300 ns tSU;STO Set-up time for STOP condition 4 0.8 μs tBUF Bus free time between a STOP and START condition 4.7 1.3 μs Cb Capacitive load for each bus line 400 400 pF (1) All timing specifications are measured at characterization but not tested at final test.

5.11 SPI Interface Timing

At 25°C, DVDD = 1.8V PARAMETER TEST CONDITION IOVDD=1.8V IOVDD=3.3V UNIT MIN TYP MAX MIN TYP MAX tsck SCLK period (1) 100 50 ns tsckh SCLK pulse width High 50 25 ns tsckl SCLK pulse width Low 50 25 ns tlead Enable lead time 30 20 ns tlag Enable lag time 30 20 ns td Sequential transfer delay 40 20 ns ta Slave DOUT access time 40 40 ns tdis Slave DOUT disable time 40 40 ns tsu DIN data setup time 15 15 ns thi DIN data hold time 15 10 ns tv;DOUT DOUT data valid time 25 18 ns tr SCLK rise time 4 4 ns tf SCLK fall time 4 4 ns (1) These parameters are based on characterization and are not tested in production. TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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t (WS)h t (WS)h t (BCLK)L tr tf t (DI)St (BCLK)H t (DI)h t (WS)S t (WS)S Figure 5-4. DSP Timing in Slave Mode STO ST A ST A STO SDA SCL tBUF tLOW tSU;ST A tHIGH tHD;ST A tr tHD;ST A tHD;DA T tSU;DA T tSU;STO tf T0295-02 Figure 5-5. I2C Interface Timing ttdS ta MSB OUT BIT 6 . . . 1 LSB OUT tscktLead tLag tsckh tsckl trtf tv(DOUT) tdis MSB IN BIT 6 . . . 1 LSB IN th(DIN)t su SS SCLK MISO MOSI Figure 5-6. SPI Interface Timing Diagram TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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5.12 Typical Characteristics

5.12.1 Class D Speaker Driver Performance

±180 ±160 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 4000 8000 12000 16000 20000 Amlitude (dB) Frequency (Hz) C001 (4Ω Load) Figure 5-7. DAC To Speaker Amplitude at 0dBFS vs Frequency ±180 ±160 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 4000 8000 12000 16000 20000 Amplitude (dB) Frequency (Hz) C002 (4Ω Load) Figure 5-8. AINL To Speaker FFT Amplitude at 0dBFS vs Frequency 0.01 0.1 100 0 0.5 1 1.5 2 2.5 3 THDN (%) Output Power (W) Gain = 6 dB Gain = 12 dB Gain = 18 dB Gain = 24 dB C003 (SPKVDD = 5.5V) Figure 5-9. Total Harmonic Distortion + Noise vs 4Ω Speaker Power 0.01 0.10 1.00 10.00 100.00 0 0.5 1 1.5 2 2.5 3 THDN (%) Output Power (W) Series1 Series2 Series4 Series5 Series6 Series7 C004 SPKVDD=2.7V SPKVDD=3V SPKVDD=3.3V SPKVDD=3.6V SPKVDD=4.2V SPKVDD=5.5V (Gain = 18dB) Figure 5-10. Total Harmonic Distortion + Noise + NOISE vs 4Ω Speaker Power 0.01 0.10 1.00 10.00 100.00 0 0.5 1 1.5 2 2.5 THDN (%) Output Power (W) Series1 Series2 Series4 Series5 C005 Gain = 6 dB Gain = 12 dB Gain = 18 dB Gain = 24 dB (SPKVDD = 5.5V) Figure 5-11. Total Harmonic Distortion + Noise + NOISE vs 8Ω Speaker Power 0.01 0.1 100 0 0.5 1 1.5 2 2.5 THDN (%) Output Power (W) Series1 Series2 Series4 Series5 Series6 Series7 C006 SPKVDD = 2.7 V SPKVDD = 3 V SPKVDD = 3.3 V SPKVDD = 3.6 V SPKVDD = 4.2 V SPKVDD = 5.5 V (Gain = 18dB) Figure 5-12. Total Harmonic Distortion + Noise + NOISE vs 8Ω Speaker Power www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TAS2505

0 200 400 600 800 1000 1200 1400 1600 1800 Efficiency (%) Output Power (mWatt) SPKVDD = 2.7 V SPKVDD = 3 V SPKVDD = 3.3 V SPKVDD = 3.6 V SPKVDD = 4.2 V SPKVDD = 5.5 V C007 (Gain = 18dB, Load = 4Ω) Figure 5-13. Total Power Consumption vs Output Power Consumption

5.12.2 HP Driver Performance

±180 ±160 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 4000 8000 12000 16000 20000 Amplitude ( dB) Frequency (Hz) C008 0dBFS (16Ω Load) Figure 5-14. DAC TO HP FFT Amplitude at 0dBFS vs Frequency ±180 ±160 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 4000 8000 12000 16000 20000 Amplitude ( dB) Frequency (Hz) C008 0dBFS (16Ω Load) Figure 5-15. AINL TO HP FFT Amplitude at 0dBFS vs Frequency ±90 ±80 ±70 ±60 ±50 ±40 ±30 ±20 ±10 THDN (%) Output Power (mW) CM=0.75V,AVDD=1.5V CM=0.75V,AVDD=1.8V CM=0.75V,AVDD=1.95V CM=0.9V,AVDD=1.8V CM=0.9V,AVDD=1.95V C010 (Gain = 9dB) Figure 5-16. Total Harmonic Distortion + Noise vs HP Power ±90 ±80 ±70 ±60 ±50 ±40 ±30 ±20 ±10 THDN (dB) Output Power (mW) Series1 Series2 Series4 Series5 Series6 C011 CM=0.75V, AVDD=1.5V CM=0.75V, AVDD=1.8V CM=0.75V, AVDD=1.95V CM=0.9V, AVDD=1.8V CM=0.9V, AVDD=1.95V (Gain = 32dB) Figure 5-17. Total Harmonic Distortion + Noise vs HP Power TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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6 Parameter Measurement Information

All parameters are measured according to the conditions described in the Section 5 section. www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TAS2505

7 Detailed Description

7.1 Overview

TAS2505 is a low power analog and digital input class-D speaker amplifier. It supports 24-bit digital I2S data for mono playback. This device is able to drive a speaker up to 4 Ω and programmable digital-signal processing block. The programmable digital-signal processing block can support Bass boost, treble or EQ functions. The volume level can be controlled by register control. The device can be controlled through I 2C or SPI bus. The device also includes two analog inputs for mixing in speaker path.

7.2 Functional Block Diagram

SPI_SEL SCLK S S SPKVDD AVDD DAC Signal Proc.Data Interface SPI/I2C Control Block PLL Interrupt ControlPrimary I2S Interface Pin Muxing / Clock Routing POR Supplies Mono S-D DAC DVDD IOVDD Secondary I2S Interface Dig Vol 6 dB to +24 dB (6 dB steps) -6 dB to +29 dB and Mute (1 dB steps) 0 dB to -78 dB and Mute (Min 0.5 dB steps) 0 dB to -78 dB and Mute (Min 0.5 dB steps) 0 dB to -78 dB and Mute (Min 0.5 dB steps)

7.3 Feature Description

7.3.1 Audio Analog I/O

The TAS2505 features a mono audio DAC. The TAS2505 can drive a speaker up to 4Ω impedance.

7.3.2 Audio DAC and Audio Analog Outputs

The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital delta- sigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include mono class-D speaker TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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outputs. Because the TAS2505 contains a mono DAC, it inputs the mono data from the left channel, the right channel, or a mix of the left and right channels as [(L + R) ÷ 2], selected by page 0, register 63, bits D5–D4. For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

7.3.3 DAC

The TAS2505 mono audio DAC supports data rates from 8kHz to 192kHz. The audio channel of the mono DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, a multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and observed in the signal images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates and optimize power dissipation and performance, the TAS2505 allows the system designer to program the oversampling rates over a wide range from 1 to 1024 by configuring page 0, register 13, and page 0 / register 14. The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data rates. The TAS2505 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on the required frequency response, group delay, and sampling rate. The DAC path of the TAS2505 features many options for signal conditioning and signal routing:

• Digital volume control with a range of –63.5 to +24dB
• Mute function In addition to the standard set of DAC features the TAS2505 also offers the following special features:
• Digital auto-mute
• Adaptive filter mode

7.3.4 POR

TAS2505 has a POR (Power-On-Reset) function. This function insures that all registers are automatically set to defaults when a proper power up sequence is executed. For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

7.3.5 CLOCK Generation and PLL

The TAS2505 supports a wide range of options for generating clocks for the DAC sections as well as interface and other control blocks. The clocks for the DAC require a source reference clock. This clock can be provided on a variety of device pins, such as the MCLK, BCLK, or GPIO pins. The source reference clock for the codec can be chosen by programming the CODEC_CLKIN value on page 0, register 4, bits D1–D0. The CODEC_CLKIN can then be routed through highly-flexible clock dividers shown in Figure 2 through 7 in the TAS2505 Application Reference Guide to generate the various clocks required for the DAC and the Digital Effects section also found in the TAS2505 Application Reference Guide (SLAU472). In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO, the TAS2505 also provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the TAS2505 provides several programmable clock dividers to help achieve a variety of sampling rates for the DAC and clocks for the Digital Effects sections. For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

7.4 Device Functional Modes

7.4.1 Digital Pins

Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a default function, and also can be reprogrammed to cover alternative functions for various applications. www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TAS2505

The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending on the state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I 2C or SPI protocol. Other digital IO pins can be configured for various functions through register control. An overview of available functionality is given in Section 7.4.3.

7.4.2 Analog Pins

Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are powered down by default. The blocks can be powered up with fine granularity according to the application needs.

7.4.3 Multifunction Pins

Table 7-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO). Table 7-1. Multifunction Pin Assignments 1 2 3 4 5 6 7 PIN FUNCTION MCLK BCLK WCLK DIN GPIO /DOUT SCLK MISO A PLL Input S(2) S(3) E S(4) B Codec Clock Input S(2),D(5) S(3) S(4) C I2S BCLK input S(3),D D I2S BCLK output E(1) E I2S WCLK input E, D F I2S WCLK output E G I2S DIN E, D I General-Purpose Output I E I General-Purpose Output II E J General-Purpose Input I E J General-Purpose Input II E J General-Purpose Input III E K INT1 output E E L INT2 output E E M Secondary I2S BCLK input E E N Secondary I2S WCLK input E E O Secondary I2S DIN E E P Secondary I2S BCLK OUT E E Q Secondary I2S WCLK OUT E E R Secondary I2S DOUT E S Aux Clock Output E E (1) E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.) (2) S(1): The MCLK pin can drive the PLL and Codec Clock inputs simultaneously. (3) S(2): The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously. (4) S(3): The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously. (5) D: Default Function

7.4.4 Analog Signals

The TAS2505 analog signals consist of:

• Analog inputs AINR and AINL, which can be used to pass-through or mix analog signals to output stages TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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• Analog outputs class-D speaker driver providing output capability for the DAC, AINR, AINL, or a mix of the three

7.4.4.1 Analog Inputs AINL and AINR

AINL (pin 3 or C2) and AINR (pin 4 or B2) are inputs to Mixer P and Mixer M along with the DAC output. Also AINL and AINR can be configured inputs to HP driver. Page1 / register 12 provides control signals for determining the signals routed through Mixer P, Mixer M and HP driver. Input of Mixer P can be attenuated by Page1 / register 24, input of Mixer M can be attenuated by Page1 / register 25 and input of HP driver can be attenuated by Page1 / register 22. Also AINL and AINR can be configured to a monaural differential input with use Mixer P and Mixer M by Page1 / register 12 setting. For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

7.4.5 DAC Processing Blocks — Overview

The TAS2505 implements signal-processing capabilities and interpolation filtering through processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they may use and which interpolation filter is applied. The choices among these processing blocks allows the system designer to balance power conservation and signal-processing flexibility. Table 7-2 gives an overview of all available processing blocks of the DAC channel and their properties. The resource-class column gives an approximate indication of power consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog power consumption of the drivers (AVDD) may differ. The signal-processing blocks available are:

• First-order IIR
• Scalable number of biquad filters The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal-processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients. Table 7-2. Overview – DAC Predefined Processing Blocks PROCESSING BLOCK NO. INTERPOLATION FILTER CHANNEL FIRST-ORDER IIR AVAILABLE NUMBER OF BIQUADS RESOURCE CLASS PRB_P1 A Mono Yes 6 6 PRB_P2 A Mono No 3 4 PRB_P3 B Mono Yes 6 4 For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

7.4.6 Digital Mixing and Routing

The TAS2505 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the digital audio data. The first mixer or multiplexer can be used to select input data for the mono DAC from left channel, right channel, or (left channel + right channel) / 2 mixing. This digital routing can be configured by writing to page 0, register 63, bits D5–D4.

7.4.7 Analog Audio Routing

The TAS2505 has the capability to route the DAC output to the speaker output. If desirable, both output drivers can be operated at the same time while playing at different volume levels. The TAS2505 provides various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain. All analog outputs other than the selected ones can be powered down for optimal power consumption. For more detailed information see the TAS2505 Application Reference Guide (SLAU472). www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TAS2505

7.4.8 Digital Audio and Control Interface

7.4.8.1 Digital Audio Interface

Audio data is transferred between the host processor and the TAS2505 via the digital audio data serial interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data options, support for I 2S or PCM protocols, programmable data-length options, a TDM mode for multichannel operation, flexible master or slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly. The audio bus of the TAS2505 can be configured for left- or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0, register 27, bits D5–D4. In addition, the word clock and bit clock can be independently configured in either master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected DAC sampling frequencies. For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

7.4.8.2 Control Interface

The TAS2505 control interface supports SPI or I 2C communication protocols, with the protocol selectable using the SPI_SEL pin. For SPI, SPI_SEL should be tied high; for I 2C, SPI_SEL should be tied low. TI does not recommend changing the state of SPI_SEL during device operation.

7.4.8.2.1 I2C Control Mode

The TAS2505 supports the I 2C control protocol, and will respond to the I 2C address of 0011 000. I 2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I 2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

7.4.8.2.2 SPI Digital Interface

In the SPI control mode, the TAS2505 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO, SDA/ MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TAS2505) depend on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

7.4.8.3 Device Special Functions

• Interrupt generation
• Flexible pin multiplexing For more detailed information see the TAS2505 Application Reference Guide (SLAU472). TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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8 Register Map

Table 8-1. Summary of Register Map Decimal Hex DESCRIPTION 0 0 0x00 0x00 Page Select Register 0 1 0x00 0x01 Software Reset Register 0 2 - 3 0x00 0x02 - 0x03 Reserved Registers 0 4 0x00 0x04 Clock Setting Register 1, Multiplexers 0 5 0x00 0x05 Clock Setting Register 2, PLL P and R Values 0 6 0x00 0x06 Clock Setting Register 3, PLL J Values 0 7 0x00 0x07 Clock Setting Register 4, PLL D Values (MSB) 0 8 0x00 0x08 Clock Setting Register 5, PLL D Values (LSB) 0 9 - 10 0x00 0x09 - 0x0A Reserved Registers 0 11 0x00 0x0B Clock Setting Register 6, NDAC Values 0 12 0x00 0x0C Clock Setting Register 7, MDAC Values 0 13 0x00 0x0D DAC OSR Setting Register 1, MSB Value 0 14 0x00 0x0E DAC OSR Setting Register 2, LSB Value 0 15 - 24 0x00 0x0F - 0x18 Reserved Registers 0 25 0x00 0x19 Clock Setting Register 10, Multiplexers 0 26 0x00 0x1A Clock Setting Register 11, CLKOUT M divider value 0 27 0x00 0x1B Audio Interface Setting Register 1 0 28 0x00 0x1C Audio Interface Setting Register 2, Data offset setting 0 29 0x00 0x1D Audio Interface Setting Register 3 0 30 0x00 0x1E Clock Setting Register 12, BCLK N Divider 0 31 0x00 0x1F Audio Interface Setting Register 4, Secondary Audio Interface 0 32 0x00 0x20 Audio Interface Setting Register 5 0 33 0x00 0x21 Audio Interface Setting Register 6 0 34 0x00 0x22 Reserved Register 0 35 - 36 0x00 0x23 - 0x24 Reserved Registers 0 37 0x00 0x25 DAC Flag Register 1 0 38 0x00 0x26 DAC Flag Register 2 0 39-41 0x00 0x27-0x29 Reserved Registers 0 42 0x00 0x2A Sticky Flag Register 1 0 43 0x00 0x2B Interrupt Flag Register 1 0 44 0x00 0x2C Sticky Flag Register 2 0 45 0x00 0x2D Reserved Register 0 46 0x00 0x2E Interrupt Flag Register 2 0 47 0x00 0x2F Reserved Register 0 48 0x00 0x30 INT1 Interrupt Control Register 0 49 0x00 0x31 INT2 Interrupt Control Register 0 50-51 0x00 0x32-0x33 Reserved Registers 0 52 0x00 0x34 GPIO/DOUT Control Register 0 53 0x00 0x35 DOUT Function Control Register 0 54 0x00 0x36 DIN Function Control Register 0 55 0x00 0x37 MISO Function Control Register 0 56 0x00 0x38 SCLK/DMDIN2 Function Control Register www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TAS2505

Table 8-1. Summary of Register Map (continued) Decimal Hex DESCRIPTION 0 57-59 0x00 0x39-0x3B Reserved Registers 0 60 0x00 0x3C DAC Instruction Set 0 61 - 62 0x00 0x3D -0x3E Reserved Registers 0 63 0x00 0x3F DAC Channel Setup Register 1 0 64 0x00 0x40 DAC Channel Setup Register 2 0 65 0x00 0x41 DAC Channel Digital Volume Control Register 0 66 - 80 0x00 0x42 - 0x50 Reserved Registers 0 81 0x00 0x51 Dig_Mic Control Register 0 82 - 127 0x00 0x52 - 0x7F Reserved Registers 1 0 0x01 0x00 Page Select Register 1 1 0x01 0x01 REF, POR and BGAP Control Register 1 2 0x01 0x02 Reserved Register 1 3 0x01 0x03 Playback Configuration Register 1 1 4 - 7 0x01 0x04 - 0x07 Reserved Registers 1 8 0x01 0x08 DAC PGA Control Register 1 9 0x01 0x09 Output Drivers, AINL, AINR, Control Register 1 10 0x01 0x0A Common Mode Control Register 1 11 0x01 0x0B HP Over Current Protection Configuration Register 1 12 0x01 0x0C HP Routing Selection Register 1 13 - 15 0x01 0x0D - 0x0F Reserved Registers 1 16 0x01 0x10 Reserved Registers 1 17 - 19 0x01 0x11 - 0x13 Reserved Registers 1 20 0x01 0x14 Reserved Registers 1 21 0x01 0x15 Reserved Register 1 22 0x01 0x16 Reserved Registers 1 23 0x01 0x17 Reserved Register 1 24 0x01 0x18 AINL Volume Control Register 1 25 0x01 0x19 AINR Volume Control Register 1 26 - 44 0x01 0x1A - 0x2C Reserved Registers 1 45 0x01 0x2D Speaker Amplifier Control 1 1 46 0x01 0x2E Speaker Volume Control Register 1 47 0x01 0x2F Reserved Register 1 48 0x01 0x30 Speaker Amplifier Volume Control 2 1 49 - 62 0x01 0x31 - 0x3E Right MICPGA Positive Terminal Input Routing Configuration Register 1 64 - 121 0x01 0x40 - 0x79 Reserved Registers 1 122 0x01 0x7A Reference Power Up Delay 1 123 - 127 0x01 0x7B - 0x7F Reserved Registers 2 - 43 0 - 127 0x02 - 0x2B 0x00 - 0x7F Reserved Registers 44 0 0x2C 0x00 Page Select Register 44 1 0x2C 0x01 DAC Adaptive Filter Configuration Register 44 2 - 7 0x2C 0x02 - 0x07 Reserved 44 8 - 127 0x2C 0x08 - 0x7F DAC Coefficients Buffer-A C(0:29) 45 - 52 0 0x2D-0x34 0x00 Page Select Register 45 - 52 1 - 7 0x2D-0x34 0x01 - 0x07 Reserved. TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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Table 8-1. Summary of Register Map (continued) Decimal Hex DESCRIPTION 45 - 52 8 - 127 0x2D-0x34 0x08 - 0x7F DAC Coefficients Buffer-A C(30:255) 53 - 61 0 - 127 0x35 - 0x3D 0x00 - 0x7F Reserved Registers 62 - 70 0 0x3E-0x46 0x00 Page Select Register 62 - 70 1 - 7 0x3E-0x46 0x01 - 0x07 Reserved Registers 62 - 70 8 - 127 0x3E-0x46 0x08 - 0x7F DAC Coefficients Buffer-B C(0:255) 71 - 255 0 - 127 0x47 - 0x7F 0x00 - 0x7F Reserved Registers www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TAS2505

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TAS2505 is a digital or analog input Class-D audio power amplifier. Below are shown different setups that show the features of the TAS2505.

9.2 Typical Applications

9.2.1 Typical Configuration

SPKVSSAVDDAVSS LDO_SEL SPKVDD SCL/SSZ SDA/MOSI GPIO/DOUT RST DVDD DVSS IOVDD IOVSS AINL SPKP SPKM HOST PROCESSOR 0.1PF 22PF SVDD 0.1PF22PF +1.8VA 8-: or 4-: Speaker +1.8VD IOVDD AINR Analog Input TAS2505 HPOUT Headphone jack MISO SPI_SEL SCLK IOVDD 0.1PF 0.1PF 2.7k 2.7k 47PF 0.1PF 0.1 PF10PF 10PF Copyright © 2016, Texas Instruments Incorporated Figure 9-1. Typical Circuit Configuration TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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9.2.1.1 Design Requirements

Table 9-1 shows the design parameters. Table 9-1. Design Parameters PARAMETER EXAMPLE VALUE Audio input Digital Audio (I2S), Analog Audio AINx Speaker 8Ω or 4Ω

9.2.1.2 Detailed Design Procedure

In this application, the device is able to use both digital and analog inputs, working in mono output by summing left and right analog inputs and output from DAC and routing this signal into the speaker output. External 1.8V supply is used to power AVDD and DVDD. IOVDD can be supplied by voltages between 1.1V and 3.6V which lets the system to use conventional 1.8V or 3.3V supplies. The SPKVDD can be connected to voltages between 2.7V and 5.5V, although it is usually supplied by a 5V voltage. Decoupling capacitors should be used at all the supply lines. TI recommends using 0.1µF, 10µF, and 22µF capacitors for a better system performance. Decoupling series capacitors must be used at the analog input. All grounds are tied together; route analog and digital paths are separated to avoid interference.

9.2.1.3 Application Curves

0.01 0.1 100 0 0.5 1 1.5 2 2.5 3 THDN (%) Output Power (W) Gain = 6 dB Gain = 12 dB Gain = 18 dB Gain = 24 dB C003 (SPKVDD = 5.5V) Figure 9-2. Total Harmonic Distortion + Noise vs 4Ω Speaker Power 0.01 0.10 1.00 10.00 100.00 0 0.5 1 1.5 2 2.5 3 THDN (%) Output Power (W) Series1 Series2 Series4 Series5 Series6 Series7 C004 SPKVDD=2.7V SPKVDD=3V SPKVDD=3.3V SPKVDD=3.6V SPKVDD=4.2V SPKVDD=5.5V (Gain = 18dB) Figure 9-3. Total Harmonic Distortion + Noise vs 4Ω Speaker Power www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TAS2505

±90 ±80 ±70 ±60 ±50 ±40 ±30 ±20 ±10 THDN (%) Output Power (mW) CM=0.75V,AVDD=1.5V CM=0.75V,AVDD=1.8V CM=0.75V,AVDD=1.95V CM=0.9V,AVDD=1.8V CM=0.9V,AVDD=1.95V C010 (Gain = 9dB) Figure 9-4. Total Harmonic Distortion + Noise vs HP Power

9.3 Power Supply Recommendations

The TAS2505 integrates a large amount of digital and analog functionality, and each of these blocks can be powered separately to enable the system to select appropriate power supplies for desired performance and power consumption. The device has separate power domains for digital IO, digital core, analog core, analog input and speaker drivers. If desired, all of the supplies (except for the supplies for speaker drivers, which can directly connect to the battery) can be connected together and be supplied from one source in the range of 1.65 efficiency, the digital core power supply can range from 1.26V to 1.95V. The AVDD pin can directly be driven with SPKVDD supply slew rate needs to be lower than 20ms. For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

9.4 Layout

9.4.1 Layout Guidelines

• If the analog input, AINR and AINL, are: – Used, analog input traces must be routed symmetrically for true differential performance. – Used, do not run analog input traces parallel to digital lines. – Used, they must be AC-coupled. – Not used, they must be shorted together.
• Use a ground plane with multiple vias for each terminal to create a low-impedance connection to GND for minimum ground noise.
• Use supply decoupling capacitors. TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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9.4.2 Layout Example

Figure 9-5. Layout Diagram www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TAS2505

10 Device and Documentation Support

10.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

10.2 Documentation Support

10.2.1 Related Documentation

For related documentation see the following:

10.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10.8 Community Resources

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2021) to Revision D (January 2025) Page Changes from Revision B (November 2016) to Revision C (September 2021) Page TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 www.ti.com

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Changes from Revision A (February 2013) to Revision B (November 2016) Page

• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision * (February 2013) to Revision A (February 2013) Page

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The TAS2505TRGERQ1 orderable part number uses package outline RGE0024K, and the TAS2505ATRGERQ1 orderable part number uses package outline RGE0024Y. www.ti.com TAS2505 SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TAS2505

www.ti.com 7-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TAS2505IRGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TAS 2505 TAS2505IRGER.A Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TAS 2505 TAS2505IRGET Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TAS 2505 TAS2505IRGET.A Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TAS 2505 TAS2505IRGETG4 Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TAS 2505 TAS2505IRGETG4.A Active Production VQFN (RGE) | 24 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TAS 2505 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 7-Nov-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TAS2505 :

• Automotive : TAS2505-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS2505IRGER VQFN RGE 24 3000 367.0 367.0 35.0 TAS2505IRGER VQFN RGE 24 3000 346.0 346.0 33.0 TAS2505IRGET VQFN RGE 24 250 367.0 367.0 35.0 TAS2505IRGET VQFN RGE 24 250 210.0 185.0 35.0 TAS2505IRGETG4 VQFN RGE 24 250 367.0 367.0 35.0 TAS2505IRGETG4 VQFN RGE 24 250 210.0 185.0 35.0 Pack Materials-Page 2

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4204104/H

9,$TYPSOLDER MASK DETAILSNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASKDEFINED0.07 MAXALL AROUND0.07 MINALL AROUNDMETALSOLDER MASKOPENINGSOLDER MASKOPENINGMETAL UNDERSOLDER MASK

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