TAS2320RBGR

TAS2320 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 86

Technical content

TAS2320 19W Mono Digital Input Class-D Speaker Amp with 15V PVDD Support

1 Features

• Powerful Class-D amplifier – 19W output power @1% THD+N – 15V external PVDD supply
• Best-in-class efficiency – Up to 93.2% efficiency @ 1% TDH+N power – 14.7mW idle channel power, noise gate off – 5.3mW idle channel power, noise gate on – Integrated 1.8V VDD Y-bridge
• High performance audio channel – 14.2µV A-wt. idle channel noise – 114.4dB Dynamic Range – -90dB THD+N – Low EMI performance with ERC and SSM – < 1µs chip to chip group delay matching
• Advanced integrated features – Signal detection high efficiency modes – High accuracy supply voltage monitor & temp sensor – Boost sharing secondary device support – External Class-H Boost control algorithm
• Ease of use features – HW pin control or I2C based control – Clock based power up/down – Auto clock rate detection: 16 to 192kHz – MCLK free operation – Thermal and over current protection
• Power Supplies and user interface – VBAT: 2.5V to 5.5V – VDD: 1.65V to 1.95V – IOVDD: 1.8V or 3.3V – PVDD: 2.5V to 15V – I2S/TDM: 8 channels
• 26-Pin, 0.4mm Pitch, QFN package

2 Applications

• Smart Speakers with Voice Assistance
• Bluetooth and Wireless speakers
• Building Automation
• Tablets, Wearables
• Laptop, Desktop Computers

3 Description

The TAS2320 is a mono, digital input Class-D audio amplifier designed for efficiently driving high peak power into loudspeakers. TAS2320 is optimized to deliver best battery life for real-use cases of music playback and voice calls. Advanced efficiency optimization features like Y-bridge, and other algorithms enable the device to produce best-in-class efficiency across all power regions of operation. The Class-D amplifier is capable of delivering 15W output power using external PVDD supply. Up to four devices can share a common bus via I2S/TDM and I 2C interfaces. TAS2320 also supports HW pin based pre-defined controls that can configure the device for desired mode of operation without requiring any I2C controls. Device Information PART NUMBER PACKAGE(1) PACKAGE SIZE (2) TAS2320 QFN 4mm × 3.5mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Digital Audio Interface Control Interface Clocking Device Protections Power Management Digital Core Monitor ADC VBAT, PVDD, and Temp Monitor Efficiency Algos Filters / Control VBAT PVDD TEMP PVDD OUT_P OUT_N DREG GREG SBCLK FSYNC SDIN SDOUT SEL4_ADDR SEL5 SEL3_SDA SEL2_SCL GND PGND SDZ IRQZ Class-D Amp VBATVDDIOVDD SEL1 Functional block diagram TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

2 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

4 Pin Configuration and Functions

SEL5_CLH SBCLK SDIN SDOUT GND NC VBAT SDZ IRQZ SEL2_SCL IOVDD SEL3_SDA SEL4_ADR OUT_P

14 PGND

OUT_N PVDD GREG SEL1_I2C VBAT 7 6 5 4 3 2 Not to scale Figure 4-1. QFN Package Bottom View www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TAS2320

Type(1) DESCRIPTION NAME NO. DREG 26 P Digital core voltage regulator output. Bypass to GND with a capacitor. Do not connect to an external load. FSYNC 8 I I2S word clock or TDM frame sync. GREG 17 P High-side gate CP regulator output. Do not connect to an external load. GND 12, 22, 23, 25 P Connect to PCB ground plane. Strong connection to ground plane required through multiple vias. IOVDD 5 P 1.8V or 3.3V Digital IO supply. Decouple to GND with capacitor. IRQZ 6 O Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pullup is not used. NC 13 - No connect. Keep floating. OUT_N 19 O Class-D negative output. OUT_P 20 O Class-D positive output. PGND 21 P Class-D Power stage ground. Connect to PCB GND plane strongly through multiple vias. PVDD 18 P Class-D power stage supply. Decouple to GND with capacitor. SBCLK 9 I I2S or TDM serial bit clock. SDIN 10 I I2S or TDM serial data input. SDOUT 11 I/O I2S or TDM serial data output. SDZ 7 I Active low hardware shutdown. SEL1_I2C 16 I HW Mode: Select 1 Pin. Amplifier gain level selection with volume ramp enable and disable options. I2C Mode: Short to GND for I2C mode selection. SEL2_SCL 4 I HW Mode: Select 2 Pin. I2S, TDM, Left justified selection. I2C Mode: Clock Pin. Pull up to IOVDD with a resistor. SEL3_SDA 3 I/O HW Mode: Select 3 Pin. Data valid rising edge and falling edge selection. I2C Mode: Data Pin. Pull up to IOVDD with a resistor. SEL4_ADR 2 I HW Mode: Select 4 Pin.Y-bridge threshold configuration setting. I2C Mode: I2C address pin. SEL5_CLH 1 I/O HW Mode: Select5 Pin. Connect to IOVDD. I2C Mode: Class-H control. Shared boost output or external boost PWM generation. Short to GND if shared boost or external boost feature is not used. VBAT 15 P Battery power supply input. Connect to a 2.5 to 5.5V supply and decouple with a capacitor. 14 I Battery power supply input. Connect to a 2.5 to 5.5V supply. VDD 24 P Connect to 1.8V supply and decouple to GND with capacitor. (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

4 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply Voltage PVDD –0.3 19 V Supply Voltage VBAT –0.3 6 V Supply Voltage VDD –0.3 2 V Supply Voltage IOVDD –0.3 6 V Class-D Output OUTP, OUTM –0.7 19 V High Side Drive Regulator GREG –0.3 PVDD + 6 V Digital Supply Regulator DREG –0.3 1.65 V Digital IO Pins Digital pins referenced to IOVDD supply –0.3 6 V Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per ANSI/ESDA/ JEDEC JS-002, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VBAT Battery Supply 2.5 3.6 5.5 V VPVDD Amplifier Supply VBAT 12 15 V VVDD Supply Voltage 1.65 1.8 1.95 V VIOVDD IO Supply Voltage 1.8V 1.62 1.8 1.98 V VIOVDD IO Supply Voltage 3.3V 3.0 3.3 3.6 V RSPK Speaker resistance 3.2 8 38.4 Ω LSPK Speaker inductance 5 33 100 µH TA Ambient temperature –40 85 °C TJ Junction temperature –40 150 °C

5.4 Thermal Information

THERMAL METRIC(1) Standard JEDEC(2) UNITHR-QFN

26 PINS

RθJA Junction-to-ambient thermal resistance 51.5 ℃/W RθJC(top) Junction-to-case (top) thermal resistance 28.5 ℃/W RθJB Junction-to-board thermal resistance 15.3 ℃/W www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TAS2320

THERMAL METRIC(1) Standard JEDEC(2) UNITHR-QFN ΨJT Junction-to-top characterization parameter 0.9 ℃/W ΨJB Junction-to-board characterization parameter 15.2 ℃/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) JEDEC Standard 4 Layer PCB

5.5 Electrical Characteristics

TA = 25°C, PVDD = 12V, VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AMPLIFIER PERFORMANCE POUT_EXT _PVDD Maximum Output Power - 1% THD+N RL = 8 Ω + 33 µH 8.3 W RL = 4 Ω + 33 µH 14.6 W RL = 8 Ω + 33 µH, PVDD = 15V 11.2 W RL = 4 Ω + 33 µH, PVDD = 15V 19 W POUT_EXT _PVDD Maximum Output Power - 10% THD+N RL = 8 Ω + 33 µH 10.3 W RL = 4 Ω + 33 µH 18.0 W ηSYSTEM_ _EXT_1W System Efficiency at POUT = 1.0W RL = 8 Ω + 33 µH 88.5 % RL = 4 Ω + 33 µH 84.3 % ηSYSTEM_ EXT_MAX_ POUT System Efficiency at 1% THD+N power Level RL = 8 Ω + 33 µH 93.2 % RL = 4 Ω + 33 µH 88.5 % VN_EXT Idle channel Noise A-Weighted, Gain = 21dBV (Speaker Mode), DAC-Running 14.2 µV DNR_EX T Dynamic Range A-Weighted, -60 dBFS Method, RL = 8 Ω + 33 µH 114.4 dB THD+N_ EXT Total Harmonic distortion + Noise POUT = 1 W, RL = 8 Ω + 33 µH 0.003 % POUT = 1 W, RL = 4 Ω + 33 µH 0.004 % KCP_EXT Click and pop performance All dynamic power up/downs of audio channel except for faults. Includes In/Out of Mute, Power Up and power Down, Noise Gate mode entry and Exit. Measured at Peak A-weighted Voltage. RL = 8 Ω + 33 µH, Input = Digital Silience –68 dBV VOS_EX T Output Offset Voltage Idle channel –1 1 mV PSRRPV DD_EXT PVDD power-supply rejection ratio PVDD + 200 mVpp, fripple = 217 Hz 119 dB PVDD + 200 mVpp, fripple = 1 kHz 115 dB PVDD + 200 mVpp, fripple = 20 kHz 91 dB PSRRVB AT_EXT VBAT power-supply rejection ratio VBAT + 200 mVpp, fripple = 217 Hz 118 dB VBAT + 200 mVpp, fripple = 1 kHz 116 dB VBAT + 200 mVpp, fripple = 20 kHz 102 dB PSRRVD D_EXT VDD power-supply rejection ratio VDD + 200 mVpp, fripple = 217 Hz 113 dB VDD + 200 mVpp, fripple = 1 kHz 113 dB VDD + 200 mVpp, fripple = 20 kHz 91 dB TDM Serial Port TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

6 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

TA = 25°C, PVDD = 12V, VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PCM Sample Rates and FSYNC Input Frequency 16 192 kHz SBCLK Input Frequency I2S/TDM Operation 0.512 24.57 MHz SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation 0.5 ns RMS Jitter above 40 kHz that can be tolerated without performance degradation 5 ns SBCLK Cycles per FSYNC in I2S and TDM Modes Values: 64, 96, 128, 192, 256, 384 and 512 64 512 Cycles PCM Playback Characteristics to fs ≤ 48 kHz Fs Sample Rates 16 48 kHz Audio Channel Passband LPF Corner Ripple < pass-band ripple 0.454 fs Audio Channel Passband Ripple 20 Hz to LPF cutoff ± 0.1 dB Audio Channel Stop Band Attenuation ≥ 0.55 fs 60 dB ≥ 1 fs 65 dB Audio Channel Group Delay Fin = 1kHz, Lowest latency mode (Y- bridge, Noise gate disabled) 8.5 1/fs Fin = 1kHz, Class-H disabled 16.5 1/fs DC to 20kHz, Lowest latency mode (HPF bypassed, Y-bridge, Noise gate disabled) 13 1/fs DC to 20kHz, HPF bypassed 21 1/fs PCM Playback Characteristics to fs > 48 kHz Fs Sample Rates 88.2 192 kHz Audio Channel Passband LPF Corner fs = 96 kHz 0.469 fs fs = 192 kHz 0.234 fs Audio Channel Passband Ripple 20 Hz to LPF cutoff ± 0.2 dB Audio Channel Stop Band Attenuation fs = 96 kHz, fin ≥ 0.55 fs 60 dB fs = 96 kHz, fin ≥ 1 fs 65 dB fs = 192 kHz, 0.55 fs ≥ fin ≥ 0.275 fs 60 dB Audio Channel Group Delay Fin = 1kHz, Fs = 96kHz, Lowest latency mode (Y-bridge, Noise gate disabled) 11 1/fs Fin = 1kHz, Fs = 96kHz, Class-H disabled 6.7 1/fs DC to 20kHz, Fs = 96kHz, Lowest latency mode (HPF bypassed, Y-bridge, Noise gate disabled) 11.5 1/fs DC to 40kHz, Fs=96kHz, HPF bypassed 28.6 1/fs Protection Circuits Thermal shutdown temperature 140 °C Thermal shutdown retry time 1.5 s VBAT undervoltage lockout threshold (UVLO) UVLO is asserted 1.9 V UVLO is released 2.3 V VDD undervoltage lockout threshold (UVLO) UVLO is asserted 1.4 V UVLO is released 1.6 V PVDD undervoltage lockout threshold (UVLO) UVLO is asserted 2.6 V UVLO is released 2.8 V www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TAS2320

TA = 25°C, PVDD = 12V, VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PVDD overvoltage lockout threshold (OVLO) OVLO is asserted, OVLO protection enabled. 16 V Output Short circuit protection Output to Output, Output to GND, Output to PVDD, Output to VBAT, H-bridge mode 5.3 A Power up/down Time TSTDBY Turn ON time from SDZ Asserted to device ready for i2c Command 300 us TACTIVE Turn ON time from release of Software Shutdown to Amplifier output Active Volume ramping disabled 1.6 ms Volume ramping enabled 3.9 ms TTURNOFF Turn OFF time from assertion of Software Shutdown to Amplifier output Hi-Z Volume ramping disabled 0.2 ms Volume ramping enabled 13.9 ms Current Consumption IQ_HW_SD Current consumption in Hardware Shutdown PVDD, SDZ=0 0.1 uA VBAT, SDZ=0 0.1 uA VDD, SDZ=0 0.2 uA IOVDD, SDZ=0 0.1 uA IQ_SW_SD Current consumption in Software Shutdown PVDD, All clocks Stopped 0.1 uA VBAT, All clocks Stopped 0.1 uA VDD, All clocks Stopped 12 uA IOVDD, All clocks Stopped 0.1 uA IQ_NG Current consumption in Idle channel PVDD, POUT = 0, Noise gate enabled 0.1 mA VBAT, POUT = 0, Noise gate enabled 0.15 mA VDD, POUT = 0, Noise gate enabled 2.2 mA IOVDD, POUT = 0, Noise gate enabled 0.1 mA Total Power, POUT = 0, Noise gate enabled 5.3 mW IQ_IDLE Current consumption in Idle channel PVDD, POUT = 0, Noise gate disabled 0.2 mA VBAT, POUT = 0, Noise gate disabled 0.5 mA VDD, POUT = 0, Noise gate disabled 6 mA IOVDD, POUT = 0, Noise gate disabled 0.1 mA Total Power, POUT = 0, Noise gate disabled 14.7 mW DIGITAL IOs VIH High-level digital input logic voltage threshold All digital pins 0.7 x IOVDD V VIL Low-level digital input logic voltage threshold All digital pins 0.3 x IOVDD V VOH High-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOH = 100µA IOVDD -

0.2 V V

VOL Low-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOL = -100µA 0.2 V VOL(I2C) Low-level digital output voltage SDA and SCL; IOL = -1mA 0.2 x IOVDD V VOL(IRQZ) Low-level digital output voltage for open drain output IRQZ pin; IOL = -1mA 0.2 V IIH (1) Input logic-high leakage for digital inputs All digital pins; Input = IOVDD. -1 1 µA TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

8 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

TA = 25°C, PVDD = 12V, VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIL (1) Input logic-low leakage for digital inputs All digital pins; Input = GND -1 1 µA CIN Input capacitance for digital inputs All digital pins 5 pF RPD Pull down resistance for digital input/IO pins when asserted on All digital pins. Pull down resistance option enabled 18 kΩ (1) Errata: Additional 2mA to 3mA current consumption expected if IRQZ signal is pulled high. Read more details in section "what to do and what not to do".

5.6 Timing Requirements

TA = 25 °C, VDD = IOVDD = 1.8 V (unless other wise noted) MIN NOM MAX UNIT I2C - Standard Mode fSCL SCL clock frequency 0 100 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 μs tLOW LOW period of the SCL clock 4.7 μs tHIGH HIGH period of the SCL clock 4 μs tSU;STA Setup time for a repeated START condition 4.7 μs tHD;DAT Data hold time: For I2C bus devices 0 3.45 μs tSU;DAT Data set-up time 250 ns tr SDA and SCL rise time 1000 ns tf SDA and SCL fall time 300 ns tSU;STO Set-up time for STOP condition 4 μs tBUF Bus free time between a STOP and START condition 4.7 μs Cb Capacitive load for each bus line 400 pF I2C - Fast Mode fSCL SCL clock frequency 0 400 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 μs tLOW LOW period of the SCL clock 1.3 μs tHIGH HIGH period of the SCL clock 0.6 μs tSU;STA Setup time for a repeated START condition 0.6 μs tHD;DAT Data hold time: For I2C bus devices 0 0.9 μs tSU;DAT Data set-up time 100 ns tr SDA and SCL rise time 20 + 0.1 × Cb 300 ns tf SDA and SCL fall time 20 + 0.1 × Cb 300 ns tSU;STO Set-up time for STOP condition 0.6 μs tBUF Bus free time between a STOP and START condition 1.3 μs Cb Capacitive load for each bus line 400 pF TDM Port fsbclk SBCLK Frequency range 0.384 24.576 MHz tH(SBCLK) SBCLK high period 0.35/fsbclk ns tL(SBCLK) SBCLK low period 0.35/fsbclk ns tSU(FSYNC) FSYNC setup time 8 ns www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TAS2320

TA = 25 °C, VDD = IOVDD = 1.8 V (unless other wise noted) MIN NOM MAX UNIT tHLD(FSYNC) FSYNC hold time 8 ns tSU(SDIN) SDIN setup time 8 ns tHLD(SDIN) SDIN hold time 8 ns td(SBCLK- SDOUT) SBCLK to SDOUT delay : 10% of SBCLK falling edge or 90% of SBCLK rising edge to 50% of SDOUT, IOVDD=1.8V 30 ns td(SBCLK- SDOUT) SBCLK to SDOUT delay : 10% of SBCLK falling edge or 90% of SBCLK rising edge to 50% of SDOUT, IOVDD=3.3V 18.5 ns tr(SBCLK) SBCLK rise time : 10 % - 90 % Rise Time 0.15 / fsbclk ns tf(SBCLK) SBCLK fall time : 90 % - 10 % Rise Time 0.15 / fsbclk ns tf(SBCLK- CLH) SBCLK to CLH delay: Boost share configuration 1 /2* fsbclk ns

5.7 Timing Diagrams

th(STA) tLOW tr th(DAT) tf tHIGH tsu(DAT) SDA SCL tsu(STA) STA th(STA) STO tsu(STO) Figure 5-1. I2C timing diagram FSYNC SBCLK tH(SBCLK) tL(SBCLK) tr(SBCLK) tf(SBCLK) tSU(FSYNC)tHLD(FSYNC) tSU(SDIN) tHLD(SDIN) td(SDO-FSYNC) td(SBCLK_SDOUT) SDIN SDOUT Figure 5-2. I2S/TDM timing diagram

5.8 Typical Characteristics

TA = 25°C, VBAT = 3.6V, PVDD = 12V, VDD = 1.8V, IOVDD = 1.8V, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, SDZ = 1, Noise gate disabled, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted). TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

10 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

O u t p u t P o w e r ( W ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 P V D D = 4 . 5 V P V D D = 8 . 4 V P V D D = 1 2 V P V D D = 1 4 V P V D D = 1 5 V RL = 8Ω Figure 5-9. Efficiency vs Output Power O u t p u t P o w e r ( W ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 P V D D = 4 . 5 V P V D D = 8 . 4 V P V D D = 1 2 V P V D D = 1 4 V P V D D = 1 5 V RL = 4Ω Figure 5-10. Efficiency vs Output Power O u t p u t P o w e r ( W ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 P V D D = 4 . 5 V P V D D = 8 . 4 V P V D D = 1 2 V P V D D = 1 4 V P V D D = 1 5 V RL = 8Ω HW Pin Control Figure 5-11. Efficiency vs Output Power O u t p u t P o w e r ( W ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 P V D D = 4 . 5 V P V D D = 8 . 4 V P V D D = 1 2 V P V D D = 1 4 V P V D D = 1 5 V RL = 4Ω HW Pin Control Figure 5-12. Efficiency vs Output Power P V D D ( V ) Output Power (W) 4 . 5 6 7 . 5 9 1 0 . 5 1 2 1 3 . 5 1 5 1 2 1 5 1 8 2 1 2 4 2 7 3 0 T H D + N = 0 . 1 % T H D + N = 1 % T H D + N = 1 0 % RL = 8 Ω Figure 5-13. Output Power vs PVDD Voltage P V D D ( V ) Output Power (W) 4 . 5 6 7 . 5 9 1 0 . 5 1 2 1 3 . 5 1 5 1 2 1 5 1 8 2 1 2 4 2 7 3 0 T H D + N = 0 . 1 % T H D + N = 1 % T H D + N = 1 0 % RL = 4 Ω Figure 5-14. Output Power vs PVDD Voltage TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

12 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

6 Detailed Description

6.1 Overview

The TAS2320 is a mono digital input Class-D amplifier optimized for delivering the highest efficiency across all powers for longer battery life operation. It comes with a small solution size for board space-constrained applications. It integrates battery/temperature sensors for system-level protection features.

6.2 Functional Block Diagram

VBAT, PVDD, and Temp Monitor Efficiency Algos Filters / Control VBAT PVDD TEMP PVDD OUT_P OUT_N DREG GREG SBCLK FSYNC SDIN SDOUT SEL4_ADR SEL5_CLH SEL3_SDA SEL2_SCL GND PGND SDZ IRQZ Class-D Amp VBATVDDIOVDD SEL1_I2C Figure 6-1. Top Level Functional block diagram

6.3 Device Functional Modes

6.3.1 Operational Modes

6.3.1.1 Hardware Shutdown

The device can be powered down by asserting SDZ pin low. The shutdown behavior of the device when SDZ pin is pulled low is controlled by SDZ_MODE register settings. In Hardware Shutdown mode (SDZ_MODE[1:0] = 00 or 01) if the SDZ pin is asserted low, the device consumes the minimum quiescent current from supplies. All registers lose state in this mode and go back to default settings, and I2C communication is disabled. If configured in SDZ_MODE[1:0] = 00, when the SDZ pin is asserted low while audio is playing, the device will follow the normal power down sequencing like volume ramp down on the audio (if enabled), stop the Class-D TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

14 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

switching, power down analog and digital blocks to ensure no power down pop and finally put the device into Hardware Shutdown mode. I2C communication is disabled while the SDZ pin is asserted low in this mode. If configured in SDZ_MODE[1:0] = 01, when the SDZ pin is asserted low the device will immediately enter the hardware shutdown and will not go through any power-down sequencing routine. It is recommended to ensure that the audio input signal is ramped down to the idle channel before asserting the SDZ pin low in this mode, device software mute mode can be used to realize this. I 2C communication is disabled while the SDZ pin is asserted low in this mode. Finally, the device can be configured to Software shutdown mode by setting SDZ_MODE[1:0] = 10. In this mode, when the SDZ pin is pulled low, the device will follow normal power-down sequencing and enter software shutdown mode. All the device register configuration programmed is retained as is from the state the device was in before the SDZ pin was pulled low. I 2C communication is still available while the SDZ pin is asserted low in this mode. Table 6-1. Shutdown Control SDZ_MODE[1:0] Configuration 00 (default) Hardware shutdown mode with power-down sequencing

01 Hardware shutdown mode -

10 Software shutdown mode (All

register values retained)

11 Reserved

When SDZ_MODE[1:0] is 00 or 10, the device goes through shutdown sequencing and the SDZ pin must be held low for the entire duration of the shutdown time. The shutdown time is specified in the Power up/down Time section of the Electrical Characteristics section. When SDZ is released, the device will sample relevant configuration and address pins then enter software shutdown mode.

6.3.1.2 Hardware Config Modes

The TAS2320 device can operate in a Pin control based HW Mode depending on the resistor terminations used for Select Pin1 to Select Pin5. Pin control based HW Mode behavior of the device is designed to simplify device configuration without using any software based configurations through I2C communication. Table 6-2. Select Pin Functionalities Select Pin Name Functionality SEL1 Amplifier gain setting with volume ramp enable/disable option SEL2 I2S, TDM, Left justified selection SEL3 Data valid rising/falling edge selection SEL4 Y-bridge threshold configuration SEL5 Supply voltage mode selection Table 6-3. SEL1 HW Mode configuration SEL1 Connection Amplifier Gain Volume Ramp Direct Short to GND Configured through I2C Configured through I2C 1.2kΩ to GND 6 dBV Disabled 1.2kΩ to VBAT 12 dBV Disabled 5kΩ to GND 18 dBV Disabled 330Ω to VBAT 21 dBV Disabled 5kΩ to VBAT 6 dBV Enabled www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TAS2320

Table 6-3. SEL1 HW Mode configuration (continued) SEL1 Connection Amplifier Gain Volume Ramp 24kΩ to GND 12 dBV Enabled 24kΩ to VBAT 18 dBV Enabled Direct Short to VBAT 21 dBV Enabled Table 6-4. SEL2 HW Mode configuration SEL2 Connection Configuration Direct Short to GND I2S L or TDM0 330Ω to IOVDD I2S R or TDM1 Direct Short to IOVDD I2S (L+R)/2 or TDM2 1.2kΩ to GND Left-Justified L or TDM3 1.2kΩ to IOVDD Left-Justified R or TDM4 5kΩ to GND Left-Justified (L+R)/2 or TDM5 5kΩ to IOVDD I2S L or TDM6 24kΩ to GND I2S R or TDM7 24kΩ to IOVDD Reserved Table 6-5. SEL3 HW Mode configuration SEL3 Connection Configuration Direct Short to GND Data valid on rising edge Direct Short to IOVDD Data valid on falling edge Table 6-6. SEL4 HW Mode configuration SEL4 Connection Configuration Direct Short to GND Y-bridge threshold of 80mW Direct Short to IOVDD Y-bridge threshold of 40mW 24kΩ to IOVDD Y-bridge threshold of 1mW Table 6-7. SEL5 HW Mode configuration SEL5 Connection Configuration Direct Short to IOVDD HW mode supply config

6.3.1.3 Software Power Modes Control and Software Reset

When SEL1 pin is shorted to GND, TAS2320 is configured in I 2C Mode and can be configured by modifying configuration registers over I2C interface. TAS2320 power state can be controlled using the register MODE[1:0]. Change in any of the MODE settings will not cause the device to lose any of the existing device configuration register settings. Table 6-8. Software Mode Control MODE[1:0] Configuration

00 Device in active mode of

01 Reserved

10 (default) Device in software shutdown mode

11 Device in Clock based Active and

Active state: When MODE[1:0] is configured as '00', the device enters an active mode of operation with proper power-up sequencing to minimize the click and pop. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

16 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Software shutdown state: When MODE[1:0] is configured as '10', the device enters software shutdown mode. This mode powers down all analog blocks required to playback audio but does not cause the device to lose register state. If audio is playing when Software Shutdown is asserted, the Class-D will volume ramp down before shutting down. When de-asserted, the Class-D will begin switching and volume ramp back to the programmed digital volume setting. Clock based Active and shutdown state: When MODE[1:0] is configured as '11' the device toggles between Active and Shutdown state based on valid ASI clock signals applied on the ASI input pins, BCLK and FSYNC. When clocks are applied, the device will automatically detect the clock signals and follow proper power-up sequencing to avoid any power-up click and pop. When the audio channels are powered up and the ASI clock is removed, the device will automatically start power-down sequencing and avoid any click and pop. It is recommended to do a volume ramp-down in the input data stream before stopping the clocks for the best pop & click experience (device software mute mode can be used to realize this). TAS2320 can be reset to its default configuration by setting the SW_RESET register to '1'. If the device is powered up, when the SW_RESET bit is set high, all the channels are powered down immediately. All the registers are restored to the default state when SW_RESET is set high. This bit is self-clearing and goes back to '0' once the reset is complete. The device can also signal to the host once the status of the device reaches Active mode of operation using the INT_LTCH0[1] bit ( Section 6.3.2). This bit is a live device status bit and reflects the device status in real-time. This bit is set high when the device is in Active mode and set low when the device is in shutdown mode.

6.3.1.4 Efficiency and power saving modes

TAS2320 has multiple power-saving modes of operation designed to achieve the highest system level efficiency under all operating conditions. The device transitions from one mode to the next based on the configured mode and the signal condition. The transitions from one mode to another are automatic and designed to ensure high-performance audio levels during the transition of the modes.

6.3.1.4.1 Noise Gate

When the Noise gate feature is enabled, the device automatically detects periods of silence during active playback mode and reduces the idle channel power consumption significantly to extend the battery life. This feature is useful for signals playback having long periods of silence, eg voice calls, movie tracks, etc. The device monitors the input audio signal level against the programmed Noise gate threshold configured by the NG_TH_LVL[2:0] register. When the audio signal falls below the threshold, an internal Hysteresis timer is enabled. If the signal level remains below the configured NG_TH_LVL[2:0] for the entire duration of the NG_HYST_TIMER[1:0], the device enters into the Noise gate mode and reduces the idle channel power consumption. In the Noise gate mode of operation, the high switching blocks like class-D PWM output are turned OFF and outputs are pulled low. The output impedance of class-D can be controlled when the Noise gate mode is active using the CLASSD_HIZ_MODE register. While the Noise gate mode is active, class-D outputs are not switching and the device does not produce any audio output signal. When the device is in Noise gate mode, the NG_STATUS bit is set as high and when the device comes out of noise gate mode, the status bit is set to low. When the signal level increases above the NG_TH_LVL[1:0], the device automatically wakes up the blocks in low IQ mode and starts playing out the audio input signals. The wake up from Noise gate maintains the signal fidelity by buffering the input signal data during the transition time from noise gate mode to active playback mode. The device does not lose any audio input samples while transitioning from noise gate to active playback. The transition into noise gate mode and recovery out of noise gate mode is designed to be click and pop-free by following the proper shutdown and power up sequencing. Table 6-9. Noise gate threshold NG_TH_LVL[2:0] Configuration 000 -85 dBFs www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TAS2320

Table 6-9. Noise gate threshold (continued) NG_TH_LVL[2:0] Configuration 001 -90 dBFs 010 -95 dBFs 011 -100 dBFs 100 (default) -105 dBFs 101 -110 dBFs 110 -115 dBFs 111 -120 dBFs Table 6-10. Noise gate hysteresis timer NG_HYST_TIMER[1:0] Configuration 00 10 ms 01 (default) 50 ms 10 100 ms 11 1000 ms

6.3.1.4.2 Music Efficiency Mode

When the Music efficiency mode feature is enabled, the device automatically detects low-power signal states during active playback mode and reduces the overall IQ power consumption to extend the battery life. This feature is useful for dynamic audio signals with varying signal levels for example music tracks, voice calls movie tracks, and so forth. The device monitors the input audio signal level against the programmed Music efficiency threshold configured by the MUSIC_EFF_MODE_THR[23:0] register. When the audio signal falls below the threshold, an internal hysteresis timer is enabled. If the signal level remains below the configured MUSIC_EFF_MODE_THR[23:0] for the entire duration of the MUSIC_EFF_MODE_TIMER[23:0], the device enters into the Music efficiency mode. When the device is in Music efficiency mode, the MUSIC_EFF_STATUS bit is set as high and when the device comes out of music efficiency mode, the status bit is set low. When the signal level increases above the MUSIC_EFF_MODE_THR[23:0], the device automatically wakes up the blocks in low IQ mode and continues playing out the audio input signals. The transition from Music efficiency mode to normal operation occurs with minimal click and pop. While the device is in Music efficiency mode, the audio channel performance is maintained and doesn't impact the output signal level or noise. The MUSIC_EFF_MODE_THR[23:0] and MUSIC_EFF_MODE_TIMER[23:0] registers can be configured using the PPC3 Software Section 6.4.1.

6.3.2 Faults and Status

During power-up sequencing, the power-on-reset circuit (POR) monitors the VDD and IOVDD pins and holds device in reset (including all the configuration registers) until the supplies are valid. Any supply voltage dip on VDD or IOVDD below the UVLO voltage thresholds resets the device immediately along with all the register configurations. During operation modes, the device monitors internal device status and fault conditions and can notify the host of error and status conditions using the IRQZ interrupt pin and internal I2C based interrupt registers. The interrupt generation in IRQZ pin can be masked by configuring the corresponding Interrupt mask register bit. Table 6-11 lists the different faults and interrupts that the device monitors and the corresponding configuration bits to enable/disable the interrupt generation and reading the I2C interrupt status TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

18 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 6-11. Faults and Interrupts Category Interrupt Interrupt Mask register bit Default Mask status Interrupt Latched status bit Limiter & Brown out protection Section 6.4.2.4 Brownout detected INT_MASK0[3] Not Masked INT_LTCH0[3] BOP Active INT_MASK0[2] Not Masked INT_LTCH0[2] BOP infinite hold INT_MASK0[7] Not Masked INT_LTCH0[7] Limiter Active INT_MASK0[4] Not Masked INT_LTCH0[4] Limiter attenuation INT_MASK0[6] Not Masked INT_LTCH0[6] Supply below inflection point INT_MASK0[5] Not Masked INT_LTCH0[5] Supply Voltage Monitors Section 6.4.5 PVDD Over voltage INT_MASK3[2] Not Masked INT_LTCH3[2] PVDD Under voltage INT_MASK1[7] Not Masked INT_LTCH1[7] Thermal protection Section 6.4.6 Thermal warning at 135C INT_MASK1[4] Masked INT_LTCH1[4] Thermal warning at 125C INT_MASK1[3] Masked INT_LTCH1[3] Thermal warning at 115C INT_MASK1[2] Masked INT_LTCH1[2] Thermal warning at 105C INT_MASK1[1] Masked INT_LTCH1[1] Over temperature error INT_MASK3[7] Not Masked INT_LTCH3[7] Clock protection Section 6.4.7.1 Watchdog expiry INT_MASK2[7] Not Masked INT_LTCH2[7] Frame out of sync INT_MASK2[5] Masked INT_LTCH2[5] PLL clock error INT_MASK2[4] Not Masked INT_LTCH2[4] TDM clock error INT_MASK2[3] Masked INT_LTCH2[3] Pre-Power-up Clock error INT_MASK4[2] Not Masked INT_LTCH4[2] Clock ratio change error INT_MASK2[2] Masked INT_LTCH2[2] Fs change error INT_MASK2[1] Masked INT_LTCH2[1] Fs invalid error INT_MASK2[0] Masked INT_LTCH2[0] Frame out of sync INT_MASK2[5] Masked INT_LTCH2[5] Internal PLL Clock error INT_MASK2[4] Not Masked INT_LTCH2[4] Digital watchdog INT_MASK2[7] Not Masked INT_LTCH2[7] Other Protections & Status Class-D Over current error INT_MASK3[3] Not Masked INT_LTCH3[3] Device Active INT_MASK0[1] Masked INT_LTCH0[1]

6.3.2.1 Interrupt generation and clearing

The IRQZ is an open drain output that asserts low during unmasked fault conditions and therefore must be pulled up with a resistor to IOVDD. An internal pull up resistor (18k Ω) is provided in the device and can be assessed by setting the IRQZ_PU register bit. The interrupt generation on IRQZ pin can be configured using IRQZ_PIN_CFG[1:0] register. For the interrupts that have auto retry feature, the retry timer can be configured using RETRY_WAIT_TIME register. The interrupt pin polarity can be changed from the default case of Active Low to Active high by setting the IRQZ_POL register bit high. Any latched interrupt can be cleared by setting INT_CLR_LTCH bit high. This is self clearing bit and automatically gets updated to low once the interrupt is cleared. Interrupts can also be cleared by hardware shutdown by pulling the SDZ pin low, or by software reset using SW_RESET bit. Table 6-12. IRQZ pin configuration IRQZ_PIN_CFG[1:0] Configuration

00 Reserved

01(default) Interrupt generated on any unmasked latched interrupt

10 Reserved

www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TAS2320

Table 6-12. IRQZ pin configuration (continued) IRQZ_PIN_CFG[1:0] Configuration

11 Interrupt generated for 2 to 4 ms

every 4 ms on any unmasked latched interrupt Table 6-13. Retry wait timer RETRY_WAIT_TIME Configuration 0 (default) Retry every 1.5sec

1 Retry every 100ms

6.4 Feature Description

6.4.1 PurePath™ Console 3 Software

The TAS2320's advanced features and device configuration can be performed using PurePath Console 3 (PPC3) software. The base PPC3 software can be downloaded and installed from TI website . Once installed the TAS2320 application can be downloaded with-in base PPC3 software. The TAS2320 PPC3 application calculates necessary register coefficients that are described in the following sections so it is highly recommended to use PPC3 in I 2C Mode. The device configurations are optimized using register updates based on the options selected in PPC3. This is the recommended method to configure the device for best performance. Once TAS2320 PPC3 application calculates and updates the device, End System Integration tab in PPC3 can be used to generate files for final system integration.

6.4.2 Playback Signal Path

6.4.2.1 Digital Volume Control and Amplifier Output Level

The gain from audio input to speaker terminals is controlled by setting the amplifier’s analog gain level (A AMP) and digital volume control (A DVC). Equation 1 calculates the amplifiers output voltage. Amplifier analog gain setting should be set before powering up the playback channel and shouldn't be changed while the channel is active. The digital volume control can be modified while the channel is active and also allows for soft volume ramp up/down feature to allow for smooth transition of output voltage from one level to another. AMP dvc AMPV Input A A dBV/c61 /c43 /c43 (1) where

• VAMP is the amplifier output voltage in dBV
• Input is the digital input amplitude in dB with respect to 0 dBFS
• ADVC is the digital volume control setting, 6 dB to -110 dB in 0.5 dB steps
• AAMP is the amplifier output level setting, -0.071dBV to 21.0dBV in 0.5017dBV steps. Amplifier output level settings are presented in dBV (dB relative to 1 V rms) with a full scale digital audio input (0 dBFS) and the digital volume control set to 0 dB. It should be noted that these levels may not be achievable because of analog clipping in the amplifier, so they should be used to convey gain only. Table below shows gain settings that can be programmed via the AMP_LVL register. When AMP_LVL is set to less than 9dBV settings, the playback channel is automatically configured to low noise mode or receiver mode of operation. Table 6-14. Amplifier Output Level Settings AMP_LVL[5:0] FULL SCALE OUTPUT dBV VPEAK (V) 0x00 21.000 15.9 0x01 20.498 15.0 0x02 19.997 14.1 0x03 19.495 13.3 TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

20 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 6-14. Amplifier Output Level Settings (continued) AMP_LVL[5:0] FULL SCALE OUTPUT dBV VPEAK (V) 0x04 18.993 12.6 0x27 1.434 1.7 0x28 0.932 1.6 0x29 0.430 1.5 0x2A -0.071 1.4 0x2B-0x3F Reserved Reserved When a change in digital volume control occurs, the device ramps the volume to the new setting based on the DVC_SLEW_RATE register bits. If DVC_SLEW_RATE is set to 0x7FFFFF, volume ramp is disabled. This can be used to speed up start up, shutdown and digital volume changes when volume ramp is handled by the system host. When volume ramp is disabled, the input audio data stream should be held at digital silence during shutdown and power up of the device to avoid any clicks and pops. The device can be put in software based mute by setting DVC_LEVEL to 0x000000 setting. The digital voltage control registers DVC_LEVEL and DVC_SLEW_RATE registers can be configured using the PPC3 Software Section 6.4.1. Table 6-15. Digital Volume Control DVC_LEVEL[23:0] VOLUME (dB) 0x000000 Software MUTE 0x00000D (MIN) -110 0x400000 0 (default) 0x7FB261 (MAX) 6 Table 6-16. Digital Volume Ramp Rate DVC_SLEW_RATE[23:0] RAMP RATE @ 48kHz (s) 0x00036A 1000ms ... 0x034A51 4ms (default) ... 0x7FFFFF 0 - Ramp disabled

6.4.2.2 High Pass Filter

Excessive DC and low frequency content in audio playback signal can damage loudspeakers. The playback path employs a high-pass filter (HPF) to prevent this from occurring. The HPF is a 1st order filter and can be changed from the default 2 Hz for 48ksps fs using the AUDIO_HPF_N0, AUDIO_HPF_N1, AUDIO_HPF_D1 registers. The HPF filter frequency scales with change in the FSYNC clock and can be re-configured to achieve the required cutoff frequency for different FSYNC clock frequencies. The coefficients can also be changed to disable the HPF coefficients appropriately. These coefficients should be calculated and set using PPC3 Software Section 6.4.1.

6.4.2.3 Class-D Amplifier

www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TAS2320

TAS2320 has integrated high performance class-D amplifier with low idle channel noise, low distortion and high PSRR. The Class-D amplifier switches on a clock frequency derived from the SBCLK frequency and is always synchronized to the input clock source. The SAMP_RATE_CFG register enables selection between input clock source based out of multiple of 44.1kHz vs 48kHz multiples. Table 6-17. Sample rate configuration SAMP_RATE_CFG Configuration 0 (default) Audio data rate is multiple/sub- multiple of 48ksps

1 Audio data rate is multiple/sub-

multiple of 44.1ksps For improvements in EMI performance the class-D amplifier supports programmable Edge rate control (ERC) and class-D clock spread spectrum modulation (SSM). The edge rate of class-D can be controlled using CLASSD_OUTPUT_EDGERATE_CTRL[1:0] register. By default the class-D output edge rate is configured to fastest setting to enable high efficiency in the system. The class-D output edge rate can be slowed down using other configuration settings to reduce the EMI energy at high frequency with reduction in efficiency. The exact rate of change of output edge rate varies based on output load conditions, and the values mentioned in the tables below are approximate edge rate levels for default loading conditions. Table 6-18. Class-D output edge rate control CLASSD_OUTPUT_EDGERATE _CTRL[1:0] Configuration 00 Class-D output edge rate of 0.5 V/ns 01 Class-D output edge rate of 1.0 V/ns 11(default) Class-D output edge rate of 2 V/ns The class-D amplifier has over current protection on each of the output power FETs, including the PVDD High side and the ground power FETs. The class-D amplifier output impedance can be controlled when the outputs stop switching during Noise gate mode using CLASSD_HIZ_MODE control register. Table 6-19. Class-D high-Z mode control CLASSD_HIZ_MODE Configuration 0 (default) Output pulled down with 2.5kΩ

1 Output pulled down with >13kΩ

6.4.2.4 Supply Tracking Limiters with Brown Out Prevention

TAS2320 monitors class-D supply voltage along with the audio signal to automatically decrease gain when the audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time through end of charge battery conditions. The limiter and brown out module calculates the signal attenuation required based on the condition of the signal level, channel gain and the selected supply voltage. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

22 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Signal Level < Limiter threshold BOP ATTACK/ RELEASE LIM_MAX_ATN ATTNUATION APPLIED MIN BOP ATTN BOP ACTIVE PHASE (BOP_GAIN 0dB) PAUSE LIMITER UPDATES Supply Voltage < BOP threshold Figure 6-4. Limiter and Brown out gain attenuation

6.4.2.4.1 Voltage Limiter and Clipping protection

The supply tracking limiter can be configured using LIM_MODE[1:0] register. In the VBAT voltage mode, the limiter tracks the VBAT supply voltage for voltage limiter and in PVDD voltage mode, the limiter tracks the PVDD voltage. Table 6-20. Limiter mode selection LIM_MODE[1:0] Configuration 00 (default) Disabled

01 VBAT voltage based limiter

10 PVDD voltage based limiter

The limiter can be configured to reduce the output signal based on fixed signal threshold level, or it can attenuate signal based on a dynamic threshold which tracks the selected supply voltage. The register bit SUPPLY_HEADROOM_LIM_MODE enables the dynamic supply tracking and can be used to limit the clipping distortion when the supply voltage is varying in the system. Table 6-21. Limiter dynamic supply headroom tracking mode SUPPLY_HEADROOM_LIM_MO DE Configuration 0(default) Disabled Enabled. Limiter threshold is dynamically changed based as a fixed percentage of monitored supply voltage. When SUPPLY_HEADROOM_LIM_MODE is set high, the limiter sets the threshold as a fixed percentage of the monitored supply voltage. The limiter begins reducing gain when the output signal level is greater than the threshold configured. For eg, if voltage limiting is desired to be 10% below the supply voltage, then LIM_SLOPE[23:0] is configured as 0.9 and the threshold is calculated as monitored supply voltage multiplied by 1.1. Similarly if the LIM_SLOPE[23:0] is configured at > 1.0, the limiter threshold is set at higher than the supply voltage, and a small amount of controlled clipping occurs. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

24 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

VSUP (V) Peak Out (V) BOP_TH Brown Out LIM_TH_MAX slope LIM_INF_PT Inflection Point Figure 6-7. Limiter with Inflection Point To achieve a limiter that tracks the selected supply below a threshold, configure the limiter as explained in the previous example, except program the LIM_TH_MIN[23:0] register to the desired minimum threshold. This is shown in Figure 6-8 below. VSUP (V) Peak Out (V) BOP_TH Brown Out LIM_TH_MAX slope LIM_INF_PT Inflection Point LIM_TH_MIN Figure 6-8. Limiter with Inflection Point and Minimum Threshold The limiter has a configurable attack rate (dB/Sample), hold time ( no of samples) and release rate (db/Sample), which are available via the LIM_ATK_RATE[23:0], LIM_HLD_COUNT[23:0], LIM_RLS_RATE[23:0] register bits.

6.4.2.5 Tone Generator

TAS2320 can generate internally a sine tone using an integrated tone generator. This feature can be enabled by configuring the register bit INTERNAL_TONE_GEN_ENZ to low. The tone signal will start playing back on the output by configuring the INTERNAL_TONE_PLAYBACK_EN bit high. When set high, the device will start generating a sine tone based on the programmed TONE_GEN_CNTRL_xx registers. The tone generator can generate any frequency from 16Hz to a maximum frequency of 0.45*Fs, where Fs is the sampling rate of the input digital clocks. The amplitude of the tone signal can also be controlled using the TONE_GEN_CNTRL_xx registers. It is recommended to program the tone frequency and amplitude using the PPC3 Software. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

26 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

The internally generated tone can be mixed with incoming audio stream, or can replace the input audio stream and only tone signal is generated using INTERNAL_TONE_MIXING_EN register. Table 6-22. Internal tone generator mixing options INTERNAL_TONE_MIXING_EN Configuration 0 Only internal tone is generated. 1(default) Internally generated tone is mixed with input audio data and played together. The tone generator can use external clock source like BCLK, or it can be generated using internal oscillator to generate tone signals even with no external clock sources using INTERNAL_TONE_CLK_SEL register. Table 6-23. Internal tone clock source selection INTERNAL_TONE_CLK_SEL Configuration 0 (default) Tone generator uses external clocks

1 Tone generator uses internal

6.4.3 Digital Audio Serial Interface

The device provides a flexible Audio Serial Interface (ASI) port. The port can be configured to support a variety of formats including stereo I 2S, Left Justified, and TDM. Mono audio playback is available via the SDIN pin. The SDOUT pin is used to transmit sample streams including I-sense, V-sense, PVDD voltage, VBAT voltage, die temperature, status and audio for echo reference. The TDM serial audio port supports up to 16 32-bit time slots at 44.1/48 kHz, 8 32-bit time slots at a 88.2/96 kHz sample rate and 4 32-bit time slots at a 176.4/192 kHz sample rate. The device supports 2 time slots at 32 bits in width and 4 or 8 time slots at 16, 24 or 32 bits in width. The device automatically detects the number of time slots and this does not need to be programmed. PCM data sampling rate and SBCLK to FSYNC ratio detected on the TDM bus is reported back on the read-only register bits FS_RATE_DETECTED[2:0] and FS_RATIO_DETECTED[3:0] respectively. Table 6-24. PCM Data Sample Rate Detected FS_RATE_DETECTED[2:0] (Read Only) Setting

000 Reserved

001 14.7kHz / 16kHz 010 22.05kHz / 24kHz 011 29.4kHz / 32kHz 100 (default) 44.1kHz / 48kHz 101 88.2 kHz / 96 kHz 110 176.4 kHz / 192 kHz

111 Error condition

A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge set by the RX_EDGE register bit. The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format and 1 for an I2S format. The RX_SLEN[1:0] register bits set the length of the RX time slot to 16, 24 or 32 (default) bits. The length of the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TAS2320

left justify the audio sample within the time slot by default, but this can be changed to right justification via the RX_JUSTIFY register bit. The device supports mono and stereo down mix playback ([L+R]/2). By default the device will playback mono from the time slot equal to the I 2C base address offset (set by the AD1 and AD2 pins) for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot, right time slot or stereo down mix set by the RX_SLOT_R[3:0] and RX_SLOT_L[3:0] register bits. If time slot selection places reception either partially or fully beyond the frame boundary, the receiver returns a null sample equivalent to a digitally muted sample. The TDM port can transmit a number of sample streams on the SDOUT pin including speaker voltage sense, speaker current sense, interrupts and status, PVDD voltage, VBAT voltage and die temperature. Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin. This can be configured by setting the TX_EDGE register bit. The TX_OFFSET[2:0] register bits define the number SBCLK cycles between the start of a frame and the beginning of time slot 0. This is programmed to 0 for Left Justified format and 1 for I 2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the setting of the TX_FILL register bit. An optional bus keeper can weakly hold the state of SDOUT pin when all devices are driving Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the TX_KEEPEN register bit. The bus keeper can be configured to hold the bus for only 1 LSB or Always (permanent) using TX_KEEPLN register bit. Additionally, the keeper LSB can be driven for a full cycle or half of cycle using TX_KEEPCY register bit. TDM transmit of voltage and current sense values can be enabled using VSNS_TX and ISNS_TX register bits respectively. Each sense stream can be individually enabled or disabled. This is useful to manage limited TDM bandwidth since it may not be necessary to transmit all streams for all devices on the bus. The VSNS_SLOT[5:0], ISNS_SLOT[5:0] for each sense stream defines where the MSB transmission begins. For instance, if VSNS_SLOT is set to 2, the upper 8-bits (MSBs) are transmitted in time slot 2 and the lower 8-bits (LSBs) are transmitted in time slot 3. It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. For instance, if VSNS_SLOT is set to 2 and ISNS_SLOT is set to 3, the lower 8-bits (LSBs) of voltage sense will conflict with the upper 8-bits (MSBs) of current sense. This produces unpredictable transmission results in the conflicting bit slots (for example the priority is not defined). The voltage and current sense values are transmitted at the full 16-bit measured values by default. The IVMON_SLEN[1:0] bits can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits values across multiple slots. The special 12-bit mode is used when only 24-bit I 2S/TDM data can be processed by the host processor. The device needs to be configured with the voltage-sense slot and current-sense slot off by 1 slot and consumes 3 consecutive 8-bit slots. In this mode the device will transmit the first 12 MSB bits followed by the second 12 MSB bits specified by the preceding slot. The device also support monitoring and TDM transmit of input supply voltages. For PVDD slot, enable and length settings PVDD_SLOT[5:0], PVDD_TX and PVDD_SLEN register bits can be use. Similarly for VBAT slot, enable and length settings VBAT_SLOT[5:0], VBAT_TX and VBAT_SLEN register bits can be used. Die temperature can also be transmitted from the device in same manner. Enable and slot settings for Die temperature are done using TEMP_TX and TEMP_SLOT [5:0] register bits. Information about status of slots can be found in STATUS_SLOT[5:0] register bits. STATUS_TX register bit set high enables the status transmit. If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at the frame boundary.

6.4.3.1 Digital Loopback

The device supports loop back feature to loop SDIN data to SDOUT at two levels. When this feature is enabled through TDM_LOOPBACK register bit, loop back is done at the IO Pin level without any ASI data decoding within the device. Other option is to enable the loop back feature through TDM_DESER_LOOPBACK register bit in which case SDIN data first goes through ASI protocol decoding within the device and then sent back via SDOUT. These SDIN to SDOUT loop back options can be useful for board level debug of an audio system. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

28 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Device can also loop back echo reference digital audio data at the end of the internal signal processing blocks like Limiter, BOP etc. through SDOUT signal. This allows audio system to perform noise and echo cancellation algorithms in a host processor that is connected to the device. The echo reference can be enabled by configuring AUDIO_TX register bit. The slot length and the time slot can be selected using AUDIO_SLEN and AUDIO_SLOT[5:0] register bits.

6.4.4 External Class-H Boost Controller

The TAS2320device has implemented Class-H algorithm allowing users to optimize the efficiency in the system by controlling external power supply and maintaining just enough margin to provide high dynamic range without clipping distortions. When enabled, the controller generates PWM signal at device CLH pin with duty cycle proportional to peak voltage on the speaker. Using an external RC filter signal is converted to an analog voltage and can be used to control boost converters with feedback input. The figure below shows how CLH pin can be connected to the external boost control RC network. FB VBST BOOST VBAT CLH IOVDD External Filter Feedback Network RF RF Ro CF CF RFB1 RFB2 RPU Figure 6-9. CLH Pin and External Components By default, the CLH pin has an open drain configuration which allows an easy implementation of a multi-channel control loop using only one RC circuitry in wired-or configuration.

6.4.5 Supply Voltage Monitors

TAS2320 has integrated SAR ADC to monitor the supply voltage pins. The sensed voltages are used for internal device features, protections and can also be streamed out over digital data bus or read through I2C registers. The monitor ADC samples the VBAT pin at higher rate compared to PVDD pin voltage. This sampling speed can be swapped to prioritize PVDD pin sampling rate over VBAT. Table 6-25. Supply monitor sampling rate SUPPLY_SAMPLING_RATE Configuration 0(default) VBAT Sampling rate is higher than PVDD

1 PVDD Sampling rate is higher

The VBAT and PVDD monitored voltages are stored in the register VBAT_CNV and PVDD_CNV and can be read using I2C commands. The supply monitors are also used for voltage protection like VBAT under voltage, PVDD over voltage and under voltage. The voltage protection features monitors the supply voltages, and shuts down the device when the voltage crosses the protection threshold levels. The device also sets the corresponding fault register and can generate an interrupt on IRQZ pin based on configured interrupt Mask register as described in Section 6.3.2. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TAS2320

Once the device is shutdown due to fault condition, the device can be re-powered up using the MODE[1:0] register bits. PVDD over voltage protection is based on the monitored PVDD voltage compared against a programmable threshold which can be controlled using PVDD_OVLO_TH_SEL_EXT . The PVDD Over voltage protection is enabled by default and can be disabled by setting PVDD_OV_DET_DIS bit high.

6.4.6 Thermal Protection

TAS2320 has internal device junction temperature monitor which protects the device against over temperature. When the internal temperature rises above the Over temperature threshold, the device automatically shuts down and sets the Over temperature flag in the corresponding Interrupt registers. The device can automatically retry to power up if OTE_RETRY bit is set high. When set high, the device attempts to re-power up after every RETRY_WAIT_TIME setting (default 1.5 seconds of retry) Along with over temperature protection, the device has thermal warning thresholds to allow for system to raise interrupts or flags as the junction temperature is approaching the shutdown. There are four thermal warning flags available at the internal temperature of 105C, 115C, 125C and 135C. Each thermal warning flag can be independently set to control the Interrupt generation on the IRQZ pad. The minimum temperature and the step size of the temperature warning flag can be programmed using the registers THERMAL_WARN_MIN_TEMP[23:0] and THERMAL_WARN_TEMP_STEP[23:0] The real time internal junction temperature is monitored are stored in the register TMP_CNV and can be read using i2c commands.

6.4.7 Clocks and PLL

In TDM/I2S Mode, the device operates from SBCLK. Table 6-26 below shows the valid SBCLK frequencies for each sample rate and SBCLK to FSYNC ratio. For 44.1kHz based clocking, the same table is applicable with the associated ratio change between 48ksps to 44.1ksps. While the sampling rate of 192kHz is supported, data is internally down-sampled to 96kHz. Therefore audio content greater than 40kHz should not be applied to prevent aliasing. This additionally affects all processing blocks like BOP and limiter which should use 96 kHz fs when accepting 192 kHz audio. If the sample rate is properly configured via the SAMPLE_RATE_CFG bits, no additional configuration is required as long as the SBCLK to FSYNC ratio is valid. The device automatically detects the input PCM FSYNC and BCLK frequency and auto configures itself to playback audio signal. The detected clock rates can be read using the read only registers FS_RATIO_DETECTED and FS_RATE_DETECTED. The device will detect improper SBCLK frequencies and SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts. Table 6-26. Supported SBCLK Frequencies (MHz) (48 kHz based sample rates) Sample Rate (kHz) SBCLK to FSYNC Ratio 16 24 32 48 64 96 128 192 256 384 512 125 250 500

6.4.7.1 Auto clock based wakeup and clock errors

TAS2320 supports flexible operating mode transition from active to shutdown and vice-verse using ASI clock auto detection feature. When MODE[1:0] is configured as '11' the device toggles between Active and Software shutdown state based on valid ASI clock signals applied on the ASI input pins, ie BCLK and FSYNC. If no ASI clocks are detected in this mode, the device remains in software shutdown, with software shutdown mode I Q TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

30 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

on VDD pin, until a valid BCLK and FSYNC clock is detected. Once a valid clock is detected, the device is powered up in active state until the clocks are valid or device is shutdown using software or hardware shutdown commands. The device can detect and raise interrupt flags on detection of incorrect clock configurations based on status of CLK_ERR_PWR_EN. When this bit is set high, the device monitors for activity on the clock pins and flags any error using the latched interrupts status register. The device can also raise interrupts using IRQZ pin based on status of the corresponding interrupt MASK registers. When the error protection bit is enabled, if a clock error is detected, the device will automatically shutdown with proper shutdown sequencing and minimize any clicks and pops due to invalid clocks. When the device is in shutdown state, the clock error detection can be delayed to provide system with time required to settle the input clocks. This power up delay in clock error detection is controlled using an internal pre-power up clock error detection timer configured by CLK_HALT_TIMER. If device doesn't detect a valid clock at the end of the CLK_HALT_TIMER expiry, the Pre-Power-up Clock error is flagged on INT_LTCH4[2] bit, and corresponding interrupt can be generated on IRQZ pin based on status of INT_MASK4[2] bit. When MODE[1:0] is configured as '11' (Wake-up on ASI mode), CLK_HALT_TIMER of '000' is not recommended and it stops the device from entering the software shutdown and increases the VDD IQ while the device is shutdown. Once the device is powered up, the external and internally generated clocks are constantly monitored based on status of CLK_ERR_PWR_EN bit. If enabled, any error in external or internal clock is flagged using the clock error status register INT_LTCH2[3] bit, and corresponding interrupt can be generated on IRQZ pin based on status of INT_MASK2[3]. For system flexibility, the device will also set the error status for the type of detected clock error. The device can also be configured to raise an interrupt on IRQZ pin for any specific type of clock error, instead of using the generic clock error interrupt generation. Table 6-29 below explains the different type of clock errors and corresponding status bits and interrupt MASK register bits. One or more register bits in the table below can be set based on the type of clock error detected. If the device shuts down due to any type of clock error, it can attempt to re-power itself automatically when MODE[1:0] is set to '11'. Table 6-27. Clock Error detection control CLK_ERR_PWR_EN Setting

0 Disabled

1 Enabled (default)

Table 6-28. Clock Halt Timer CLK_HALT_TIMER[2:0] Setting 000 Disabled (infinite time). 001 0.8 ms (default) 010 3.2 ms 011 34.1 ms 100 68.3 ms 101 256 ms 110 768 ms 111 1.3 s Table 6-29. Clock error type description Clock error type Description Status flag register bit IRQZ generation Mask bit Clock error Clock error for any internal or external clocking configuration errors. This bit will be set along with specific clock errors detected in the rest of the table below except for Pre-Power-up Clock errors. INT_LTCH2[3] INT_MASK2[3] www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TAS2320

Table 6-29. Clock error type description (continued) Clock error type Description Status flag register bit IRQZ generation Mask bit Pre-Power-up Clock error Clock error detected during shutdown mode after clock error is detected at end of CLK_HALT_TIMER. INT_LTCH4[2] INT_MASK4[2] Clock ratio change error Clock error detected due to on the fly change in FSYNC to SBCLK ratio. INT_LTCH2[2] INT_MASK2[2] Fs change error Clock error detected due to on the fly change in FSYNC clock frequency INT_LTCH2[1] INT_MASK2[1] Fs invalid error Clock error detected due to incorrect FSYNC clock frequency INT_LTCH2[0] INT_MASK2[0] Frame out of sync Clock error detected due to Frame out of sync INT_LTCH2[5] INT_MASK2[5] Internal PLL Clock error Clock error detected due to internally generated clock frequency error. INT_LTCH2[4] INT_MASK2[4] The device also has a digital watchdog timer which monitors for errors in the internal digital state machine and shuts down the device on detection of such errors. This error can also raise an interrupt on IRQZ pin and flag to the host device of the error state.

6.4.8 Digital IO pins

TAS2320 supports 1.8V and 3.3V IO voltage supply based on the voltage applied on the IOVDD pin. I2S digital input pin has an optional weak pull down to prevent the pin from floating. Pull downs are not enabled during HW shutdown. The pull downs are disabled by default and can be enabled by setting the corresponding Pull down enable bit high. Table 6-30. Digital pin weak pull down Pin Name Pull down control register name SDOUT SDOUT_PD_EN SDIN SDIN_PD_EN FSYNC FSYNC_PD_EN SBCLK SBCLK_PD_EN

6.5 Programming

The device contains configuration registers and programming coefficients that can be set to the desired values for a specific system and application use. These registers are called device control registers and are each eight bits in width, mapped using a page scheme. Each page contains 128 configuration registers. All key device configuration registers are stored in page 0, which is the default page setting at power up and after a software reset. All programmable coefficient registers are located in page 2, page 3 and later pages. The current page of the device can be switched to a new desired page by using the PAGE[7:0] bits located in register 0 of every page.

6.5.1 I2C Control Interface

The device supports the I 2C control protocol as a target device, and is capable of operating in standard mode, fast mode, and fast mode plus. Device configuration and status are provided via the SDA and SCL pins using the I2C protocol.

6.5.2 I2C Address Selection

The TAS2320 can operate using one of four selectable device addresses. I 2C target addresses is defined as the 7 MSBs followed by read/write bit. Table 6-31 below illustrates how to select the device I 2C address and TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

32 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

the address corresponds to R/W bit set to 0 (ie ADDR[6:0],1b'0). The I 2C address is detected by sampling the address pins when SDZ pin is released or when device is reset using software reset bit. Table 6-31. I2C Mode Address Selection I2C TARGET ADDRESS ADDR PIN 0x80 (global address) NA 0x90 Short to GND 0x92 24k to GND 0x94 24k to IOVDD 0x96 Connect to IOVDD The TAS2320 has a global 7-bit I 2C address 0x40 (0x80 in 8-bit format with R/W bit set to 0). When enabled the device will additionally respond to I 2C commands at this address regardless of the address pins selected . This is used to speed up device configuration when using multiple TAS2320 devices and programming similar settings across all devices. The I 2C ACK / NACK cannot be used during the multi-device writes since multiple devices are responding to the I 2C command. The I 2C CRC function should be used to ensure each device properly received the I2C commands. At the completion of writing multiple devices using the global address, the CRC at I2C_CKSUM register should be checked on each device using the local address for a proper value. The global I2C address can be disabled using I2C_GBL_EN register. Table 6-32. I2C Global Address Enable I2C_GBL_EN SETTING

6.5.3 General I2C Operation

The I 2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system using serial data transmission. The address and data 8-bit bytes are transferred MSB first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the controller device driving a start condition on the bus and ends with the controller device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. The controller device drives a start condition followed by the 7-bit target address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledgment condition. The target device holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the controller device transmits the next byte of the sequence. Each target device is addressed by a unique 7-bit target address plus the R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TAS2320

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the controller device generates a stop condition to release the bus. Figure 6-10 shows a generic data transfer sequence. Register□(N) 8-□Bit□Data□for 8-□Bit□Data□for Register□(N+1) Figure 6-10. Typical I2C Sequence In the system, use external pullup resistors for the SDA and SCL signals to set the logic high level for the bus. The SDA and SCL voltages must not exceed the device supply voltage, IOVDD.

6.5.4 I2C Single-Byte and Multiple-Byte Transfers

The device I 2C interface supports both single-byte and multiple-byte read/write operations for all registers. During multiple-byte read operations, the device responds with data, a byte at a time, starting at the register assigned, as long as the controller device continues to respond with acknowledges. The device supports sequential I 2C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I 2C write transaction takes place. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many registers are written.

6.5.5 I2C Single-Byte Write

As shown in Figure 6-11, a single-byte data write transfer begins with the controller device transmitting a start condition followed by the I 2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I 2C target address and the read/write bit, the device responds with an acknowledge bit (ACK). Next, the controller device transmits the register byte corresponding to the device internal register address being accessed. After receiving the register byte, the device again responds with an acknowledge bit (ACK). Then, the controller transmits the byte of data to be written to the specified register. When finished, the target device responds with an acknowledge bit (ACK). Finally, the controller device transmits a stop condition to complete the single-byte data write transfer. A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I2C□Device□Address□and Read/Write□Bit Register Data□□Byte Figure 6-11. I2C Single-Byte Write Transfer TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

34 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

6.5.6 I2C Multiple-Byte Write

As shown in Figure 6-12, a multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the controller device to the target device. After receiving each data byte, the device responds with an acknowledge bit (ACK). Finally, the controller device transmits a stop condition after the last data-byte write transfer. Register Figure 6-12. I2C Multiple-Byte Write Transfer

6.5.7 I2C Single-Byte Read

As shown in Figure 6-13, a single-byte data read transfer begins with the controller device transmitting a start condition followed by the I 2C target address and the read/write bit. For the data read transfer, both a write followed by a read are done. Initially, a write is done to transfer the address byte of the internal register address to be read. As a result, the read/write bit is set to 0. After receiving the target address and the read/write bit, the device responds with an acknowledge bit (ACK). The controller device then sends the internal register address byte, after which the device issues an acknowledge bit (ACK). The controller device transmits another start condition followed by the target address and the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the device transmits the data byte from the register address being read. After receiving the data byte, the controller device transmits a not-acknowledge (NACK) followed by a stop condition to complete the single-byte data read transfer. A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I2C□Device□Address□and Read/Write□Bit Register Data□Byte D7 D6 D1 D0 ACK I2C□Device□Address□and Read/Write□Bit Not Acknowledge R/WA1 A1 Repeat□Start Condition Figure 6-13. I2C Single-Byte Read Transfer

6.5.8 I2C Multiple-Byte Read

As shown in Figure 6-14, a multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the device to the controller device. With the exception of the last data byte, the controller device responds with an acknowledge bit after receiving each data byte. After receiving the last data byte, the controller device transmits a not-acknowledge (NACK) followed by a stop condition to complete the data read transfer. A6 A0 ACK Acknowledge I2C□Device□Address□and Read/Write□Bit R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge Last□Data□Byte ACK First□Data□Byte Repeat□Start Condition Not Acknowledge I2C□Device□Address□and Read/Write□Bit Register Other□Data□Bytes A7 A6 A5 D7 D0 ACK Acknowledge D7 D0 Figure 6-14. I2C Multiple-Byte Read Transfer www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TAS2320

7 Register Maps

The TAS2320device registers are organized into pages and books. The registers from Page 0 to Page 8 are all in Book 0, while the registers in Page 9 are in Book 100. The register map book number can be changed by programming the BOOK[7:0] register bit, and page number can be changed by programing PAGE[7:0] register bits. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

36 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

7.1 PAGE 0 Registers

Table 7-1 lists the memory-mapped registers for the PAGE 0 registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified. Table 7-1. PAGE 0 Registers Address Acronym Description Section 0h Page Device Page Section 7.1.1 1h SW_RESET Software Reset Section 7.1.2 2h PWR_CTL Power Control Section 7.1.3 3h DEVICE_CFG_01 Device configuration registers Section 7.1.4 4h DEVICE_CFG_02 Device configuration registers Section 7.1.5 5h DEVICE_CFG_03 Device configuration registers Section 7.1.6 6h DEVICE_CFG_04 Device configuration registers Section 7.1.7 7h DEVICE_CFG_05 Device configuration registers Section 7.1.8 8h TDM_CFG1 TDM Configuration registers Section 7.1.9 9h TDM_CFG2 TDM Configuration registers Section 7.1.10 Ah TDM_CFG3 TDM Configuration registers Section 7.1.11 Ch TDM_CFG5 TDM Configuration registers Section 7.1.12 10h TDM_CFG9 TDM Configuration registers Section 7.1.13 11h TDM_CFG10 TDM Configuration registers Section 7.1.14 12h TDM_CFG11 TDM Configuration registers Section 7.1.15 13h TDM_CFG12 TDM Configuration registers Section 7.1.16 14h TDM_DET TDM Clock detection monitor Section 7.1.17 18h BOP_CFG_0 Brown out protection configuration Section 7.1.18 1Ch IO_CFG_02 IO Configuration Section 7.1.19 1Dh IO_CFG_03 IO Configuration Section 7.1.20 1Eh NG_CFG0 Noise Gate Controls Section 7.1.21 25h INTERRUPT_CFG1 IRQZ clear Section 7.1.22 28h SAR_MONITOR_03 PVDD Monitor MSB Section 7.1.23 29h SAR_MONITOR_04 PVDD Monitor MSB Section 7.1.24 2Ah SAR_MONITOR_06 Temperature monitor Section 7.1.25 31h CLASSD_CFG_01 ClassD amp configurations Section 7.1.26 32h CLASSD_CFG_02 ClassD amp configurations Section 7.1.27 3Ch THERM_CFG Thermal warning configuration Section 7.1.28 5Bh INT_MASK_0 Interrupt Masks Section 7.1.29 5Ch INT_MASK_1 Interrupt Masks Section 7.1.30 5Dh INT_MASK_2 Interrupt Masks Section 7.1.31 5Eh INT_MASK_3 Interrupt Masks Section 7.1.32 5Fh INT_MASK_4 Interrupt Masks Section 7.1.33 60h INT_LATCH_0 Latched interrupt readback Section 7.1.34 61h INT_LATCH_1 Latched interrupt readback Section 7.1.35 62h INT_LATCH_2 Latched interrupt readback Section 7.1.36 63h INT_LATCH_3 Latched interrupt readback Section 7.1.37 64h INT_LATCH_4 Latched interrupt readback Section 7.1.38 65h NG_IDLE_STATUS Latched interrupt readback Section 7.1.39 78h REV_ID Revision ID Section 7.1.40 7Fh BOOK Device Book Section 7.1.41 www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TAS2320

7.1.1 Page Register (Address = 0h) [Reset = 00h]

Return to the Summary Table. The device's memory map is divided into pages and books. This register sets the page. Table 7-2. Page Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.1.2 SW_RESET Register (Address = 1h) [Reset = 00h]

Return to the Summary Table. Asserting Software Reset will place all register values in their default POR (Power on Reset) state. Table 7-3. SW_RESET Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h Reserved 0 SW_RESET R/W 0h Software reset. Bit is self clearing. 0h = Don't reset 1h = Reset

7.1.3 PWR_CTL Register (Address = 2h) [Reset = 03h]

Return to the Summary Table. Sets device's mode of operation and Power Configuration. Table 7-4. PWR_CTL Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h Reserved 1-0 MODE[1:0] R/W 3h Device operational mode. 0h = Active 1h = Reserved 2h = Software Shutdown 3h = Wake-up and Shutdown on ASI Clock

7.1.4 DEVICE_CFG_01 Register (Address = 3h) [Reset = 81h]

Return to the Summary Table. This register configures various device modes. Table 7-5. DEVICE_CFG_01 Register Field Descriptions Bit Field Type Reset Description 7-6 EFFICIENCY_MODE[1:0] R/W 2h Device operational mode. 0h = Music Efficiency and Noise Gate mode disabled 1h = Noise Gate Mode Only 2h = Music Efficiency Only 3h = Music Efficiency and Noise Gate mode 5-2 RESERVED R 0h Reserved TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

38 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-5. DEVICE_CFG_01 Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 SDZ_MODE[1:0] R/W 1h SDZ Mode configuration. 0h = Soft shutdown and device reset 1h = Immediate shutdown and device reset 2h = Soft shutdown only 3h = Reserved

7.1.5 DEVICE_CFG_02 Register (Address = 4h) [Reset = 8Ch]

Return to the Summary Table. This register configures various device modes. Table 7-6. DEVICE_CFG_02 Register Field Descriptions Bit Field Type Reset Description 7 I2C_GBL_EN R/W 1h I2C global address. 0h = Disabled 1h = Enabled

6 RESERVED R/W 0h Reserved

5-3 CLK_HALT_TIME[2:0] R/W 1h Pre-power-up valid clock checking time duration. 0h = Disabled (infinite time) 1h = 800 us 2h = 3.2 ms 3h = 34.1 ms 4h = 68.3 ms 5h = 256 ms 6h = 768 ms 7h = 1.3 s 2 CLK_BASED_PWR_UP R/W 1h Clock error detection enable/disable. 0h = Disable 1h = Enabled

1 RESERVED R/W 0h Reserved

0 RESERVED R/W 0h Reserved

7.1.6 DEVICE_CFG_03 Register (Address = 5h) [Reset = 00h]

Return to the Summary Table. This register configures various device modes. Table 7-7. DEVICE_CFG_03 Register Field Descriptions Bit Field Type Reset Description

7 RESERVED R/W 0h Reserved

5 RESERVED R/W 0h Reserved

4 OTE_RETRY R/W 0h Retry after over temperature event. 0h = Do not retry 1h = Retry after "RETRY_WAIT_TIME"

3 RESERVED R/W 0h Reserved

2 CLKE_RETRY R/W 0h Retry after Internal Clock Error event. 0h = Do not retry 1h = Retry after "RETRY_WAIT_TIME" www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TAS2320

7.1.7 DEVICE_CFG_04 Register (Address = 6h) [Reset = 04h]

Return to the Summary Table. This register configures various device modes. Table 7-8. DEVICE_CFG_04 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h Reserved 5-4 RESERVED R 0h Reserved 3-2 IRQZ_PIN_CFG[1:0] R/W 1h IRQZ interrupt configuration. IRQZ will assert. 0h = Reserved 1h = on any unmasked latched interrupts 2h = Reserved 3h = for 2-4ms every 4ms on any unmasked latched interrupts

1 RESERVED R 0h Reserved

0 RETRY_WAIT_TIME R/W 0h Retry wait time after device detects error (Valid only for errors with

retry options available). 0h = 1.5 sec 1h = 100ms

7.1.8 DEVICE_CFG_05 Register (Address = 7h) [Reset = 00h]

Return to the Summary Table. This register configures various device modes. Table 7-9. DEVICE_CFG_05 Register Field Descriptions Bit Field Type Reset Description

7 RESERVED R 0h Reserved

6 SAMPLE_RATE_CFG R/W 0h Sampling Rate selection. 0h = Audio data rate is multiple/sub-multiple of 48 Ksps 1h = Audio data rate is multiple/sub-multiple of 44.1 Ksps 5-0 AMP_LVL[5:0] R/W 0h Device Channel Gain setting 0h = 21.000dB 1h = 20.498dB 2h = 19.997dB 3h = 19.495dB 4h = 18.993dB 26h = 1.935dB 27h = 1.434dB 28h = 0.932dB 29h = 0.430dB 2Ah = -0.071dB

7.1.9 TDM_CFG1 Register (Address = 8h) [Reset = 82h]

Return to the Summary Table. This register configures device TDM modes. Table 7-10. TDM_CFG1 Register Field Descriptions Bit Field Type Reset Description 7 FRAME_START R/W 1h TDM frame start polarity. 0h = Low to High on FSYNC 1h = High to Low on FSYNC 6 RX_JUSTIFY R/W 0h TDM RX sample justification within the time slot. 0h = Left 1h = Right 5-1 RX_OFFSET[4:0] R/W 1h TDM RX start of frame to time slot 0 offset (SBCLK cycles). TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

40 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-10. TDM_CFG1 Register Field Descriptions (continued) Bit Field Type Reset Description 0 RX_EDGE R/W 0h TDM RX capture clock polarity. 0h = Rising edge of SBCLK 1h = Falling edge of SBCLK

7.1.10 TDM_CFG2 Register (Address = 9h) [Reset = 0Ah]

Return to the Summary Table. This register configures device TDM modes. Table 7-11. TDM_CFG2 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h Reserved 5-4 RX_SCFG[1:0] R/W 0h TDM RX time slot select config. 0h = Mono with time slot equal to I2C address offset 1h = Mono left channel 2h = Mono right channel 3h = Stereo downmix (L+R)/2 3-2 RX_WLEN[1:0] R/W 2h TDM RX word length. 0h = 16 bits 1h = 20 bits 2h = 24 bits 3h = 32 bits 1-0 RX_SLEN[1:0] R/W 2h TDM RX time slot length. 0h = 16 bits 1h = 24 bits 2h = 32 bits 3h = Reserved

7.1.11 TDM_CFG3 Register (Address = Ah) [Reset = 10h]

Return to the Summary Table. This register configures device TDM modes. Table 7-12. TDM_CFG3 Register Field Descriptions Bit Field Type Reset Description 7-4 RX_SLOT_R[3:0] R/W 1h TDM RX Right Audio Channel Time Slot. 3-0 RX_SLOT_L[3:0] R/W 0h TDM RX Left Audio Channel Time Slot.

7.1.12 TDM_CFG5 Register (Address = Ch) [Reset = 13h]

Return to the Summary Table. This register configures device TDM modes. Table 7-13. TDM_CFG5 Register Field Descriptions Bit Field Type Reset Description

7 TX_KEEPCY R/W 0h TDM TX SDOUT LSB data will be driven for

0h = full-cycle 1h = half-cycle

6 TX_KEEPLN R/W 0h TDM TX SDOUT will hold the bus for the following when

TX_KEEPEN is enabled 0h = 1 LSB cycle 1h = always www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TAS2320

Table 7-13. TDM_CFG5 Register Field Descriptions (continued) Bit Field Type Reset Description 5 TX_KEEPEN R/W 0h TDM TX SDOUT bus keeper enable. 0h = Disable bus keeper 1h = Enable bus keeper 4 TX_FILL R/W 1h TDM TX SDOUT unused bitfield fill. 0h = Transmit 0 1h = Transmit Hi-Z 3-1 TX_OFFSET[2:0] R/W 1h TDM TX start of frame to time slot 0 offset. 0 TX_EDGE R/W 1h TDM TX launch clock polarity. 0h = Rising edge of SBCLK 1h = Falling edge of SBCLK

7.1.13 TDM_CFG9 Register (Address = 10h) [Reset = 05h]

Return to the Summary Table. This register configures device TDM modes. Table 7-14. TDM_CFG9 Register Field Descriptions Bit Field Type Reset Description 6 TEMP_TX R/W 0h TDM TX temp sensor transmit enable. 0h = Disabled 1h = Enabled 5-0 TEMP_SLOT[5:0] R/W 5h TDM TX temp sensor time slot.

7.1.14 TDM_CFG10 Register (Address = 11h) [Reset = 07h]

Return to the Summary Table. This register configures device TDM modes Table 7-15. TDM_CFG10 Register Field Descriptions Bit Field Type Reset Description 6 STATUS_TX R/W 0h TDM TX status bits transmit enable. 0h = Disabled 1h = Enabled 5-0 STATUS_SLOT[5:0] R/W 7h TDM TX status bits time slot.

7.1.15 TDM_CFG11 Register (Address = 12h) [Reset = 06h]

Return to the Summary Table. This register configures device TDM modes. Table 7-16. TDM_CFG11 Register Field Descriptions Bit Field Type Reset Description 7 PVDD_SLEN R/W 0h TDM TX PVDD time slot length. 0h = Truncate to 8-bits 1h = Left justify to 16-bits 6 PVDD_TX R/W 0h TDM TX PVDD transmit enable. 0h = Disabled 1h = Enabled TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

42 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-16. TDM_CFG11 Register Field Descriptions (continued) Bit Field Type Reset Description 5-0 PVDD_SLOT[5:0] R/W 6h TDM TX PVDD time slot.

7.1.16 TDM_CFG12 Register (Address = 13h) [Reset = 12h]

Return to the Summary Table. This register configures device TDM modes. Table 7-17. TDM_CFG12 Register Field Descriptions Bit Field Type Reset Description

7 AUDIO_SLEN R/W 0h TDM audio slot length

0h = 16-bits 1h = 24-bits

6 AUDIO_TX R/W 0h TDM audio output transmit is

0h = Disabled 1h = Enabled 5-0 AUDIO_SLOT[5:0] R/W 12h TDM TX status time slot.

7.1.17 TDM_DET Register (Address = 14h) [Reset = 7Fh]

Return to the Summary Table. Readback of internal auto clock detection. Table 7-18. TDM_DET Register Field Descriptions Bit Field Type Reset Description 6-3 FS_RATIO_DETECTED[3: R Fh Detected SBCLK to FSYNC ratio. 0h = 16 1h = 24 2h = 32 3h = 48 4h = 64 5h = 96 6h = 128 7h = 192 8h = 256 9h = 384 Ah = 512 Bh = 250 Dh = 500 Eh = Reserved Fh = Invalid ratio 2-0 FS_RATE_DETECTED[2: R 7h Detected sample rate of TDM bus. 0h = Reserved 1h = 14.7/16 KHz 2h = 22.05/24 KHz 3h = 29.4/32 KHz 4h = 44.1/48 KHz 5h = 88.2/96 kHz 6h = 176.4/192 kHz 7h = Error condition

7.1.18 BOP_CFG_0 Register (Address = 18h) [Reset = 00h]

Return to the Summary Table. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TAS2320

This register configures brown out protection module. Table 7-19. BOP_CFG_0 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h Reserved

4 BOP_SRC R/W 0h Brown out prevention Source control

0h = VBAT 1h = PVDD 3 BOPSD_EN R/W 0h Brown out prevention shutdown enable. 0h = Disabled 1h = Enabled 2 BOP_HLD_CLR R/W 0h BOP infinite hold clear (self clearing). Available when BOP_INF_HLD = 1 0h = Don't clear 1h = Clear 1 BOP_INF_HLD R/W 0h Infinite hold on brown out event. 0h = Use BOP_HLD_TM after brown out event 1h = Don't release until BOP_HLD_CLR is asserted high 0 BOP_EN R/W 0h Brown out prevention (BOP) enable. 0h = Disabled 1h = Enabled

7.1.19 IO_CFG_02 Register (Address = 1Ch) [Reset = 3Fh]

Return to the Summary Table. This register configures the IO buffers. Table 7-20. IO_CFG_02 Register Field Descriptions Bit Field Type Reset Description 7 IRQZ_POL R/W 0h IRQZ pin polarity for interrupt. 0h = Active Low 1h = Active High

6 RESERVED R 0h Reserved

5 RESERVED R/W 1h Reserved

4 IRQZ_PD R/W 1h Weak pull down for IRQZ. 0h = Disabled 1h = Enabled

3 RESERVED R/W 1h Reserved

2 RESERVED R/W 1h Reserved

1 SDZ_PD R/W 1h Weak pull down for SDZ. 0h = Disabled 1h = Enabled 0 SDA_PD R/W 1h Weak pull down for SDA. 0h = Disabled 1h = Enabled

7.1.20 IO_CFG_03 Register (Address = 1Dh) [Reset = F0h]

Return to the Summary Table. This register configures the IO buffers. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

44 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-21. IO_CFG_03 Register Field Descriptions Bit Field Type Reset Description 7 ADR_PD R/W 1h Weak pull down for ADR. 0h = Disabled 1h = Enabled 6 SDZ_PD R/W 1h Weak pull down for SDZ. 0h = Disabled 1h = Enabled 4 CLH_PD R/W 1h Weak pull down for CLH. 0h = Disabled 1h = Enabled 3 SDOUT_PD R/W 0h Weak pull down for SDOUT. 0h = Disabled 1h = Enabled 2 SDIN_PD R/W 0h Weak pull down for SDIN. 0h = Disabled 1h = Enabled 1 FSYNC_PD R/W 0h Weak pull down for FSYNC. 0h = Disabled 1h = Enabled 0 SBCLK_PD R/W 0h Weak pull down for SBCLK. 0h = Disabled 1h = Enabled

7.1.21 NG_CFG0 Register (Address = 1Eh) [Reset = 60h]

Return to the Summary Table. Noise gate hysteresis, threshold level, and enable. Table 7-22. NG_CFG0 Register Field Descriptions Bit Field Type Reset Description 7-6 NG_HYST_TIMER[1:0] R/W 1h Noise Gate Entry hysteris timer. 0h = 10ms 1h = 50ms 2h = 100ms 3h = 1000ms 5-3 NG_TH_LVL[2:0] R/W 4h Noise-gate audio threshold level. 0h = -85 dBFS 1h = -90 dBFS 2h = -95 dBFS 3h = -100 dBFS 4h = -105 dBFS 5h = -110 dBFS 6h = -115 dBFS 7h = -120 dBFS 2-0 RESERVED R 0h Reserved

7.1.22 INTERRUPT_CFG1 Register (Address = 25h) [Reset = 00h]

Return to the Summary Table. This register clears all the latched interrupt registers. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: TAS2320

Table 7-23. INTERRUPT_CFG1 Register Field Descriptions Bit Field Type Reset Description

7 Shared_boost_primary_en R/W 0h Primary device control in shared boost mode

0h = Disabled 1h = Enabled

6 Shared_boost_secondary

_en R/W 0h Secondary device control in shared boost mode 0h = Disabled 1h = Enabled 5-2 RESERVED R 0h Reserved 1 INT_CLR_LTCH R/W 0h Clear INT_LTCH registers. 0h = Don't clear 1h = Clear

0 RESERVED R 0h Reserved

7.1.23 SAR_MONITOR_03 Register (Address = 28h) [Reset = 00h]

Return to the Summary Table. This register provides sensed VBAT Voltage. Table 7-24. SAR_MONITOR_03 Register Field Descriptions Bit Field Type Reset Description 7-0 PVDD_CNV_MSB[7:0] R 0h Returns the SAR ADC PVDD monitored voltage MSBs.

7.1.24 SAR_MONITOR_04 Register (Address = 29h) [Reset = 00h]

Return to the Summary Table. This register provides sensed VBAT Voltage. Table 7-25. SAR_MONITOR_04 Register Field Descriptions Bit Field Type Reset Description 7-4 PVDD_CNV_LSB[3:0] R 0h Returns the SAR ADC PVDD monitored voltage LSBs. 3-0 RESERVED R 0h Reserved

7.1.25 SAR_MONITOR_06 Register (Address = 2Ah) [Reset = 00h]

Return to the Summary Table. This register provides sensed temperature. Table 7-26. SAR_MONITOR_06 Register Field Descriptions Bit Field Type Reset Description 7-0 TMP_CNV[7:0] R 0h Returns the SAR ADC Temperature monitored data.

7.1.26 CLASSD_CFG_01 Register (Address = 31h) [Reset = 04h]

Return to the Summary Table. This register configures the class-D amplifier. Table 7-27. CLASSD_CFG_01 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h Reserved TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

46 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-27. CLASSD_CFG_01 Register Field Descriptions (continued) Bit Field Type Reset Description 5-4 CLASSD_OUTPUT_EDG ERATE_CTRL[1:0] R/W 0h Edgerate programmability control. 0h = Class-D output edge rate of approximately 0.5 V/ns 1h = Class-D output edge rate of approximately 1 V/ns 2h = Reserved 3h = Class-D output edge rate of approximately 2 V/ns

3 CLASSD_HIZ_MODE R/W 0h Amp output state in Noise gate mode (0 = Not Hi-Z, 1 = Hi-Z)

0h = Disabled 1h = Enabled 1-0 RESERVED R 0h Reserved

7.1.27 CLASSD_CFG_02 Register (Address = 32h) [Reset = 9Ch]

Return to the Summary Table. This register configures the class-D amplifier. Table 7-28. CLASSD_CFG_02 Register Field Descriptions Bit Field Type Reset Description

7 EN_Y_BRIDGE_MODE R/W 1h Enable/Disable VDD Bridge mode during device operation

0h = VDD Bridge mode disabled 1h = VDD Bridge mode enabled 5-4 RESERVED R/W 1h Reserved 3-2 Ybridge_hyst_timer[1:0] R/W 3h Time hysteresis programability 0h = 100 us 1h = 500 us 2h = 5 ms 3h = 50 ms 1-0 RESERVED R 0h Reserved

7.1.28 THERM_CFG Register (Address = 3Ch) [Reset = 00h]

Return to the Summary Table. This register configures thermal warning detection. Table 7-29. THERM_CFG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h Reserved 0 EN_THERM_WARN_DET R/W 0h Enable control for thermal warning detection feature. 0h = Disabled 1h = Enabled

7.1.29 INT_MASK_0 Register (Address = 5Bh) [Reset = 03h]

Return to the Summary Table. This register configures Masks for Interrupt flags. Table 7-30. INT_MASK_0 Register Field Descriptions Bit Field Type Reset Description 7 INT_MASK0[7] R/W 0h Mask for Interrupt due to BOP Inf Hold flag. 0h = Don't Mask 1h = Mask www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: TAS2320

Table 7-30. INT_MASK_0 Register Field Descriptions (continued) Bit Field Type Reset Description 6 INT_MASK0[6] R/W 0h Mask for Interrupt due to limiter attentuation flag. 0h = Don't Mask 1h = Mask 5 INT_MASK0[5] R/W 0h Mask for Interrupt due to supply less than inf pt flag. 0h = Don't Mask 1h = Mask 4 INT_MASK0[4] R/W 0h Mask for Interrupt due to limiter active flag. 0h = Don't Mask 1h = Mask 3 INT_MASK0[3] R/W 0h Mask for Interrupt due to brownout detected flag. 0h = Don't Mask 1h = Mask 2 INT_MASK0[2] R/W 0h Mask for Interrupt due to bop active flag. 0h = Don't Mask 1h = Mask 1 INT_MASK0[1] R/W 1h Mask for Interrupt due to device active flag. 0h = Don't Mask 1h = Mask

0 RESERVED R/W 1h Reserved

7.1.30 INT_MASK_1 Register (Address = 5Ch) [Reset = 1Fh]

Return to the Summary Table. This register configures Masks for Interrupt flags. Table 7-31. INT_MASK_1 Register Field Descriptions Bit Field Type Reset Description 7 INT_MASK1[7] R/W 0h Mask for Interrupt due to PVDD Under voltage. 0h = Don't Mask 1h = Mask

4 INT_MASK1[4] R/W 1h Mask for Interrupt due to Thermal Warning 135C

0h = Don't Mask 1h = Mask

3 INT_MASK1[3] R/W 1h Mask for Interrupt due to Thermal Warning 125C

0h = Don't Mask 1h = Mask

2 INT_MASK1[2] R/W 1h Mask for Interrupt due to Thermal Warning 115C

0h = Don't Mask 1h = Mask

1 INT_MASK1[1] R/W 1h Mask for Interrupt due to Thermal Warning 105C

0h = Don't Mask 1h = Mask

7.1.31 INT_MASK_2 Register (Address = 5Dh) [Reset = 2Fh]

Return to the Summary Table. This register configures Masks for Interrupt flags. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

48 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-32. INT_MASK_2 Register Field Descriptions Bit Field Type Reset Description

7 INT_MASK2[7] R/W 0h Mask for Interrupt due to watchdog expiry

0h = Don't Mask 1h = Mask

5 INT_MASK2[5] R/W 1h Mask for Interrupt due to frame out of sync

0h = Don't Mask 1h = Mask

4 INT_MASK2[4] R/W 0h Mask for Interrupt due to PLL clock error

0h = Don't Mask 1h = Mask

3 INT_MASK2[3] R/W 1h Mask for Interrupt due to tdm error

0h = Don't Mask 1h = Mask

2 INT_MASK2[2] R/W 1h Mask for Interrupt due to ratio change error flag

0h = Don't Mask 1h = Mask

1 INT_MASK2[1] R/W 1h Mask for Interrupt due to fs change error flag

0h = Don't Mask 1h = Mask

0 INT_MASK2[0] R/W 1h Mask for Interrupt due to invalid ratio fs flag

0h = Don't Mask 1h = Mask

7.1.32 INT_MASK_3 Register (Address = 5Eh) [Reset = 10h]

Return to the Summary Table. This register configures Masks for Interrupt flags. Table 7-33. INT_MASK_3 Register Field Descriptions Bit Field Type Reset Description

7 INT_MASK3[7] R/W 0h Mask for Interrupt due to over temperature detected

0h = Don't Mask 1h = Mask

4 RESERVED R/W 1h Reserved

3 INT_MASK3[3] R/W 0h Mask for Interrupt due to Class-D Over current protection

0h = Don't Mask 1h = Mask

2 INT_MASK3[2] R/W 0h Mask for Interrupt due to pvdd_ov_flag

0h = Don't Mask 1h = Mask

7.1.33 INT_MASK_4 Register (Address = 5Fh) [Reset = 0Ah]

Return to the Summary Table. This register configures Masks for Interrupt flags. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: TAS2320

Table 7-34. INT_MASK_4 Register Field Descriptions Bit Field Type Reset Description

7 INT_MASK4[7] R/W 0h Mask for Interrupt due to vbat_por

0h = Don't Mask 1h = Mask

4 RESERVED R/W 0h Reserved

2 INT_MASK4[2] R/W 0h Mask for Interrupt due to clock halt flag. This interrupt also flags errors due to Pre-power-up clock error while using Wake-up-on-ASI feature 0h = Don't Mask 1h = Mask

1 RESERVED R/W 1h Reserved

7.1.34 INT_LATCH_0 Register (Address = 60h) [Reset = 00h]

Return to the Summary Table. This register provides the status of latched interrupts. Table 7-35. INT_LATCH_0 Register Field Descriptions Bit Field Type Reset Description

7 INT_LTCH0[7] R 0h Interrupt due to BOP Inf Hold flag

0h = No interrupt 1h = Interrupt

6 INT_LTCH0[6] R 0h Interrupt due to limiter attentuation flag

0h = No interrupt 1h = Interrupt

5 INT_LTCH0[5] R 0h Interrupt due to supply less than inf pt flag

0h = No interrupt 1h = Interrupt

4 INT_LTCH0[4] R 0h Interrupt due to limiter active flag

0h = No interrupt 1h = Interrupt

3 INT_LTCH0[3] R 0h Interrupt due to brownout detected flag

0h = No interrupt 1h = Interrupt

2 INT_LTCH0[2] R 0h Interrupt due to bop active flag

0h = No interrupt 1h = Interrupt

1 INT_LTCH0[1] R 0h Live Interrupt due to device active flag

0h = No interrupt 1h = Interrupt

7.1.35 INT_LATCH_1 Register (Address = 61h) [Reset = 00h]

Return to the Summary Table. This register provides the status of latched interrupts. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

50 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-36. INT_LATCH_1 Register Field Descriptions Bit Field Type Reset Description

7 INT_LTCH1[7] R 0h Interrupt due to PVDD under voltage detection

0h = No interrupt 1h = Interrupt

5 RESERVED R 0h Reserved

4 INT_LTCH1[4] R 0h Interrupt due to Thermal Warning 135C

0h = No interrupt 1h = Interrupt

3 INT_LTCH1[3] R 0h Interrupt due to Thermal Warning 125C

0h = No interrupt 1h = Interrupt

2 INT_LTCH1[2] R 0h Interrupt due to Thermal Warning 115C

0h = No interrupt 1h = Interrupt

1 INT_LTCH1[1] R 0h Interrupt due to Thermal Warning 105C

0h = No interrupt 1h = Interrupt

7.1.36 INT_LATCH_2 Register (Address = 62h) [Reset = 00h]

Return to the Summary Table. This register provides the status of latched interrupts. Table 7-37. INT_LATCH_2 Register Field Descriptions Bit Field Type Reset Description

7 INT_LTCH2[7] R 0h Interrupt due to watchdog expiry

0h = No interrupt 1h = Interrupt

5 INT_LTCH2[5] R 0h Interrupt due to frame out of sync

0h = No interrupt 1h = Interrupt

4 INT_LTCH2[4] R 0h Interrupt due to PLL clock error

0h = No interrupt 1h = Interrupt

3 INT_LTCH2[3] R 0h Interrupt due to tdm error

0h = No interrupt 1h = Interrupt

2 INT_LTCH2[2] R 0h Interrupt due to ratio change error flag

0h = No interrupt 1h = Interrupt

1 INT_LTCH2[1] R 0h Interrupt due to fs change error flag

0h = No interrupt 1h = Interrupt

0 INT_LTCH2[0] R 0h Interrupt due to invalid ratio fs flag

0h = No interrupt 1h = Interrupt

7.1.37 INT_LATCH_3 Register (Address = 63h) [Reset = 00h]

Return to the Summary Table. This register provides the status of latched interrupts. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: TAS2320

Table 7-38. INT_LATCH_3 Register Field Descriptions Bit Field Type Reset Description

7 INT_LTCH3[7] R 0h Interrupt due to over temperature detected

0h = No interrupt 1h = Interrupt

4 RESERVED R 0h Reserved

3 INT_LTCH3[3] R 0h Interrupt due to Class-D Over current protection

0h = No interrupt 1h = Interrupt 2 INT_LTCH3[2] R 0h Interrupt due to Over voltage on PVDD supply. 0h = No interrupt 1h = Interrupt

7.1.38 INT_LATCH_4 Register (Address = 64h) [Reset = 00h]

Return to the Summary Table. This register provides the status of latched interrupts. Table 7-39. INT_LATCH_4 Register Field Descriptions Bit Field Type Reset Description

7 INT_LTCH4[7] R 0h Interrupt due to VBAT under voltage detection

0h = No interrupt 1h = Interrupt

3 RESERVED R 0h Reserved

2 INT_LTCH4[2] R 0h Interrupt due to clock halt flag

0h = No interrupt 1h = Interrupt

7.1.39 NG_IDLE_STATUS Register (Address = 65h) [Reset = 00h]

Return to the Summary Table. This register provides the status of noise gate. Table 7-40. NG_IDLE_STATUS Register Field Descriptions Bit Field Type Reset Description

7 NG_STATUS R 0h Noise mode status bit

0h = Device not in Noise gate mode 1h = Device in Noise gate mode

6 MUSIC_EFF_STATUS R 0h Music efficiency mode status bit

0h = Device not in music efficiency mode 1h = Device in music efficiency mode 5-0 RESERVED R 0h Reserved TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

52 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

7.1.40 REV_ID Register (Address = 78h) [Reset = 00h]

Return to the Summary Table. Returns Revision ID (REV_ID). Table 7-41. REV_ID Register Field Descriptions Bit Field Type Reset Description 7-4 REV_ID[3:0] R 0h Returns the revision ID. 3-0 RESERVED R 0h Reserved

7.1.41 BOOK Register (Address = 7Fh) [Reset = 00h]

Return to the Summary Table. Device's memory map is divided into pages and books. This register sets the book. Table 7-42. BOOK Register Field Descriptions Bit Field Type Reset Description 7-0 BOOK[7:0] R/W 0h Sets the device book. 0h = Book 0 1h = Book 1 FFh = Book 255 www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: TAS2320

7.2 PAGE 1 Registers

Table 7-43 lists the memory-mapped registers for the PAGE 1 registers. All register offset addresses not listed in Table 7-43 should be considered as reserved locations and the register contents should not be modified. Table 7-43. PAGE 1 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.2.1 Eh DEV_PERF_TUNING_07 Device performance tuning register Section 7.2.2 18h PVDD_OVLO1 PVDD Over voltage Section 7.2.3 2Bh DEV_PERF_TUNING_04 Device performance Tuning register Section 7.2.4 64h I2C_CKSUM I2C Checksum Section 7.2.5

7.2.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table. The device's memory map is divided into pages and books. This register sets the page. Table 7-44. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.2.2 DEV_PERF_TUNING_07 Register (Address = Eh) [Reset = 0Bh]

Return to the Summary Table. Device performance tuning register Table 7-45. DEV_PERF_TUNING_07 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h Reserved 5-4 RESERVED R 0h Reserved 3-0 DEV_PERF_TUNING_07[ 3:0] R/W Bh Device performance tuning register 0h = External PVDD mode tuning Bh = Reserved

7.2.3 PVDD_OVLO1 Register (Address = 18h) [Reset = EBh]

Return to the Summary Table. Configures PVDD OVLO voltage in external PVDD mode Table 7-46. PVDD_OVLO1 Register Field Descriptions Bit Field Type Reset Description 7-6 pvdd_ovlo_th_sel_ext_boo st[1:0] R/W 3h Pvdd ovlo threshold selection during external PVDD mode 0h = 13.5V 1h = 14V 2h = 15V 3h = 16V 5-4 RESERVED R/W 2h Reserved 3-2 RESERVED R/W 2h Reserved TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

54 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-46. PVDD_OVLO1 Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 RESERVED R/W 3h Reserved

7.2.4 DEV_PERF_TUNING_04 Register (Address = 2Bh) [Reset = 80h]

Return to the Summary Table. Device performance Tuning register Table 7-47. DEV_PERF_TUNING_04 Register Field Descriptions Bit Field Type Reset Description 7-0 DEV_PERF_TUNING_04[ 7:0] R/W 80h Device performance tuning. PPC3 software generates the correct configuration required

7.2.5 I2C_CKSUM Register (Address = 64h) [Reset = 00h]

Return to the Summary Table. Returns I2C checksum. Table 7-48. I2C_CKSUM Register Field Descriptions Bit Field Type Reset Description 7-0 I2C_CKSUM[7:0] R/W 0h Returns I2C checksum. Writing to this register will reset the checksum to the written value. This register is updated on writes to other registers on all books and pages. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: TAS2320

7.3 PAGE 2 Registers

Table 7-49 lists the memory-mapped registers for the PAGE 2 registers. All register offset addresses not listed in Table 7-49 should be considered as reserved locations and the register contents should not be modified. Table 7-49. PAGE 2 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.3.1 Ch DVC_LEVEL Digital Volume Control Level Section 7.3.2 10h DVC_SLEW_RATE Digital Volume Control Slew Rate Section 7.3.3 18h AUDIO_HPF_N0 Set Audio DC Blocker filter coefficients Section 7.3.4 1Ch AUDIO_HPF_N1 Set Audio DC Blocker filter coefficients Section 7.3.5 20h AUDIO_HPF_D1 Set Audio DC Blocker filter coefficients Section 7.3.6 54h TONE_GEN_CNTRL_01 Tone generator Frequency Control register Section 7.3.7 58h TONE_GEN_CNTRL_02 Tone generator Frequency Control register Section 7.3.8 5Ch TONE_GEN_CNTRL_03 Tone generator Frequency Control register Section 7.3.9 60h TONE_GEN_CNTRL_04 Tone generator Frequency Control register Section 7.3.10 64h TONE_GEN_CNTRL_05 Tone generator Frequency Control register Section 7.3.11 68h TONE_GEN_CNTRL_06 Tone generator amplitude control register Section 7.3.12 6Ch CLASSH_TUNING_01 ClassH Tuning Coefficient Section 7.3.13 70h CLASSH_TUNING_02 ClassH Tuning Coefficient Section 7.3.14 74h CLASSH_TUNING_03 ClassH Tuning Coefficient Section 7.3.15 78h CLASSH_TUNING_04 ClassH Tuning Coefficient Section 7.3.16 7Ch CLASSH_TUNING_05 ClassH Tuning Coefficient Section 7.3.17

7.3.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-50. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.3.2 DVC_LEVEL Register (Address = Ch) [Reset = 400000h]

Return to the Summary Table. Digital Volume Control Level Table 7-51. DVC_LEVEL Register Field Descriptions Bit Field Type Reset Description 23-0 DVC_LEVEL[23:0] R/W 400000h Addresses 0xC to 0xE are combined. Can be configured using the PPC3 Software.

7.3.3 DVC_SLEW_RATE Register (Address = 10h) [Reset = 034A51h]

Return to the Summary Table. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

56 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Digital Volume Control Slew Rate Table 7-52. DVC_SLEW_RATE Register Field Descriptions Bit Field Type Reset Description 23-0 DVC_SLEW_RATE[23:0] R/W 34A51h Addresses 0x10 to 0x12 are combined. Can be configured using the PPC3 Software.

7.3.4 AUDIO_HPF_N0 Register (Address = 18h) [Reset = 7FFBB6h]

Return to the Summary Table. Set Audio DC Blocker filter coefficients Table 7-53. AUDIO_HPF_N0 Register Field Descriptions Bit Field Type Reset Description 23-0 AUDIO_HPF_N0[23:0] R/W 7FFBB6h Addresses 0x18 to 0x1A are combined. Can be configured using the PPC3 Software.

7.3.5 AUDIO_HPF_N1 Register (Address = 1Ch) [Reset = 80044Ah]

Return to the Summary Table. Set Audio DC Blocker filter coefficients Table 7-54. AUDIO_HPF_N1 Register Field Descriptions Bit Field Type Reset Description 23-0 AUDIO_HPF_N1[23:0] R/W 80044Ah Addresses 0x1C to 0x1E are combined. Can be configured using the PPC3 Software.

7.3.6 AUDIO_HPF_D1 Register (Address = 20h) [Reset = 7FF76Ch]

Return to the Summary Table. Set Audio DC Blocker filter coefficients Table 7-55. AUDIO_HPF_D1 Register Field Descriptions Bit Field Type Reset Description 23-0 AUDIO_HPF_D1[23:0] R/W 7FF76Ch Addresses 0x20 to 0x22 are combined. Can be configured using the PPC3 Software.

7.3.7 TONE_GEN_CNTRL_01 Register (Address = 54h) [Reset = 7FFFEDh]

Return to the Summary Table. Tone generator Frequency Control register Table 7-56. TONE_GEN_CNTRL_01 Register Field Descriptions Bit Field Type Reset Description 23-0 TONE_GEN_CNTRL_01[2 3:0] R/W 7FFFEDh Addresses 0x54 to 0x56 are combined. Can be configured using the PPC3 Software.

7.3.8 TONE_GEN_CNTRL_02 Register (Address = 58h) [Reset = 4D0582h]

Return to the Summary Table. Tone generator Frequency Control register www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: TAS2320

Table 7-57. TONE_GEN_CNTRL_02 Register Field Descriptions Bit Field Type Reset Description 23-0 TONE_GEN_CNTRL_02[2 3:0] R/W 4D0582h Addresses 0x58 to 0x5A are combined. Can be configured using the PPC3 Software.

7.3.9 TONE_GEN_CNTRL_03 Register (Address = 5Ch) [Reset = 002250h]

Return to the Summary Table. Tone generator Frequency Control register Table 7-58. TONE_GEN_CNTRL_03 Register Field Descriptions Bit Field Type Reset Description 23-0 TONE_GEN_CNTRL_03[2 3:0] R/W 2250h Addresses 0x5C to 0x5E are combined. Can be configured using the PPC3 Software.

7.3.10 TONE_GEN_CNTRL_04 Register (Address = 60h) [Reset = 42FC96h]

Return to the Summary Table. Tone generator Frequency Control register Table 7-59. TONE_GEN_CNTRL_04 Register Field Descriptions Bit Field Type Reset Description 23-0 TONE_GEN_CNTRL_04[2 3:0] R/W 42FC96h Addresses 0x60 to 0x62 are combined. Can be configured using the PPC3 Software.

7.3.11 TONE_GEN_CNTRL_05 Register (Address = 64h) [Reset = 000BB8h]

Return to the Summary Table. Tone generator Frequency Control register Table 7-60. TONE_GEN_CNTRL_05 Register Field Descriptions Bit Field Type Reset Description 23-0 TONE_GEN_CNTRL_05[2 3:0] R/W BB8h Addresses 0x64 to 0x66 are combined. Can be configured using the PPC3 Software.

7.3.12 TONE_GEN_CNTRL_06 Register (Address = 68h) [Reset = 01235Ah]

Return to the Summary Table. Tone generator amplitude control register Table 7-61. TONE_GEN_CNTRL_06 Register Field Descriptions Bit Field Type Reset Description 23-0 TONE_GEN_CNTRL_06[2 3:0] R/W 1235Ah Addresses 0x68 to 0x6A are combined. Can be configured using the PPC3 Software.

7.3.13 CLASSH_TUNING_01 Register (Address = 6Ch) [Reset = 000280h]

Return to the Summary Table. ClassH Tuning Coefficient TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

58 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-62. CLASSH_TUNING_01 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_01[23: R/W 280h Addresses 0x6C to 0x6E are combined. Can be configured using the PPC3 Software.

7.3.14 CLASSH_TUNING_02 Register (Address = 70h) [Reset = 800000h]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-63. CLASSH_TUNING_02 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_02[23: R/W 800000h Addresses 0x70 to 0x72 are combined. Can be configured using the PPC3 Software.

7.3.15 CLASSH_TUNING_03 Register (Address = 74h) [Reset = 507480h]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-64. CLASSH_TUNING_03 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_03[23: R/W 507480h Addresses 0x74 to 0x76 are combined. Can be configured using the PPC3 Software.

7.3.16 CLASSH_TUNING_04 Register (Address = 78h) [Reset = 400000h]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-65. CLASSH_TUNING_04 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_04[23: R/W 400000h Addresses 0x78 to 0x7A are combined. Can be configured using the PPC3 Software.

7.3.17 CLASSH_TUNING_05 Register (Address = 7Ch) [Reset = 006666h]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-66. CLASSH_TUNING_05 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_05[23: R/W 6666h Addresses 0x7C to 0x7E are combined. Can be configured using the PPC3 Software. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: TAS2320

7.4 PAGE 4 Registers

Table 7-67 lists the memory-mapped registers for the PAGE 4 registers. All register offset addresses not listed in Table 7-67 should be considered as reserved locations and the register contents should not be modified. Table 7-67. PAGE 4 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.4.1 8h VDD_MODE_THR_LVL VDD Y Bridge Set Threshold Section 7.4.2 Ch VDD_MODE_HYST VDD Y Bridge Set Threshold hysterisis Section 7.4.3 18h MUSIC_EFF_MODE_THR Set Music Efficiency Mode Threshold Section 7.4.4 1Ch MUSIC_EFF_MODE_TIMER Set Music Efficiency Mode Hysteresis Section 7.4.5 38h LIM_MAX_ATT Limiter Set Maximum Attenuation Section 7.4.6 3Ch LIM_TH_MAX Limiter Set maximum audio limiting threshold Section 7.4.7 40h LIM_TH_MIN Limiter Set minimum audio limiting threshold Section 7.4.8 44h LIM_INF_PT Limiter Set Inflection Point Section 7.4.9 48h LIM_SLOPE Limiter Set Slope Section 7.4.10 4Ch LIM_ATK_RATE Limiter Set Attack Rate Section 7.4.11 50h LIM_RLS_RATE Limiter Set Release Rate Section 7.4.12 54h LIM_HLD_COUNT Limiter Set Hold Count Section 7.4.13 58h BOP_ATK_RATE Brown Out Protection Set Attack Rate Section 7.4.14 5Ch BOP_HLD_COUNT Brown Out Protection Set Hold Count Section 7.4.15 60h BOP_THR_LVL Brown Out Protection Set Threshold Level Section 7.4.16 64h BOSD_THR_LVL Brown Out Protection ShutDown Set Threshold Level Section 7.4.17 74h DEV_PERF_TUNING_01 Device performance tuning register Section 7.4.18 78h DEV_PERF_TUNING_02 Device performance tuning register Section 7.4.19

7.4.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-68. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.4.2 VDD_MODE_THR_LVL Register (Address = 8h) [Reset = 50A3D7h]

Return to the Summary Table. VDD Y Bridge Set Threshold Table 7-69. VDD_MODE_THR_LVL Register Field Descriptions Bit Field Type Reset Description 23-0 VDD_MODE_THR_LVL[2 3:0] R/W 50A3D7h Addresses 0x8 to 0xA are combined. Can be configured using the PPC3 Software. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

60 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

7.4.3 VDD_MODE_HYST Register (Address = Ch) [Reset = 00DA74h]

Return to the Summary Table. VDD Y Bridge Set Threshold hysterisis Table 7-70. VDD_MODE_HYST Register Field Descriptions Bit Field Type Reset Description 23-0 VDD_MODE_HYST[23:0] R/W DA74h Addresses 0xC to 0xE are combined. Can be configured using the PPC3 Software.

7.4.4 MUSIC_EFF_MODE_THR Register (Address = 18h) [Reset = 0443F5h]

Return to the Summary Table. Set Music Efficiency Mode Threshold Table 7-71. MUSIC_EFF_MODE_THR Register Field Descriptions Bit Field Type Reset Description 23-0 MUSIC_EFF_MODE_TH R[23:0] R/W 443F5h Addresses 0x18 to 0x1A are combined. Can be configured using the PPC3 Software.

7.4.5 MUSIC_EFF_MODE_TIMER Register (Address = 1Ch) [Reset = 000034h]

Return to the Summary Table. Set Music Efficiency Mode Hysteresis Table 7-72. MUSIC_EFF_MODE_TIMER Register Field Descriptions Bit Field Type Reset Description 23-0 MUSIC_EFF_MODE_TIM ER[23:0] R/W 34h Addresses 0x1C to 0x1E are combined. Can be configured using the PPC3 Software.

7.4.6 LIM_MAX_ATT Register (Address = 38h) [Reset = 2D6A86h]

Return to the Summary Table. Limiter Set Maximum Attenuation Table 7-73. LIM_MAX_ATT Register Field Descriptions Bit Field Type Reset Description 23-0 LIM_MAX_ATT[23:0] R/W 2D6A86h Addresses 0x38 to 0x3A are combined. Can be configured using the PPC3 Software.

7.4.7 LIM_TH_MAX Register (Address = 3Ch) [Reset = 400000h]

Return to the Summary Table. Limiter Set maximum audio limiting threshold Table 7-74. LIM_TH_MAX Register Field Descriptions Bit Field Type Reset Description 23-0 LIM_TH_MAX[23:0] R/W 400000h Addresses 0x3C to 0x3E are combined. Can be configured using the PPC3 Software. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: TAS2320

7.4.8 LIM_TH_MIN Register (Address = 40h) [Reset = 0A0000h]

Return to the Summary Table. Limiter Set minimum audio limiting threshold Table 7-75. LIM_TH_MIN Register Field Descriptions Bit Field Type Reset Description 23-0 LIM_TH_MIN[23:0] R/W A0000h Addresses 0x40 to 0x42 are combined. Can be configured using the PPC3 Software.

7.4.9 LIM_INF_PT Register (Address = 44h) [Reset = 0D3333h]

Return to the Summary Table. Limiter Set Inflection Point Table 7-76. LIM_INF_PT Register Field Descriptions Bit Field Type Reset Description 23-0 LIM_INF_PT[23:0] R/W D3333h Addresses 0x44 to 0x46 are combined. Can be configured using the PPC3 Software.

7.4.10 LIM_SLOPE Register (Address = 48h) [Reset = 100000h]

Return to the Summary Table. Limiter Set Slope Table 7-77. LIM_SLOPE Register Field Descriptions Bit Field Type Reset Description 23-0 LIM_SLOPE[23:0] R/W 100000h Addresses 0x48 to 0x4A are combined. Can be configured using the PPC3 Software.

7.4.11 LIM_ATK_RATE Register (Address = 4Ch) [Reset = 7C5E4Eh]

Return to the Summary Table. Limiter Set Attack Rate Table 7-78. LIM_ATK_RATE Register Field Descriptions Bit Field Type Reset Description 23-0 LIM_ATK_RATE[23:0] R/W 7C5E4Eh Addresses 0x4C to 0x4E are combined. Can be configured using the PPC3 Software.

7.4.12 LIM_RLS_RATE Register (Address = 50h) [Reset = 400179h]

Return to the Summary Table. Limiter Set Release Rate Table 7-79. LIM_RLS_RATE Register Field Descriptions Bit Field Type Reset Description 23-0 LIM_RLS_RATE[23:0] R/W 400179h Addresses 0x50 to 0x52 are combined. Can be configured using the PPC3 Software. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

62 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

7.4.13 LIM_HLD_COUNT Register (Address = 54h) [Reset = 005DC0h]

Return to the Summary Table. Limiter Set Hold Count Table 7-80. LIM_HLD_COUNT Register Field Descriptions Bit Field Type Reset Description 23-0 LIM_HLD_COUNT[23:0] R/W 5DC0h Addresses 0x5C to 0x5E are combined. Can be configured using the PPC3 Software.

7.4.14 BOP_ATK_RATE Register (Address = 58h) [Reset = 78D67Ch]

Return to the Summary Table. Brown Out Protection Set Attack Rate Table 7-81. BOP_ATK_RATE Register Field Descriptions Bit Field Type Reset Description 23-0 BOP_ATK_RATE[23:0] R/W 78D67Ch Addresses 0x58 to 0x5A are combined. Can be configured using the PPC3 Software.

7.4.15 BOP_HLD_COUNT Register (Address = 5Ch) [Reset = 005DC0h]

Return to the Summary Table. Brown Out Protection Set Hold Count Table 7-82. BOP_HLD_COUNT Register Field Descriptions Bit Field Type Reset Description 23-0 BOP_HLD_COUNT[23:0] R/W 5DC0h Addresses 0x5C to 0x5E are combined. Can be configured using the PPC3 Software.

7.4.16 BOP_THR_LVL Register (Address = 60h) [Reset = 0B9999h]

Return to the Summary Table. Brown Out Protection Set Threshold Level Table 7-83. BOP_THR_LVL Register Field Descriptions Bit Field Type Reset Description 23-0 BOP_THR_LVL[23:0] R/W B9999h Addresses 0x60 to 0x62 are combined. Can be configured using the PPC3 Software.

7.4.17 BOSD_THR_LVL Register (Address = 64h) [Reset = 0ACCCCh]

Return to the Summary Table. Brown Out Protection ShutDown Set Threshold Level Table 7-84. BOSD_THR_LVL Register Field Descriptions Bit Field Type Reset Description 23-0 BOSD_THR_LVL[23:0] R/W ACCCCh Addresses 0x64 to 0x66 are combined. Can be configured using the PPC3 Software. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: TAS2320

7.4.18 DEV_PERF_TUNING_01 Register (Address = 74h) [Reset = 079BCCh]

Return to the Summary Table. Device performance tuning register Table 7-85. DEV_PERF_TUNING_01 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_01[ 23:0] R/W 79BCCh Addresses 0x74 to 0x76 are combined. Can be configured using the PPC3 Software.

7.4.19 DEV_PERF_TUNING_02 Register (Address = 78h) [Reset = 000034h]

Return to the Summary Table. Device performance tuning register Table 7-86. DEV_PERF_TUNING_02 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_02[ 23:0] R/W 34h Addresses 0x78 to 0x7A are combined. Can be configured using the PPC3 Software. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

64 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

7.5 PAGE 5 Registers

Table 7-87 lists the memory-mapped registers for the PAGE 5 registers. All register offset addresses not listed in Table 7-87 should be considered as reserved locations and the register contents should not be modified. Table 7-87. PAGE 5 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.5.1 64h THERMAL_WARN_MIN_TEMP Thermal Flag Section 7.5.2 68h THERMAL_WARN_TEMP_STEP Thermal Flag Section 7.5.3

7.5.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-88. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.5.2 THERMAL_WARN_MIN_TEMP Register (Address = 64h) [Reset = 348000h]

Return to the Summary Table. Set the minimum threshold for Thermal Flag Table 7-89. THERMAL_WARN_MIN_TEMP Register Field Descriptions Bit Field Type Reset Description 23-0 THERMAL_WARN_MIN_T EMP[23:0] R/W 348000h Addresses 0x64 to 0x66 are combined. Can be configured using the PPC3 Software.

7.5.3 THERMAL_WARN_TEMP_STEP Register (Address = 68h) [Reset = 050000h]

Return to the Summary Table. Set the delta threshold for Thermal Flag Table 7-90. THERMAL_WARN_TEMP_STEP Register Field Descriptions Bit Field Type Reset Description 23-0 THERMAL_WARN_TEMP _STEP[23:0] R/W 50000h Addresses 0x68 to 0x6A are combined. Can be configured using the PPC3 Software. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: TAS2320

7.6 PAGE 6 Registers

Table 7-91 lists the memory-mapped registers for the PAGE 6 registers. All register offset addresses not listed in Table 7-91 should be considered as reserved locations and the register contents should not be modified. Table 7-91. PAGE 6 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.6.1 1Ch CLASSH_TUNING_07 ClassH Tuning Coefficient Section 7.6.2 20h CLASSH_TUNING_08 ClassH Tuning Coefficient Section 7.6.3 24h CLASSH_TUNING_09 ClassH Tuning Coefficient Section 7.6.4 30h DEV_PERF_TUNING_14 Device performance tuning Section 7.6.5 34h DEV_PERF_TUNING_24 Device performance tuning Section 7.6.6 38h DEV_PERF_TUNING_18 Device performance tuning Section 7.6.7 48h DEV_PERF_TUNING_25 Device performance tuning Section 7.6.8 60h CLASSH_TUNING_10 ClassH Tuning Coefficient Section 7.6.9 70h CLASSH_TUNING_11 ClassH Tuning Coefficient Section 7.6.10 74h CLASSH_TUNING_12 ClassH Tuning Coefficient Section 7.6.11 78h CLASSH_TUNING_13 ClassH Tuning Coefficient Section 7.6.12 7Ch CLASSH_TUNING_14 ClassH Tuning Coefficient Section 7.6.13

7.6.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-92. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.6.2 CLASSH_TUNING_07 Register (Address = 1Ch) [Reset = 0A72ABh]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-93. CLASSH_TUNING_07 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_07[23: R/W A72ABh Addresses 0x1C to 0x1E are combined. Can be configured using the PPC3 Software.

7.6.3 CLASSH_TUNING_08 Register (Address = 20h) [Reset = 103F46h]

Return to the Summary Table. ClassH Tuning Coefficient TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

66 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-94. CLASSH_TUNING_08 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_08[23: R/W 103F46h Addresses 0x20 to 0x22 are combined. Can be configured using the PPC3 Software.

7.6.4 CLASSH_TUNING_09 Register (Address = 24h) [Reset = 0A45F1h]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-95. CLASSH_TUNING_09 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_09[23: R/W A45F1h Addresses 0x24 to 0x26 are combined. Can be configured using the PPC3 Software.

7.6.5 DEV_PERF_TUNING_14 Register (Address = 30h) [Reset = 400000h]

Return to the Summary Table. Device performance tuning Table 7-96. DEV_PERF_TUNING_14 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_14[ 23:0] R/W 400000h Addresses 0x30 to 0x32 are combined. Can be configured using the PPC3 Software.

7.6.6 DEV_PERF_TUNING_24 Register (Address = 34h) [Reset = 400000h]

Return to the Summary Table. Device performance tuning Table 7-97. DEV_PERF_TUNING_24 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_24[ 23:0] R/W 400000h Addresses 0x34 to 0x36 are combined. Can be configured using the PPC3 Software.

7.6.7 DEV_PERF_TUNING_18 Register (Address = 38h) [Reset = 400000h]

Return to the Summary Table. Device performance tuning Table 7-98. DEV_PERF_TUNING_18 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_18[ 23:0] R/W 400000h Addresses 0x38 to 0x3A are combined. Can be configured using the PPC3 Software.

7.6.8 DEV_PERF_TUNING_25 Register (Address = 48h) [Reset = 166666h]

Return to the Summary Table. Device performance tuning www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: TAS2320

Table 7-99. DEV_PERF_TUNING_25 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_25[ 23:0] R/W 166666h Addresses 0x48 to 0x4A are combined. Can be configured using the PPC3 Software.

7.6.9 CLASSH_TUNING_10 Register (Address = 60h) [Reset = 074969h]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-100. CLASSH_TUNING_10 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_10[23: R/W 74969h Addresses 0x60 to 0x62 are combined. Can be configured using the PPC3 Software.

7.6.10 CLASSH_TUNING_11 Register (Address = 70h) [Reset = 133333h]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-101. CLASSH_TUNING_11 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_11[23: R/W 133333h Addresses 0x70 to 0x72 are combined. Can be configured using the PPC3 Software.

7.6.11 CLASSH_TUNING_12 Register (Address = 74h) [Reset = 04999Ah]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-102. CLASSH_TUNING_12 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_12[23: R/W 4999Ah Addresses 0x74 to 0x76 are combined. Can be configured using the PPC3 Software.

7.6.12 CLASSH_TUNING_13 Register (Address = 78h) [Reset = 046666h]

Return to the Summary Table. ClassH Tuning Coefficient Table 7-103. CLASSH_TUNING_13 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_13[23: R/W 46666h Addresses 0x78 to 0x7A are combined. Can be configured using the PPC3 Software.

7.6.13 CLASSH_TUNING_14 Register (Address = 7Ch) [Reset = 280000h]

Return to the Summary Table. ClassH Tuning Coefficient TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

68 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-104. CLASSH_TUNING_14 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_14[23: R/W 280000h Addresses 0x7C to 0x7E are combined. Can be configured using the PPC3 Software. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: TAS2320

7.7 PAGE 7 Registers

Table 7-105 lists the memory-mapped registers for the PAGE 7 registers. All register offset addresses not listed in Table 7-105 should be considered as reserved locations and the register contents should not be modified. Table 7-105. PAGE 7 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.7.1 30h DEV_PERF_TUNING_17 Device performance Tuning Section 7.7.2 44h CLASSH_TUNING_15 ClassH Tuning register Section 7.7.3 78h DEV_PERF_TUNING_21 Device performance Tuning Section 7.7.4 7Ch DEV_PERF_TUNING_05 Device performance Tuning Section 7.7.5

7.7.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-106. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.7.2 DEV_PERF_TUNING_17 Register (Address = 30h) [Reset = 0E9DDFh]

Return to the Summary Table. Device performance Tuning Table 7-107. DEV_PERF_TUNING_17 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_17[ 23:0] R/W E9DDFh Addresses 0x30 to 0x32 are combined. Can be configured using the PPC3 Software.

7.7.3 CLASSH_TUNING_15 Register (Address = 44h) [Reset = 580000h]

Return to the Summary Table. ClassH Tuning register Table 7-108. CLASSH_TUNING_15 Register Field Descriptions Bit Field Type Reset Description 23-0 CLASSH_TUNING_15[23: R/W 580000h Addresses 0x44 to 0x46 are combined. Can be configured using the PPC3 Software.

7.7.4 DEV_PERF_TUNING_21 Register (Address = 78h) [Reset = 000070h]

Return to the Summary Table. Device performance Tuning TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

70 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-109. DEV_PERF_TUNING_21 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_21[ 23:0] R/W 70h Addresses 0x78 to 0x7A are combined. Can be configured using the PPC3 Software.

7.7.5 DEV_PERF_TUNING_05 Register (Address = 7Ch) [Reset = 000000h]

Return to the Summary Table. Device performance Tuning Table 7-110. DEV_PERF_TUNING_05 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_05[ 23:0] R/W 0h Addresses 0x7C to 0x7E are combined. Can be configured using the PPC3 Software. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: TAS2320

7.8 PAGE 8 Registers

Table 7-111 lists the memory-mapped registers for the PAGE 8 registers. All register offset addresses not listed in Table 7-111 should be considered as reserved locations and the register contents should not be modified. Table 7-111. PAGE 8 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.8.1 8h DEV_PERF_TUNING_08 Device performance tuning Section 7.8.2 Ch DEV_PERF_TUNING_09 Device performance tuning Section 7.8.3 10h DEV_PERF_TUNING_10 Device performance tuning Section 7.8.4 14h DEV_PERF_TUNING_06 Device performance tuning Section 7.8.5

7.8.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-112. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.8.2 DEV_PERF_TUNING_08 Register (Address = 8h) [Reset = 002D0Eh]

Return to the Summary Table. Device performance tuning Table 7-113. DEV_PERF_TUNING_08 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_08[ 23:0] R/W 2D0Eh Addresses 0x8 to 0xA are combined. Can be configured using the PPC3 Software.

7.8.3 DEV_PERF_TUNING_09 Register (Address = Ch) [Reset = F8CCCDh]

Return to the Summary Table. Device performance tuning Table 7-114. DEV_PERF_TUNING_09 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_09[ 23:0] R/W F8CCCDh Addresses 0xC to 0xE are combined. Can be configured using the PPC3 Software.

7.8.4 DEV_PERF_TUNING_10 Register (Address = 10h) [Reset = 009AC0h]

Return to the Summary Table. Device performance tuning TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

72 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 7-115. DEV_PERF_TUNING_10 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_10[ 23:0] R/W 9AC0h Addresses 0x10 to 0x12 are combined. Can be configured using the PPC3 Software.

7.8.5 DEV_PERF_TUNING_06 Register (Address = 14h) [Reset = 000007h]

Return to the Summary Table. Device performance tuning Table 7-116. DEV_PERF_TUNING_06 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_06[ 23:0] R/W 7h Addresses 0x14 to 0x16 are combined. Can be configured using the PPC3 Software. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: TAS2320

7.9 BOOK100 PAGE9 Registers

Table 7-117 lists the memory-mapped registers for the BOOK100 PAGE9 registers. All register offset addresses not listed in Table 7-117 should be considered as reserved locations and the register contents should not be modified. Table 7-117. BOOK100 PAGE9 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.9.1 58h DEV_PERF_TUNING_19 Device performance tuning Section 7.9.2

7.9.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-118. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.9.2 DEV_PERF_TUNING_19 Register (Address = 58h) [Reset = 000000h]

Return to the Summary Table. Device performance tuning Table 7-119. DEV_PERF_TUNING_19 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_19[ 23:0] R/W 0h Addresses 0x58 to 0x5A are combined. Can be configured using the PPC3 Software. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

74 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

TAS2320 is a mono channel digital-in Class-D amplifier with battery voltage and temperature monitoring capabilities. I2S audio data is supplied by host processor via SDIN data port along with the bit clock and frame sync signals. I2C bus is used for configuration and control. The device needs external power supply voltage rails of VBAT: 2.5V to 5.5V, VDD : 1.65V to 1.95V and IOVDD: 1.8V or 3.3V for operation. PurePathTM Console 3 (PPC3) software is the recommended tool to configure the device, and it enables optimization of device performance parameters depending on different application scenarios.

8.2 Typical Application

Diagrams below show typical application connections for TAS2320 device. SEL1_I2C pin is used for HW Mode selection or I2C Mode selection of the Device. System can use same 1.8V supply source to power the IOVDD and VDD if required. The decoupling caps C2 and C3 should be placed close to the device pins. VBAT, VDD, PVDD power rails are critical for device performance and wide trace should be used from the source PMIC to these pins to minimize parasitic inductance. Supply ripple should be kept at minimum for these rails and should be connected to common supply planes. Errata: Additional 2mA to 3mA current consumption expected if IRQZ singal is pulled high. Read more details in What to Do and What Not to Do section. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: TAS2320

OUT_P OUT_N VBAT GND IOVDD PGND VDD PVDD VDD 1.65 V - 1.95 V GREG IOVDD 1.8 V / 3.3 V 2.2 µF 0.1 µF C11C10 Optional Components if EMI filtering is required 1 µF VDD_5V 2.5 V - 5.5 V 1 µF 0.1 µF 10 µF I2S4 External PVDD NC VBATDREG SDZ IRQZ 1 µF SEL3_SDA SEL2_SCL SEL1_I2CPVDD or GND IOVDD or GND IOVDD or GND IOVDD or GND SEL4_ADR SEL5_CLH IOVDD or GND Figure 8-1. Application Diagram for TAS2320 based system TAS2120 (Primary) OUT_P OUT_N VBAT BGNDGND IOVDD PGND VDD PVDD SW VDD 1.65 V - 1.95 V GREG DREG SDZ IRQZ IOVDD 1.8 V / 3.3 V 2.2 µF 0.1 µF C11C10 Optional Components if EMI filtering is required 1 µF 1 µF 1S Battery 2.5 V - 5.5 V 1 µF 1 µH 10 µF 0.1 µF 10 µF 10 µF I2S C12 10 µF VBAT_SNS SEL3_SDA SEL2_SCL SEL1_I2C SEL4_ADR TAS2320 (Secondary) OUT_P OUT_N VBAT GND IOVDD PGND VDD PVDD VDD 1.65 V - 1.95 V GREG IOVDD 1.8 V / 3.3 V 2.2 µF 0.1 µF C11 C10 Optional Components if EMI filtering is required 1 µF VDD_5V 2.5 V - 5.5 V 1 µF 0.1 µF I2S NC VBAT DREG SDZ IRQZ 1 µF SEL3_SDA SEL2_SCL SEL1_I2C SEL4_ADR SEL5_CLHSEL5_CLH IOVDD or GND IOVDD or GND Figure 8-2. Application Diagram for Boost Share Topology TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

76 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

Table 8-1. Recommended External Components Component Description Specification Min Typ Max Unit L2, L3 Optional EMI Filter Inductors (must use C10, C11 if L2, L3 are used) DC Current 2 A C1, C2 DREG, IOVDD decap Capacitance, 20% tolerance 1 µF Voltage rating 2 6.3 V C3 VDD decap Capacitance, 20% tolerance 2.2 µF Voltage rating 2 6.3 V C4 VBAT decap Capacitance, 20% tolerance 1 µF Voltage rating 6.3 10 V C6 PVDD Low ESL decap Capacitance, 20% tolerance 0.1 µF Voltage rating 16 25 V C7 PVDD Power decap Capacitance, 20% tolerance 10 µF Voltage rating 16 25 V C9 GREG decap Capacitance, 20% tolerance 0.1 µF Voltage rating 6.3 10 V C10, C11 Optional EMI Filter capacitors (must use L2, L3 if C10, C11 are used) Voltage rating 2xPVDD V

8.2.1 Design Requirements

Table 8-1 lists the BOM components required for the application. Table 8-2 lists other requirements for the application. Table 8-2. Design Parameters PARAMETER CONDITION SPECIFICATION VDD supply current(1) VDD Y-bridge disabled, 48ksps mode, all blocks enabled < 15mA VDD Y-bridge disabled, 96ksps mode, all blocks enabled < 20mA IOVDD supply current 1.8V mode < 1mA 3.3V mode < 1mA LC filter cut-off frequency(2) Optional EMI filter Fc > 2.4 MHz LC filter inductor Optional EMI filter L_IND > 4*VBST/(pi*Fc) (1) When VDD Y-bridge is enabled, additional power taken from VDD supply based on the selected switchover threshold voltage and the output load impedance. (2) In I2C mode, VDD Y-bridge feature can be disabled to use lower LC filter cut-off frequency. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: TAS2320

8.2.2 Detailed Design Procedure

8.2.2.1 Mono/Stereo Configuration

In this application, the device is assumed to be operating in mono mode. See Section 6.5.2 for information on changing the I 2C address of the TAS2320 to support stereo or multi-channel operation. Mono or stereo configuration does not impact the device performance.

8.2.2.2 EMI Passive Devices

The TAS2320 supports edge-rate control to minimize EMI, but the system designer may want to include passive devices on the Class-D output for further reduction in EMI . These passive devices that are labeled L2, L3, C10 and C11 in Section 8.2. If C10 and C11 are used, L2 and L3 must also be installed, and C10 and C11 must be placed after L2 and L3 respectively to maintain the stability of the output stage. The component value selection for the EMI filters depends on the application need on the frequency band that needs to be suppressed using these filters. Higher cutoff frequency helps in reducing the BOM size and reduces the switching power loss associated with the filters. Application should select the highest cutoff frequency filter which will meet the system's frequency suppression target to get better efficiency performance. The DC resistance of the inductors or ferrite beads used in the EMI filters also plays a critical role in system efficiency. Lower resistance reduces power loss and helps in improving overall system efficiency. Based on available board space, smallest DC resistance components which meet the application needs will give better efficiency performance.

8.2.2.3 Miscellaneous Passive Devices

The GREG Capacitor requires 100 nF to meet Class-D power delivery and efficiency specs. For device functionality, the GREG capacitor should be kelvin/star connected to PVDD pin of the device. In order to maintain the device performance and keep the supply ripple within the device specification, minimizing the parasitic inductance on supply/ground paths for decoupling capacitors is required. All supply decapacitors should be selected as smallest package footprint to minimize the ESL of the capacitors. The layout placement and routing of the capacitors is critical for minimizing the trace parasitic inductance. Refer to Layout section (Section 8.5.1) to get detailed recommendations.

8.2.3 Application Performance Plots

TA = 25 ℃, VBAT = 3.6V, PVDD = 12V, VDD = 1.8V, IOVDD = 1.8V, R L = 8Ω + 33μH, F in = 1kHz, Fs = 48kHz, Gain = 21dBV, SDZ=1, Noise gate mode disabled, Measured on EVM with typical application use case ( Section 8.2). Measured filter free with an Audio Precision with a 22Hz to 20kHz un-weighted bandwidth, unless otherwise noted. O u t p u t P o w e r ( W ) THD+N (%) 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 1 0 2 02 0 P V D D = 4 . 5 V P V D D = 8 . 4 V P V D D = 1 2 V P V D D = 1 4 V P V D D = 1 5 V Figure 8-3. THDN vs Output Power O u t p u t P o w e r ( W ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 P V D D = 4 . 5 V P V D D = 8 . 4 V P V D D = 1 2 V P V D D = 1 4 V P V D D = 1 5 V Figure 8-4. Efficiency vs Output Power TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

78 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

8.3 What to Do and What Not to Do

• Additional 2mA to 3mA leakage current from VDD supply is expected when IRQZ pin is pulled high.
• IRQZ pin should be left floating or grounded on the board instead of connecting pull-up resistor to avoid leakage current issue.
• I2C polling based interrupt mechanism can be implemented in host instead of HW pin based interrupt from device.
• For HW pin based interrupt, recommend to change IRQZ polarity to active high instead of the default active low state. This can be done by writing ‘1’ to IRQZ_POL register in IO_CFG_02 register in Page0 (Section 7.1).

8.4 Power Supply Recommendations

TAS2320 power up sequence of supply rails and ASI clocks can be applied in any order as long as SDZ pin is held low. Once all supplies and ASI clocks are stable the SDZ pin can be pulled high to initialize the device. For power down sequence recommedation is to mute the device first. Following that SDZ pin must be pulled low before supply rails are ramped down in any order. Once all the supplies are valid and SDZ pin is released to high, the digital core voltage regulator powers up, and starts the internal initialization sequence. After a hardware or software reset, additional I2C commands to the device should be delayed by at-least 300us to allow the device internal blocks to be initialized. VBAT supply voltage needs to be 2.2V or higher at all times including ripple conditions to avoid device VBAT UVLO.

8.5 Layout

8.5.1 Layout Guidelines

• Use wide traces for signals that carry high current and avoid VIAs wherever possible. If VIAs can't be avoided, multiple VIAs should be added to enable low parasitic inductance and high current capability. These include traces for PVDD, VBAT, VDD, PGND, GND, OUT_P and OUT_N.
• PGND signal should be directly connected and shorted to the ground plane of board to minimize parasitic inductance. Common inductance between ground pins (eg GND and PGND common routing) before connecting to ground plane should be avoided.
• The coupling between high switching signal traces like OUT_P, OUT_N, SW, should be avoided from sensitive low voltage signals.
• Minimize capacitance between high switching lines like OUT_P, OUT_N, SW, to ground/static nodes. Larger capacitance will result in efficiency drop. Coupling between OUT_P and OUT_N will also cause degraded efficiency.
• Decoupling capacitors should be placed close to the device. Smallest possible package size is recommended for the decaps to achieve best performance from device. DREG, VDD, IOVDD, VBAT (C4 cap), PVDD low ESL (C6 cap) are recommended to be 0201 case size or lower. VIAs between decapacitors and device pins should be avoided, or multiple VIAs added to minimize parasitic inductances.
• All decoupling capacitor's ground terminal should be strongly connected to the ground plane with multiple ground VIAs. The ground routing loop between the cap ground and the device ground pins should be minimized.
• For VDD Y-bridge functionality, the routing from the host PMIC to the device VDD should be wide supply plane trace with minimal routing parasitic inductance.
• For the capacitor between GREG-PVDD (C9 cap), PVDD side of capacitor should not be connected directly to the PVDD decoupling capacitors (C6, C7 and C8), and should be connected as close as possible to the device PVDD pin. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: TAS2320

8.5.2 Layout Example

Figure 8-5. Example Layout Top Figure 8-6. Example Layout Bottom

9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 www.ti.com

80 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TAS2320

9.1 Documentation Support

9.1.1 Related Documentation

For related documents see the following

• Texas Instruments, Purepath Console 3 (PPC3) Software

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (August 2024) to Revision A (October 2025) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TAS2320 SLASFC5A – SEPTEMBER 2024 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: TAS2320

www.ti.com 4-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TAS2320RBGR Active Production VQFN-HR (RBG) | 26 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 TAS2X20 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com PACKAGE OUTLINE 3.6 3.4 4.1 3.9 1.0 0.8 0.05 0.00 2X 2 18X 0.4 4X 0.55 2X 1.64X 0.5 22X 0.25 0.15 4X 0.7 0.5 4X 0.7 0.5 8X 0.35 0.25 12X 0.5 0.3 0.753 0.553 4X 0.7 0.5 0.65 0.45 (0.2) TYP VQFN-HR - 1 mm max heightRBG0026A PLASTIC QUAD FLATPACK - NO LEAD 4230415/B 03/2024 0.08 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID (45 X 0.1) PKG PKG 9 13 2226 PINS 9, 10, 12 & 23 PINS 11, 13, 22, 25 & 26

0.1 C A B

0.05 C 0.05 C SCALE 3.500 AB C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

.000 PKG 0 .000 PKG 0 (0.853) 2X ( ) 1.55 2X ( ) 1 2X ( ) 0.6 2X ( ) 0.2 2X ( ) 0.2 2X ( ) 0.6 2X ( ) 1 2X ( ) 1.55 ( ) TYP 2.2 ( ) TYP 2.2 ( ) TYP 1.95 2X ( ) 1.3 2X ( ) 0.8 2X ( ) 0.4 2X ( ) 0.4 2X ( ) 0.8 2X ( ) 1.3 ( ) TYP 1.95 (3.3) 12X (0.6) 4X (0.8) 4X (0.8) 8X (0.3) 4X (R0.1) (R0.05) TYP VQFN-HR - 1 mm max heightRBG0026A PLASTIC QUAD FLATPACK - NO LEAD 4230415/B 03/2024 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). PKG PKG LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SEE SOLDER MASK DETAIL 9 13 2226 PINS 9, 10, 12 & 23 PINS 11, 13, 22, 25 & 26 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN .000 PKG 0 .000 PKG 0 ( ) TYP 2.2 2X ( ) 1.55 2X ( ) 1 2X ( ) 0.6 2X ( ) 0.2 2X ( ) 0.2 2X ( ) 0.6 2X ( ) 1 2X ( ) 1.55 ( ) TYP 2.2 ( ) TYP 1.95 2X ( ) 1.3 2X ( ) 0.8 2X ( ) 0.4 2X ( ) 0.4 2X ( ) 0.8 2X ( ) 1.3 ( ) TYP 1.95 4X (R0.1) 12X (0.6) 22X (0.2) (R0.05) TYP (3.3) 4X (0.8) 4X (0.8) 8X (0.3) (0.853) (0.8)(0.75) VQFN-HR - 1 mm max heightRBG0026A PLASTIC QUAD FLATPACK - NO LEAD 4230415/B 03/2024 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. PINS 9, 10, 12 & 23 PINS 11, 13, 22, 25 & 26 SOLDER PASTE EXAMPLE BASED ON 0.1 MM THICK STENCIL SCALE: 20X PKG PKG 9 13 2226

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025