TAMC641 TEWS | Alldatasheet
Document overview
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Technical content
TAMC641 High Performance Virtex-5 AMC with FMC-Slot
Application Information
The TAMC641 is a standard single Mid-Size or Full -Size AMC module providing a user configurable Virtex -5 FPGA. The integrated PC Ie Endpoint Block of the Virtex-5 can be used to build an x1, x4 or x8 PCIe link via AMC Port 4 -11. The implementation of other protocols like SRIO or XAUI is also possible. AMC Ports 0 & 1, commonly used for Gigabit Ethernet, and AMC Ports 2 & 3 are also connected to the FPGA. The integrated Gigabit Ethernet MACs of the Virtex-5 allow fast and easy protocol implementation. To allow direct board- to-board communication, AMC Ports 12-17 are connected to Virtex -5 I/Os, allowing AC - coupled LVDS communication wi th a port speed up to 1.0Gb/sec. For flexible I/O solutions the TAMC641 provides a VITA 57.1 high pin count FMC Module slot, allowing active and passive signal conditioning. All FMC I/O lines are directly connected to the FPGA, which maintains the flexibility of the Select I/O technology of the Virtex -5 FPGA. In addition, the FPGA is connected to the following external memories: - two banks of DDR2 SDRAM (up to 128 M x 32 (512 MB) each) - two banks of QDR -II SRAM (up to 4 M x 18 (8 MB) each) Multiple clock s from the AMC -interface, the FMC and from on-board sources are supplied to the FPGA. The FPGA is configured by a flash device, which is in- system programmable and able to store multiple code versions. The TAMC641 supports encrypted FPGA bitstream usage. Encrypted FPGA bitstreams cannot be copied or reverse engineered, securing your intellectual property. The IPMI Connectivity Records located inside the Module Management Controller (MMC) can be modified by the customer (e.g. via IPMI), to adapt to the differ ent possible communication protocols (PCIe, SRIO, XAUI, ...). User applications for the TAMC641 require the full ISE Foundation software, which must be purchased from Xilinx. The Engineering Documentation TAMC641 -ED includes all information needed for cust omer specific FPGA programming. The FPGA Development Kit TAMC641-FDK includes the engineering documentation, ucf-files with all necessary pin assignments and basic timing constraints, and a well documented VHDL example application. This example application is called TPLD003 (Tews Programmable Logic Design) and covers the main functionalities of the TAMC641 like DMA capable PCIe endpoint with interrupt support, register mapping, DDR2 and QDR -II memory access and basic I/O to the FMC slot. It comes as a Xilin x ISE project with source code and as a ready -to-download bitstream. It is the basis for fast and reliable customer application development, and can significantly reduce time to market. Software support for the TPLD003 is available for all major operating systems. In-circuit programming and debugging of the FPGA design (e.g. using Xilinx “ChipScope”) is supported. The Program and Debug Box TA900 allow s access to the module while it is inserted in a system. It provides access to the module's JTAG Chain, the UART of the on-board Module Management Controller (MMC) and to two user pins of the Virtex-5 FPGA. If a UART core is implemented in the FPGA, serial communication via the TA900 is possible. The TA900 can be accessed by USB 2.0 and by a 14-pin JTAG Header ( e.g. for connecting a Xilinx Platform Cable). For First -Time-Buyers the TA900 and the TAMC641 -ED or TAMC641-FDK is recommended. TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice. All trademarks mentioned are property of their respective owners. Issue 1.0.0 2013-11-14 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com
Form Factor: PICMG AMC.0 R2.0 Module Board size: single Mid-Size or Full-Size AMC AMC port 0 – 11 connected to FPGA MGTs on-board AC-coupling for Rx and Tx port speed up to 3.2Gb/sec (6.5Gb/s for FX) AMC port 12 – 15 & 17 connected to FPGA I/Os on-board AC-coupling for Rx and Tx port speed up to 1.0Gb/sec TCLKA – TCLKD support Virtex-5 FPGA with integrated PCIe Endpoint Block XC5VLX110T or XC5VLX155T XC5VSX95T XC5VFX70T or XC5VFX100T 2 x QDR-II SRAM bank, 1M x18 (2 MB) each 2 x DDR2 SDRAM bank, 64 M x32 (256 MB) each IPMI V1.5 support Front panel LEDs: Blue Hot Swap LED Red FAIL LED (LED1) Green USER / Power Good LED (LED2) Vita57.1 FMC Slot (high pin count) 160 single ended I/Os or 80 differential x4 Multi-Gigabit Link to FMC VADJ = 1.2 – 3.3 Volt Operating temperature 0°C to +70°C MTBF (MIL-HDBK217F/FN2 GB 20°C) TAMC641: 304000 h TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice. All trademarks mentioned are property of their respective owners. Issue 1.0.0 2013-11-14 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com
TAMC641-10R Virtex-5 FPGA Module, Single Mid-Size, XC5VLX110T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot TAMC641-11R Virtex-5 FPGA Module, Single Full-Size, XC5VLX110T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot TAMC641-12R Virtex-5 FPGA Module, Single Mid-Size, XC5VLX155T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot TAMC641-13R Virtex-5 FPGA Module, Single Full-Size, XC5VLX155T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot TAMC641-14R Virtex-5 FPGA Module, Single Mid-Size, XC5VSX95T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot TAMC641-15R Virtex-5 FPGA Module, Single Full-Size, XC5VSX95T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot TAMC641-16R Virtex-5 FPGA Module, Single Mid-Size, XC5VFX70T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot TAMC641-17R Virtex-5 FPGA Module, Single Full-Size, XC5VFX70T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot TAMC641-18R Virtex-5 FPGA Module, Single Mid-Size, XC5VFX100T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot TAMC641-19R Virtex-5 FPGA Module, Single Full-Size, XC5VFX100T-1, 512 MB DDR3, 4 MB QDR-II, FMC Slot Optional available on request:
- Operating temperature -40°C to +85°C
- Faster FPGA speed grades
- 1 GB DDR2 (2 banks 128 M x 32)
- 8 MB QDR-II (2 banks of 2 M x 18) or 16 MB QDR-II (2 banks of 4 M x 18) For the availability of non-RoHS compliant (leaded solder) products please contact TEWS. Documentation TAMC641-DOC User Manual TAMC641-ED Engineering Documentation includes TAMC641-DOC, Data Sheets, Constraints Files TAMC641-FDK FPGA Development Kit for TAMC641, includes TPLD003 Example Design Accessories TA900-10R Program and Debug Box, USB, JTAG, 20pin FPC connector, including USB A-USB B and FPC Flexcable Software TDRV015-SW-25 Integrity Software Support (for basic example design TPLD003 of the TAMC641-FDK) TDRV015-SW-42 VxWorks Software Support (for basic example design TPLD003 of the TAMC641-FDK, Legacy and VxBus-Enabled Software Support) TDRV015-SW-65 Windows Software Support (for basic example design TPLD003 of the TAMC641-FDK) TDRV015-SW-72 LynxOS Software Support (for basic example design TPLD003 of the TAMC641-FDK) TDRV015-SW-82 Linux Software Support (for basic example design TPLD003 of the TAMC641-FDK) TDRV015-SW-95 QNX Software Support (for basic example design TPLD003 of the TAMC641-FDK) For other operating systems please contact TEWS. TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice. All trademarks mentioned are property of their respective owners. Issue 1.0.0 2013-11-14 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com