TACT83000

Texas Instruments

AT CHIP SET

Manufacturer: Texas Instruments

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03612 AUGUST 1990

~ * High-Speed 1-um CMOS Technology * TACT83443 AT Bus Interface Unit (ATU) Supports System Speeds up to 33 MHz — Internal Clock Switching Between Two © Fully AT-Compatible 386 Three-Chip SX, Independent Frequencies Controlled by Four-Chip DX Solutions Software — Asynchronous AT Bus Interface With * Only Four Additional Logic Chips Needed Write Buffer Option * Major Features Programmable Through ~ Full AT Direct-Drive Capability Software — Extended Direct Memory Access Mode for 32-Bit Operation * TACT83442 Memory Control Unit (MCU) — Fast CPU Reset and A20GATE. — Cascadable up to Eight Devices Modification - Address Range of up to 32M Byte Per ~— Numeric Processor Interface for 387SX, Device, 256M Byte Fully Cascaded 387DX, and Weitek 3167 — Supports 256K-, 1M-, and 4M-Bit DRAMs — Integrates All Essential AT Peripherals in Normal, Page, Word-Interleave, and — Real Time Clock With 128-Byte CMOS Page Block-Interleave Modes RAM ~— Programmable DRAM Timing Parameters * TACT83441 Data Path Unit (DPU) — Supports up to Two Memory Banks for . 32-Bit Systems and Four Banks for ~ 8- and 16-Bit Data Bus Sizing 16-Bit Systems - Data Path Cascadable to 32 Bits — Can Directly Drive up to 36 DRAM — Write Buffer Capability for AT Bus Devices Access ~— Shadow RAM Available Between — Supports Posted Write Operations From OC 0000h and OF FFFFh Cache Controller - Contains Global Page Mapping RAM — Parity Generation and Checking Logic Allowing Remap of * 64K-Byte Memory Blocks Above 1M Byte * 16K-Byte Memory Blocks Below 4M Byte

description

The Texas Instruments TACT83000 AT Chip Set is designed for cached and noncached 386™-based PC-AT™ compatible systems running at speeds up to 33 MHz. Manufactured with high-speed 1-um CMOS EPIC™ technology, the chip set is functionally partitioned into three devices: the TACT83443 AT Bus Interface Unit (ATU), the TACT83442 Memory Control Unit (MCU), and the TACT83441 Data Path Unit (DPU). The ATU is packaged in a 208-lead plastic quad flatpack (QFP), while the MCU and DPU are packaged in 100-lead plastic QFPs. These three chips, along with four other logic chips, comprise all the logic necessary for a fully compatible 16-bit 386SX-based system. Since one DPU provides a 16-bit data path, a 32-bit 386DX-based system requires an additional DPU. With software-controlled configuration registers on board the ATU and MCU, the chip set supports a wide variety of PC system configurations. For complete programming details, see the TACT83000 AT Chip Set User's Guide, literature number SRZU001. ~ PC-AT is a trademark of international Business Machines. 386 and 387 are trademarks of Intel Corporation. EPIC is a trademark of Texas Instruments Incorporated el PRODUCTION DATA documents contain information current Copyright © 1990, Texas Instruments Incorporated of all parameters. INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265 1

386 CONTROLLER 4} TIMING 3

cpu ‘& ADDRESS E} contro. fe} |o 7 iad ; BUFFER =j PHERALS [4 ED EA ee SD + Optional architecture In a 386 cache-based system, the TACT83000 chip set architecture uses three tiers of buses. From the system core outward, these buses are the local or CPU bus, the extended local (EL) bus, and the AT bus. The architecture also provides an 8-bit peripheral bus, the XD bus, which operates with AT bus timing. The three-tiered bus structure used by the TACT83000 in a cache-based system can be seen in the functional block diagram. SS TEXAS tp INSTRUMENTS

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The EL bus includes both data (ED) and address (EA) lines. CPU addresses sent out on the EA lines are mapped to physical memory addresses (MA) by the MCU. The AT bus includes system address (SA) and latched address (LA) lines, as well as system data (SD). Control lines are also included in the buses, though they are not listed separately in the block diagram. All data traffic between the buses is controlled by the DPU(s), which contain(s) logic for bus sizing and conversion, as well as for parity generation and checking. The TACT83000 chip set supports the 82385 (or compatible) cache controller, providing control of external address buffers and data transceivers in the DPU between the CPU local bus and EL bus. In a cache-based system, the interface between the CPU local bus and the EL bus is controlled by the cache controller. In a noncached system, the EL bus essentially becomes the CPU bus. The ATU, situated between the EL bus and the AT system bus, provides the interface, timing, and command control for both buses, as well as direct 24-mA drive capability for the I/O channel. The ATU also contains essential AT system board peripherals. The MCU, located on the EL bus, controls system memory interface. The MCU is a programmable DRAM controller that has extensive memory mapping capability. It can function in several DRAM modes selectable through its configuration registers. extended local (EL) bus The EL bus is a buffered CPU bus with additional parity lines and control signals for EL bus accesses. These control signals, local access with parity (LAP) and local access with no parity (LANP), are required of all devices on the EL bus and gated to the ATU to indicate that the current cycle is an EL bus access. In many systems, performance can be greatly improved by placing high-speed I/O peripheral devices on the EL bus instead of on the AT bus. These devices can then operate at CPU speed, rather than at the 8-MHz limit of the AT bus. Typical examples of such peripherals are SCSI disk controllers, LAN adapters, and display . subsystems. A peripheral placed on the EL bus must generate LAP/LANP when it is accessed in order to let the system controller know that the bus cycle belongs to that device on the EL bus. Otherwise, the cycle will be either passed on to the AT bus or terminated by a ready signal from the system controller. The EL bus directly supports the data bus width of the attached processor. Bus sizing must be accomplished through the byte enable bits (BE3 — BEO) and the DPU(s). Ina minimum system without a cache controller, the EL bus is identical to the CPU bus with respect to address and control. For example, the CPU address line A10 will be directly connected to the MCU EA10 address line. Note, however, that the EL data bus (EDO-EDxx) is always the output data from the DPU; itis the CPU data bus buffered via the DPU and is, therefore, the same in either a cached or noncached system. chip set configuration All programmable functions and page map entries for the ATU and MCU are accessed through an index/data register pair, minimizing the size of CPU I/O space necessary for configuration. The index register is a pointer to the actual configuration register/map entry location, and the data register is the port used to access the location pointed to by the index register. Once the desired index value is set by writing to the index register, reading from or writing to the data register will retrieve or update the value in the configuration register/page map entry addressed by the index register. A read or write of either register involves a single 16-bit data access. By default, the data register is located at I/O address 0024h and the index register at 0026h. However, the register pair may be relocated after power-up to any unused I/O address between 0000h and FFFFh by resetting the configuration register I/O base address for the device (index = OXFF). In a 32-bit system, the data register address must be at a double-word boundary. For details regarding programming the configuration registers, see the TACT83000 AT Chip Set User's Guide. Cd TEXAS *% INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265 3

the device Terminal Function Table. Figure 1 details the convention used to describe each type of I/O buffer. t Bidirectional buffers operate at non-Schmitt-triggered TTL Input levels. Figure 1. Buffer Naming Convention

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AT BUS INTERFACE UNIT (ATU) EEE ~ TACT83443 AT Bus Interface Unit (ATU) The ATU supports three types of functions: system bus interfacing, timing between buses, and standard AT peripherals. During a DMA cycle or a master cycle for an AT bus device, the ATU asserts control over the EL bus. At all other times, it is a slave to the EL bus master. This master is normally the cache controller in a cache-based system; however, there may be other EL bus masters as well. interfacing system address and control buses The ATU provides the interface, command translation, and timing control among the CPU/EL bus, AT bus, and system support peripherals. It manages two separate command/control buses — the AT bus and the EL bus. The signals from these two buses are inputs to two internal control blocks. The AT control block monitors inbound CPU/EL signals and encodes those into corresponding AT bus signals. The EL control block monitors inbound AT bus signals and decodes those into CPU/EL signals. There is also acommon support peripheral block, address management block, data control block, and configuration register space shared by the AT and EL control blocks. timing between system buses System oscillators are fed into the ATU, which in turn divides them to generate the appropriate system clocks for both the EL and AT buses. In addition to providing the clocks as outputs, the ATU uses the clocks for timing control and synchronization. The ATU also manages the generation of system reset and drives AT bus refresh timing. The AT bus interface works either synchronously or asynchronously in both directions. All timing parameters, including control of the clock dividers, are defined by software. AT peripherals ~ The ATU contains the following standard AT system board peripherals: * Two 8237A-compatible direct memory access (DMA) controllers with SN74LS612-compatible page registers * Two 8259-compatible interrupt controllers ° — 8254-compatible timer/counter * —146818-compatible real-time clock (RTC) with on-board oscillator * Port B and nonmaskable interrupt (NMI) logic All of these peripherals are fully AT-compatible functions. The DMA and NMI functions and the static RAM offer additional features. The DMA controller supports full 32-bit DMAs for EL bus devices, including support of an EL cascade or AT master mode. The NMI extensions provide for generation of NMI due to a READY timeout and improved NMI status reporting. The configuration static RAM provided with the RTC registers is 128 bytes in length and can be backed up by a battery. Because the ELand AT buses share the standard peripheral block, these peripherals are available to both buses. For I/O addressing, the ATU peripherals and keyboard controller are placed on the XD bus, the only data bus that is routed into the ATU. Any additional devices (system ROMs) placed on the XD bus must drive XDSEL. In addition to its extensive control and timing management for the major system buses, the ATU also provides interfaces for or supports several other system devices or functions. For example, an interface is available for anumeric coprocessor. This interface is monitored by the ATU and is used to provide the coprocessor'’s status to the CPU. A keyboard processor interface, AT bus refresh control logic, programmable chip select options, and AT write buffer control are also available. SS TEXAS % INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265, 5

AT BUS INTERFACE UNIT (ATU) EE Eee ATU terminal assignments The ATU is packaged in a 208-lead QFP. The ATU Terminal Functions Table gives a description of each terminal. See Figure 1 for details of the 1/O buffer types. Top View gepeuie 2 5 Rx PEE EE RE gysgogend ai © goers erosre wie 3 iets) S BM egosley os eee FQQlSlel ove eses2 aay 9 segzee eee 89993925553 98858225555 2555555893333 2333533825 BERBAPSISSS STITT SSSH SATIS SRASLRALKAK SSE SST Ser esssss wen eee eee eee eee Eee Eee ee RRR Ee a eee eee ee ah suena Te ise toa SMERW ono 159 tozf RESET DAV oREG7 160 101 % DReos 161 100 MASTER oREOS qi62 sep ows oREos q163, sep TocHcK DREG? qr68 o7b ioesie DREa! qt65 96 WEMCSTS oREao 166, 9p GNO Vee 4167 sab trots xb? 168 sop inate x06 169 s2f inai2 xos 170 sip init xos 171 sof inci x03 Qi72 69 IRQQ xo2 173 8B Vee xo1 176 a7 iar xoo 175 asp inos no diz asp inos aTeux 177 sab trae MecKHH 178 esp inas MPCKHL 179 e2p inat MPCKLM 180 ai nu MPCKLL 181 sop NU ATLATCH qfis2 79 nu Veo 4183 TACT83443 78 NU opuss Gis 7B XOsEL opus2 qies 75 osc_1 Dpust qli26 75 GNO’ ‘sae ie? 74 azocate ‘BOE qfiss zap KeYBCS Lwik qtes 72 SPEAKER teus qfi90 71B osc_t2 POLK 191 70 Vee Gno qisz s9f PwRGOOD azocouT 4133 sab PCSt ERESET i194 e7p pese TARP cli9s esp PCs TAP i968 esp ATcsow FLUSH qf197 sab ATCRES: Veo-4 198 sap Batt £A31 9199 62 RTCXOUT £A30 4200 61 ATCXIN ea29 201 sop RTCRTN £A26 202 sop setsz ea27 203 50) CLKINt GNO 204 57 GNo Eaz6 205 56) CLKINO EA25 208 ssf CPUSTEN EA24 207 s4p NPRST €A23 208 50 NPPEREG cnn ewonoate SPE SCS PRENSA RRKRREHASSSSHSHSETITIETIIBSS ¥eS2 SSESesesseesess QOeSSIER FES Boog Zigisn|gy 9 slo oa ales $495 25552852955 95085 £5 3585 92582585 2388 MENG ge

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NU-Nonusable, make no external connection. These are reserved for future use INSTRUMENTS

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AT BUS INTERFACE UNIT (ATU) ES ~ ATU Terminal Descriptions TERMINAL BUFFER [BUSY______0 | 0 | Ps | Numeric coprocessorbasy Oe Tearstscuana Oe USE Or poner Pe source is CLKINO. verify that the CPU clock and the internal AT unit clock have the same delay. It should be sourced after any clock distribution buffering. an ee reset. The keyboard reset is generated internally to the ATU by intercepting the keyboard controller reset command. [ERROR 28, [-0 | PP6 | Coprocessoreror SSCS [HOLD a8 [0 | P10 [Hold requestinputto CPU [HOLOA a6 [1_[ TIS [Hold acknowiedge outputfrom GRU [NTR 28 | 0 | PPS interuptrequest ouputio PU [N28 [0 | PP6__|Nonmaskabie nieraptouputio GPUS | PEREG 37 [0 | PB [Numeric processorrequest—— SS [READY a8 1] TLS [Ready input. Same signal as OPU wr ERERBY. i a A cr READY signals. uses the signal BLE (Byte Low Enable). uses the signal BHE (Byte High Enable). uses the CPU address line A1. on 386SX systems. EA2-EA4 24-22 fe} 3S10PU | EL bus address bits 2~31 EAS-EA14 20-11 EA15-EA18 96 EA19-EA22 at EA23-EA26 208-205 EA27-EA31 203-199 [ERESET 104 | 0 | PY | EL busreceh Aclve only durng poweronresct__————=d [ANP 195 [1 [TIS [Local access with nopaty [ear t96 | TS [tonal access wih party [owe saa | 0 | P10 | Latones WI. Tis is the latched CPU or EL bus Wi signa | [pci 191 | 0 | pPt6 [CPU phase cock. High during processorphase®. ———+| tin aminimum system configuration without cache and address buffers, some EL signals can be connected directly to the CPU. ~ For example, in this case, EA10 is identical to A10 from the CPU. SS TEXAS % INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75285 7

AT BUS INTERFACE UNIT (ATU) Ls ATU Terminal Descriptions (continued) TERMINAL BUFFER ee ee L 386SX Operation Mode H 386DX Operation Mode [CRBUS 10 [OFFS [SPU rE bus state signal indicating Ta/TaP. Asie gh | Eee the ATU numeric processor error logic to generate IRQ13 if a processor other than the 387 is used. Pee ST PS iam 5057 orc signal is used for generating a BUSY signal for the CPU. Pe | Se an unmasked error condition has been detected. In this case, the NPBUSY signal is latched, and a numeric processor interrupt signal will be generated. | NPPEREG 5 | 1 TIPOS [Numeric processor exensionrequestinpat——— a ee for the numeric processor. Either a write to I/O address OOF 1h or a system reset will activate this signal. LaTAtcH tea | O[ 6P6__[ATbusbferaicheomon EP Renicamavemrsen | the DPU if no cache controller is present. Loeusr eee PU soueeseett Cppuse tes 0 | Pre [oPUsoweessiet? CS Lopuss te [0 | Ps [PU source selects Conversonsarad a ee ee 1 to the FPC bit of the ATU miscellaneous control register and cleared by writing 0. (panne ira | CWO Memory pariy checkin wordhanbye (ouPcKat tre 1_[-GM0s | Memory party check igh wordiowbyte | CMPCKLH Teo |_| GMOS [Memory party checklow wordhighbyte | [LWPoKLL ter_| 1 GMOS [Memory party checklowwordiowbyfe sats ter | 0 [pps | Source/destnaion convcloftne AT bus ufer | AEN 157 PP24 ‘Address enable. This signal is used to disable other address driver de- vices from the AT bus. When this line is active, the DMA controller has ai control of the address data bus and read/write lines. a a el state machine. This clock is used for generating the independent AT bus timing. The power-on default source is CLKINO/4. ee ee | signal is driven high. LS TEXAS % INSTRUMENTS

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AT BUS INTERFACE UNIT (ATU) a > ATU Terminal Descriptions (continued) TERMINAL BUFFER NAME No. vo TvPE DESCRIPTION DACKO-DACK3 = 156-153 DMA request acknowledge DACK5—DACK7, 152-150 DREQO-DREQ3 = 166-163 TTL-S DMA request. These signals are asynchronous channel requests that DREQ5-DREQ7 162-160 are prioritized. DREQO has the highest priority; DREQ7 has the lowest. DREQO-DREQ3 will perform 8-bit DMA transfers and DREQ4—DREQ7 will perform 16-bit DMA transfers. IOCHCK 98 TTL-S [1/0 channel check. This signal is used by devices on the I/O channel to indicate an uncorrectable error, such as a parity error. An NMI will be generated if NMI is enabled in Port B/NMI logic. IOCHRDY 134 VO | OD24 |1/O channel ready. The ATU does not complete the current cycle as long as OCHRDY is low. This signal is used by AT bus cards to extend the number of wait states beyond the set default values. 1OCS16 97 TIL-S 1/0 chip select 16. If 1OCS16 goes active low during an AT bus I/O cycle, the ATU disables the 16-to-8-bit conversion logic and sets the default wait states for 16-bit I/O transfer; otherwise, the ATU generates two 8-bit I/O cycles on the AT bus. {OR 135 yo 3S24PU | 1/O read. During AT master and DMA cascade modes, outputs are in 3-state. TOW 136 YO | 3S24PU | I/O write. During AT master and DMA cascade modes, outputs are in 3-state. IRQ1 82 TTL-S Interrupt request. Available for AT bus devices ~ IRQ3IRQ7 83-87 IRQS-IRQ12 89-92 IRQ14-IRQ15 93-94 LAI7-LA19 141-143 vO 3824 Latchable address. These address bits are inputs when MASTER is LA20-LA23 145-148 low and HOLDA is high, indicating an external bus master cycle; they are outputs otherwise. [WASTER 00 [|S [Masi reuestinnwt a memory cycle, the ATU disables the 16-to-8-bit conversion logic and activates the default wait state logic for a 16-bit transfer; otherwise, the ATU generates two 8-bit memory cycles on the AT bus. MEMR 137 fe} 3S24PU | Memory read bus. During AT master and DMA cascade modes, outputs are in 3-state. MEMW 138 ie} 3S24PU | Memory write bus. During AT master and DMA cascade modes, outputs are in 3-state. RESET DRV 102 PP24 Reset drive. This line is used to reset or initialize system logic on the AT bus. This signal is active during power-on and if the RPC bit in the ATU miscellaneous control register is set. SAO-SA4 109-113 fe} 3824 System address lines 0-16. Latched by BALE. During AT master and SA5-SAQ 115-119 DMA cascade modes, outputs are in 3-state. SA10-SA15 121-126 SA16 128 [Sair-Saieteo-tet_| 0 | ae |Synemaasressines 1 Te ed TEXAS % INSTRUMENTS POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9

AT BUS INTERFACE UNIT (ATU) Cl ATU Terminal Descriptions (continued) TERMINAL BUFFER NAME NO. vo TYPE DESCRIPTION SMEMR 104 3S24PU_ | System memory read. This signal is similar to the MEMR signal, but is only active in the first 1M byte address range. SMEMW 103 3S24PU_ | System memory write. This signal is similar to the MEMW signal, but is only active in the first 1M byte address range. SYSCLK 105 PP24 AT bus system clock. This clock is half of the ATCLK frequency and is inactive until the first CPU access after reset. TC 158 PP24 Terminal count. During DMA service, a high level indicates the completion of the requested number of transfers. ows 99 TTL-S __| Zero-wait state. AT bus cards can use this input to shorten the current bus cycle. After OWS goes low, the ATU will synchronously finish the cycle. A20GATE 74 TTL-S A20 gate input. Sourced by the keyboard and input to A20 gate out control logic. A20GOUT 193 ‘A20 gate output. Combination of keyboard controller, A20 gate, and gate output contro! bit of miscellaneous control register. A low level on this input will hold the A20 line low; otherwise, the A20 line is identical to the CPU A20 line. BATT 63 Real-time clock power supply input. This terminal should be connected to battery circuit. This terminal is at Vgc level during powered operations and battery voltage is applied to it during a powered-down condition. KEYBCS 73 Keyboard controller chip select. Normally, the ATU generates chip select signals for |/O addresses 60h and 64h. However, when FO, F2, F4, F6, F8, FA, or FCh is written as data to I/O address 64h, both CPURST and KEYBCS are generated. When FEh is written to /O address 64h, only CPURST is generated OSC_1 76 TTL Oscillator clock input. This is the 14.31818-MHz clock, which is not synchronous to the AT-system clock (SYSCLK); an external oscillator is required. OSC_12 ral Oscillator clock output. Provides 1.193-MHz frequency for a PC-AT-compatible design, which is used internally for the timers and by the MCU for refresh and RAS pulse width timing. PCST 68 Programmable chip select 1. Programmable through index address = 0809. PCS2 67 Programmable chip select 2. Programmable through index address = 080A. PCS3 66 Programmable chip select 3. Programmable through index address = |° | oe | RTCRES 64 CMOS-S | Real-time clock reset. This signal resets the real time clock after a RTCRTN 60 Real-time clock oscillator ground terminal. This terminal provides ground return for the 32.768-kHz crystal timing capacitor to the onboard oscillator circuit. RTCSQW 65 Real-time clock square-wave output. This signal is enabled through the RTC configuration registers. Neel TEXAS % INSTRUMENTS

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AT BUS INTERFACE UNIT (ATU) a ~ ATU Terminal Descriptions (continued) TERMINAL BUFFER NAME NO. vo TYPE DESCRIPTION RTCXIN 61 Real-time clock oscillator input. This signal connects to a 32.768-kHz RTCXOUT 62 Real-time clock oscillator output. This is the second terminal for the ee TT eetitceyeeltssaesyeacy | SPEAKER 72 Speaker output. This is an ANDed output of data bit 1 of port B (I/O address 0061h) and the OUT2 output of the timer. For driving the speaker, an open collector TTL buffer or a transistor with a base [xOSEL_______—77_~+|_1_| TLS | XObus select Orvendby XD bus devcosto nivale WObus Wanstor | [cuxino 86 tT CMOS [tock input. One ofthe two oscilatorinputs. | [cunt 88 CMOS [Clock input t-One ofthe two oscilatorinputs, | CPUSTEN 55 TIL CPU self-test enable. When active high (pulled up), the ATU will drive BUSY low during power-on reset and hold it low for 10 CLK2 states PWRGOOD 69 CMOS Power good. Power supply generates this signal, which is used as a ae ed [Woe [| Nena, make no eternal sonnesion Reserved fer iture use| ~ GND 10, 25, 37, Ground 38, 57, 75, 95, 108, 120, 132, 133, 144, 159, 176, 192, 204 Voc 5, 21, 35, Supply voltage 48, 70, 88, 101, 114, 127, 139, 149,167, 183, 198 LS TEXAS % INSTRUMENTS POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 "1

DATA PATH UNIT (DPU) SS TACT83441 Data Path Unit (DPU) The DPU provides data routing for all system data traffic. The data routing is provided by two sections of the DPU: the CPU and EL data buses (the D/ED data lines) and the AT data bus (the SD/XD data lines). For both read and write operations, data between these two sections is transferred through an AT bus buffer latch. An AT write buffer controlled by the ATU is also provided on the DPU. In addition, the DPU contains bus sizing and conversion logic for 8-bit and 16-bit AT bus accesses, and parity generation and checking logic. DPU terminal assignments The DPU is packaged in a 100-terminal QFP. The DPU Terminal Function Table gives a description of each terminal. See Figure 1 for details of the I/O buffer types. Top View SF yo22Ee2 Qa x 55 8a55528 85888 S8S8aRh8saes yeas DAFDADARDGOHDDDDDADSFDORDDDKKKRKOKS KKK BRRARKRRKRKKRSSSSSSSSSSSSESRSSSS GND Q 81 50 [} SELOPU sao [| 2 49 0 GND sai 83 48 f} MPCKL NU | 84 47 [) MPCKH NU ( 85 46 wwik NU | 86 45 [} ppuss NU Qj 87 44 1 ppus2 MDPH {J 88 43 [ ppusi GND qj 89 42 1) ATLATCH EDis J 90 41D Vcc Vec 91 TACTE3441 40 P sate pis 92 39 GND ED14 J 93 36D BTR pia G94 37 P DOE E013 Q 95 36 WBCLK 013 96 35 [] ELWBEN Epi2 Qj 97 34 [1 CLKSEL GND q 98 33 ff] cLK2 p12 q 99 32 [| READY E011 (| 100 31 ff GND ranmemonaaol EN et PeSEPSRaNQRaRRaRas ro OSPOPePeItnnwoOe YMHT TN MOANT ro YO Bg Sse gSGS a G50 88 SoS RS 88288858 28 uw = NU ~ Nonusable, make no external connection. These are reserved for future use. el TEXAS 2 INSTRUMENTS

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DATA PATH UNIT (DPU) SS SEES eo > DPU Terminal Functions TERMINAL vo | BUFFER DESCRIPTION NAME NO. TYPE DPU Control Signals ATLATCH 42 CMOS | AT read/write buffer latch control. Data is latched in the AT read/write buffer on the rising edge of this input. BTR 38 TTL Bus transmit/receive. CPU D bus transceiver direction control. This signal is sourced by the cache controller or connects to the ATU LW/R signal in a non-cache system. CLKSEL 34 CMOS | Clock select input. Used for inverting the CLK2 input. L 386DX or 386SX H Reserved DOE 37 TTL Data output enable control, CPU D bus transceiver output control. This signal is sourced either by the cache controller or, in a non-cached system, by the ATU. [peusi S| ns DPUS3 45 [1 | CMOS AT bus conversion control ELWBEN 35 CMOS | EL bus write buffer enable L Disable write buffer H Enable write buffer Lwik 46 |__| | CMOS _|Latched write/read signal from ATU MPCKL 48 | o| pre | Latched parity low byte status SATB 40__| 1 | CMOS _|CPU/EL bus source/destination control for the AT bus buffer SELDPU 50 CMOS | DPU word select L_ Low word (015-0) in a 16-bit or 32-bit system H High word (D31—16) in a 32-bit system Note: SA1 must also be tied low in a 16-bit system. WBCLK 36 TTL Write buffer clock. Latch signal for cache controller posted write opera- tions. Write data is latched on the rising edge of WBCLK. Data Signals Do-D2 30, 27,25, | VO | 3S16PU | CPU datalines 0-15 D3-D5 22, 20, 18, D6-D8 15, 12,9, D9-D12 7,4, 1, 99, 013-015 96, 94, 92 EDO-ED2 28, 26,24, | VO | 3S16PU | EL bus data lines 0-15 ED3-ED5 21,19, 17, ED6-ED8 13, 11, 8, ED9-ED11 5, 2, 100, ED12-ED14 97, 95, 93, ED15 90 MDPL. 10 3816PU_| EL bus parity bit for the low byte 3816PU_| EL bus parity bt for the high byte SS TEXAS a2 INSTRUMENTS POST OFFICE BOX 655903 * DALLAS, TEXAS 75265 13

DATA PATH UNIT (DPU) SEs DPU Terminal Functions (continued) TERMINAL BUFFER SDO-SD3 61-63,65 | I/O | 3S24PU | AT bus system data bits 0-15 SD4-SD9 67-72 $D10-SD13 74-77 XD4-XD7 57-60 [cue Ts tT CMOS ToPUsystemelock [Reaby Tse TT tm [PU or et busreadyinpt SAO [ee [1 | Te [ArbussystemaddressiineQ [sar | 83 || TTL [AT bus system address line 1. Must be tied low ina 16-bit system. | [Ruf ee e7 fT Nonusabie, make no external connection. Reserved for future use. | GND 6, 14, 23, Ground 31, 39, 49, 56, 64, 73, Veco 3, 16, 29, Supply voltage 41, 54, 66, Sis p Pe a TEXAS % INSTRUMENTS

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MEMORY CONTROL UNIT (MCU) TE ~ TACT83442 Memory Control Unit (MCU) The MCU is a high-performance, programmable DRAM controller with an address range of 32M bytes. The MCU provides several access modes, including normal, page, word-interleave, and page block-interleave modes, as well as programmable DRAM timing parameters. Its physical memory address is generated by the on-chip page mapping RAM (PMRAM). Each page may be enabied or disabled, allowing flexible memory configuration for shadow RAM and EMS 4.0 features. The MCU can directly drive up to 36 DRAM devices. If the memory array contains more than 36 DRAM devices, then buffers are required for the memory address and write enable signals. DRAM configuration and timing parameters are programmed through the configuration registers and PMRAM in the MCU. Upto eight MCUs can be cascaded to expand the system memory. The MCU base address register and page mapping RAM combine to provide memory configuration control in a multiple MCU environment. When multiple MCUs are used, they are initialized automatically at power up as MCU0, MCU1, . .. MCU7 for configuration. Since each MCU can manage up to 32M bytes, a fully cascaded system will provide control for up to 256M bytes. memory array organization The MCU configures system memory according to the processor being used. In a 386DX system, the MCU can support two 32-bit banks of DRAM, while in a 386SX system it can support four 16-bit banks. The MCU defines DRAM type based on bank pairs, allowing for a mixture of DRAM types in system memory. However, when memory interleaving is used, each bank pair must use identical DRAM types. DRAM access modes and timing The MCU supports normal and page DRAM access modes, as well as interleaving on page block, odd/even word, or double-word boundaries (depending on the memory data width of 16 or 32 bits). Interleaved banks must use identical DRAMs. Four interleaved 16-bit banks may be used as two pairs of banks, in which case the pairs may use different-sized DRAMs, but the banks within pairs must use identical DRAMs. If four banks are organized in two pairs, ~ the banks within each pair must be interleaved. DRAM timing information is programmable for each pair of banks through separate configuration_registers. Programmable parameters include RAS and CAS pulse durations, RAS and CAS precharge times, CAS to RAS delay, CAS active write delay, RAS to memory address delay, and memory address to CAS read delay. The MCU supports a programmable DRAM refresh scheme with staggered CAS before RAS. SS TEXAS “2 INSTRUMENTS POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15

MEMORY CONTROL UNIT (MCU) el MCU terminal assignments The MCU is packaged in a 100-terminal QFP. The MCU Terminal Functions Table gives a description of each terminal. See Figure 1 for details of the I/O buffer types. Top View le 33 § F P\\=ls lo Fey irr PSEEEEE RSSSS22 ESS ELeerSeusgy PEEEEEUECEEAEEESLESEECEEELELEE BRRERRERARERGSESBESSSSRSRERRABRS A20GOUT {] 81 so [| BES E015 82 a9 1) BE2 —p14 a3 48 1 BEI ED13 Q 94 47) BEO E012 (| 85 46 D Voc eo11 qj 86 45 [| ERESET GND {| 87 440 Wh ED10 Q a8 43 0 oc Eps | 89 42 0 mio Eps 90 41 B cLK2 eo7 q 91 TACT83442 ao Bp GND EDs 92 39 | READY Vee G 93 38 [| READYO EDs Q 94 37 D ADS Epa qj 95 36 0 LAP E03 qj 96 35 [) TANP Ep2 | 97 34D Veco £01 98 33 ff osc_12 Epo q 99 32 [| REFHLD cout q 100 31 ff) cIN ramrmonaolESPZPPrPARaNRARRRRRS MlS|=|9 |= aInie Ger PHAGE LVS Yin Ils Qioio in w $18 |a(8 lo 218\\8 8232221293222 SBR eseRRE gebeg seb *282292622395 5928 S58 le MCU Terminal Functions BUFFER TERMINAL vo | BY DESCRIPTION NAME NO. TYPE EL Bus Signals ADS 37 [ 1 | TTL [Address status control signal BEO 47 TTL Byte enable 0. Used with the 386DX to enable data bits 0-7. The 386SX uses the signal BLE (Byte Low Enable). BET 48 TTL Byte enable 1. Used with the 386DX to enable data bits 8-15. The 386SX uses the signal BHE (Byte High Enable). BE2 49 TTL Byte enable 2. Used with the 386DX to enable data bits 16-23. The 386SX uses the CPU address line A1_ aun TEXAS % INSTRUMENTS

16 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265,

MEMORY CONTROL UNIT (MCU) an > MCU Terminal Functions (continued) TERMINAL BUFFER NAME No. ie} TYPE DESCRIPTION [iieniesscooene ST high on 386SX systems. [oe JP system ciock SSS [aa at etndconsignd EA2-EA6 51-55 TTL EL bus address bits 2-24 EA7-EA14 57-64 eo eee EA23-EA24 75-76 Sa: )) Sioa EA26/MEMR 78 mode. The terminal definition is selected by mode select bits 2 and 3 EA27/MEMW 79 of the configuration register. EA31/MCUEN 80 ED6-ED10 92-88 ED11-ED15 86-82 [eneset a ‘bs reset [wis aren carve signal eT [esaagane 1 NAYS Beowte Ne ready signals. ee Le LP Mitts inbes nnn cients | Must be ANDed with the other EL bus ready signals. Ra TY wifread contotsignat id [CASO-CASS—4,5,7.8 | O | PRIS [CourmaddossstobesgrasOS —SC—~S [CAS#-CAS7 25, 27-28 | 0 _| PPIE | Column aderess tobe signals 7 ——————s ee MA6-MA10 17-21 [RASO-RASS_2,3,5,24 | O | PPI6 [Row address svabo sna orbanisO-3 = [We 30 | 0 | FRI Wirte enable forBRAMs a cache-based systems (assuming AND gate is used between proces- sor and cache for A20 control.) [ona mc cascade input. Must be grounded errata] ee LP Peano ome nen oneieresievere chain. [TANS a5 [0 | FP10 | ba ocal access witmnopariy [tap 96 | 0 | P10 | EL bustocal access withparty SS eT | Sitcom ng ME tse AS seston and refresh timing. [CRED a rete innibe [Romcs tT [rio | ROM chip select. This signal is inactive if shadow RAM is enabled. | el TEXAS % INSTRUMENTS POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7

MEMORY CONTROL UNIT (MCU) el MCU Terminal Functions (continued) NAME NO. TYPE GND 6, 16, 26, Ground 40, 56, 74, ee | 46, 65, 93 SS TEXAS % INSTRUMENTS

18 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

~ absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Input clamp current, liq (Vj <O Or Vi >VoC) .. 6. cece eee e eee een eees #20MA Output clamp current, Io (VQ <0 Or VQ > VG)... eee e eee eet eee e este eect ee eeeeeeess £20MA Continuous output current, Iq (Vo = OtO VEG) oe. cece eect eee eect eee teen cece eee £25MA NOTE 1: All voltage values are with respect to all GND terminals connected together. recommended operating conditions a vesg Baton vohage aru oa y ar__Bateryvolage (ATU on) [Nomal__|veg-03__Vegr0.3| Led [vi, _Lowlevelinputvotage =z eves [a] [i input renstiontine_———S~=ir enh Seager) SSCs SS TEXAS 4 INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265 19

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) ee VoH High-level output voltage PP10, 3S v P24, 98 PP2,38,0D | tous2ma || pps [lge=8mAS]SSSCSCSC~S VoL __ Low-level output voltage PP10, 3S fion=t0mA Ss | t~—~<“*;C*~s~tSSSYLCSV pets [lon=t8mA—iPSCSC=« WA | rinaiomioa [ggsy [a a_| eS [icc Guiescent power suppiyeurent’———S~SCS~dCg = SCO | Pp Power dissipation See Note 3 [460 ~«| «mw [0 J [Backup | Voat=S6V— CY lnatt Battery current [Normal Voat=vooosv [00 |_| [larg Fealtine dockouputvequeney [|i Ce NOTES: 2. Hysteresis is the difference between the positive-going input threshold voltage, VT ,, and the negative-going input threshold voltage, VT 3. System environment: 25-MHz CPU without cache operating in pipeline mode. 8-MHz AT bus. Relevant load capacitances equivalent to stated test conditions. el TEXAS % INSTRUMENTS

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~ TIMING AND SWITCHING DATA Page TACT83443 — ATU Slave Cycle: AT Bus Refresh 00.2... c cee cree eee rece erect tte e ett tteterretetsneeerenns 28 Master Cycle: AT Bus DMA Cascade — Capture/Release «1.00... ieee cece eee e ese eeeeeeneeeee 40 DPU Interface: Select COde oo. e ee cece reece eee eee een ene ences tees eee e teens 44 Numeric Coprocessor: 387 BUSY/ERROR wie ccc cece nett teen e ene te een eenee 48 IMCEPPUPTS ee renee eee tnt b etn e tet tttttseerereeees 52 Peripherals: Read/Write Cycle 2.0... ccc cece cece eee etn eter e eben ete t rset etrttreneree 54 TACT83441 — DPU Parity Generation 20... ec eee cee t neers nets tte ete ve eset estestnereenns 62 Parity CHECK 2... cic cece eter e tere etree etter etre etre tenet rete eteeeeeeree 63 SD or XD Data Transfers... eee eee eect eee teen tt eee ete eee eres B64 TACT83442 — MCU EL Bus Interface oo teeter eee eee 66 Memory Interface 2. ccc eect eee tee tet e ete e ieee eet eeee sees 69 CO Ser EO 0) Refresh Hold... eee cence etter tenet t nn etttneeetteeeeenne 7A SS Texas ¥ INSTRUMENTS POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21

Figure 2. Clock Generator/Divider Waveforms

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Figure 3. Reset/PCLK Waveforms

AT BUS INTERFACE UNIT (ATU) ood ATU SLAVE CYCLE: EL BUS SIGNALS timing requirements, T, = 0°C to 70°C | awa [ing Holdtme AOSafercu@nt | ‘Setup time, EA31-EA2, BE3-BEO, and EL CMDst before ‘sut0 CLKQINt 7 Hold time, EA31-EA2, BE3-BEO, and EL CMDs after th10 CLK2INt 7 7 ns Teast Setup tine, CAB and LANP balers OLKAINT [ee th11__Hold time, LAP and LANE attr CLK2INE [es tha Held time, READY after CLK2IN? a Tinie Hold time, MPOKH, MPOKL after LK@NY____———~«| Sid Si 1 The EL CMDs consist of M/iO, W/R, and D/C. switching characteristics, Ta = 0°C to 70°C, C, = 50 pF (unless otherwise noted) PARAMETER TEST CONDITIONS [Vcc =5V= 10% Vec=5V=5% | UNIT [tase _Delaytine CLKANToWA [Si So] | ‘gig _Delaytime OLKZINoATLATGH [Tae os aT eS] ns | NOTE: For 33-MHz operation, the MCU DRAM contro! register CWD bit = 1 el TEXAS *% INSTRUMENTS

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t The EL CMDs consist of M0, WIR, and D/C. B. The ATU timing control register AT write bit is enabled. mode, T2P = subsequent state of cycle in pipelined mode, Tx = any state. Figure 4. EL Bus Waveforms

AT BUS INTERFACE UNIT (ATU) SS ATU SLAVE CYCLE: AT BUS NORMAL 8-BIT AND 16-BIT CYCLES timing requirements, T, = 0°C to 70°C — a | | (guia _Setup tne, MEMES batore ATCIKI [we taza Hold time, MEWCSTS afer BALE| a 15u23__ Setup time, LA23-LA17 before ATCLK|, (See Note 3) (See Note 3) (SeeNote3) | ns | thag Hod time, LAZS-LAIT afer ATOLKL teu2i__ Setup tne, OCS belore ATOLKL a tna6 Hold time, [OCST6 afr ATCLKI a 1gu25 Setup time, IOCHRDY before ATOLKL a tha Hol tm, OCHADY ater ATCLKI a teva. Setup tine, OWS before ATCLK, a thgo__Held time, OWS after ATCLKI [Dae 0s NOTE 4: Default MIN = 2 x CLK2. When early AT bus control trigger is selected, MIN = 1 x CLK2. MAX = MIN + 2x ATCLK. switching characteristics, Ta = 0°C to 70°C, C, = 100 pF (unless otherwise noted) PARAMETER TEST Voc =5V=10% | Voc=5V+5% conornions ta20_Delay time, ATCLK to SYSCLK Gy=sopF [6 eet ea ans vga} Delay time, ATGLK to BALE ou=sopr [8 sf 6 as) 8 sf ms tang Delay'time, ATCLK 10 SA19-SAO and 10 32 10 32 10 22 SBHE (Gas_Dely tno, ATOLK to AT CDS WENCSS-5[ 8 sof Delay time, AT CMDst to SMEMW and — tga Delay tin = 6 22 ni

026 SHEMA MEMCS16 = 0 iS

iga7_Delay time, ATCLK to AT CMDs* [wewcsie-1 [|e sof ao] 0s tT The AT CMDs are MEMW, MEMR, IOW, and IOR. __ +The AT CMDs are SMEMW, SMEMA, MEMW, MEM, TOW, and TOR. ae TEXAS 4 INSTRUMENTS

26 POST OFFICE BOX 655903 * DALLAS, TEXAS 75265

t The AT CMDs are MEMW, MEMR, IOW, and TOR. +The AT CMDs are SMEMW and SMEMR. NOTE: The AT bus cycle states are as follows: Ti = idle, TS = status state, TC = command state, and Tx = any state. Figure 5. AT Bus Waveforms (Normal 8-Bit and 16-Bit Cycles)

NOTE: The AT bus cycle states are as follows: Ti = idle, TS = status state, TC = command state, and Tx = any state. Figure 6. AT Bus Refresh Waveforms

28 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

NOTE: The EL bus cycle states are as follows: Ti = idle, T1 = first state of cycle, T2 = subsequent state of cycle, and Tx = any state. Figure 7. EL Bus DMA Cycle Waveforms — HOLD Request

AT BUS INTERFACE UNIT (ATU) ——— ATU MASTER CYCLE: EL BUS DMA CYCLE — SINGLE TRANSFER MODE (1 WAIT STATE) timing requirements, Ta = 0°C to 70°C Pe a et | Wig Held tine, DRG afer OURAN [sf es Ps Ur | tgu87_Selup time, HOLA before CLK@INT [a es Tgut2_Selup time, READY before OLX2INT a thi? Hold time, READY ater OLK2IN} [sp «i 3 is _] switching characteristics, T, = 0°C to 70°C, C, = 50 pF (unless otherwise noted) [tea0wne —[fa25wre | tesowi | PARAMETER TEST | Voo=5V= 10% | Voc=5V=5% | Voc=5V25% | UNIT CONDITIONS [MIN MAX [MIN MAX| MIN” MAX| ijag_Dalay tne, OLKEN To DRGRE ce Dd [tss9Delaytme,cuxnio ADS ea] es tens Enable time, CLK2IN i ABS Sd ‘isao_Disable time, OLK2IN to ADS. Po cr=o fs ets asf sai ns Tent Enable time, CURANToELGMDST | ——+{ sets st 8 tens | t Enable time, CLK2IN to EA31—EA2 and en43 BES-BEO 5 23 5 19| ns Disable time, CLK2IN to EA31-EA2 and . few weer ae [eal eal eal | {gag_Delay time, OLKAIN To TO a A 8 t The EL CMDs are M/IO, WIR, and D/C. eel TEXAS wy INSTRUMENTS

30 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

t The EL CMDs are M/IO, WIR, and D/C. Figure 8. EL Bus DMA Cycle Waveforms — Single Transfer Mode (1 Wait State)

AT BUS INTERFACE UNIT (ATU) eee eee ATU MASTER CYCLE: EL BUS DMA CYCLE — BLOCK DEMAND TRANSFER MODE (0 WAIT STATE) timing requirements, T, = 0°C to 70°C Raga rere rere | 1ayas_Selup tine, DREGn before CLINT a Tgua7__ Setup time, HOLDA before CLKAINT [ies] igut2_Selup time, READY before CLINT [ets [thigHoldtime, READY after CLKaINT PS Ts switching characteristics, Ta = 0°C to 70°C, C, = 50 pF PARAMETER TEST | Voc =5V = 10% | =5Vz 10% | Voc =5V+5% | =5V25% | Veo =5V=5% | =5V+5% UNIT conpmmions [fase Deayiime, CueNDACRT CSCS fara ‘ago Delay time, CLK2IN to AOS [ess | tena Enablotine, CLKANto ELGMOST | —s«dP S| 8] Os Delay time, CLK2IN to EA31~EA2 and CN a Enable time, CLK2IN to EA31-EA2 and ten4S BES_BEO 5 19} ns tyas Delay time, CLK2IN to TC [sss ais ass t The EL CMDs are M/IO, W/R, and D/C. TEXAS * INSTRUMENTS

32 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265

t The EL CMDs are M/IO, WIR, and D/C. NOTE: The EL bus cycle states are as follows: Ti = idle, T1 = first state of cycle, T2 = subsequent state of cycle, and Tx = any state. Figure 9. EL Bus DMA Cycle Waveforms — Block Demand Transfer Mode (0 Wait States)

T The EL CMDs are M/IO, WIR, and DIC. t The EL CMDs are M/IO, WIR, and D/C. NOTE: The EL bus cycle states are as follows: Ti = idle, T1 = first state of cycle, T2 = subsequent state of cycle, and Tx = any state. Figure 10. EL Bus DMA Cycle Waveforms — Exiting

34 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265

t The EL CMDs are M/IO, WIR, and D/C. NOTE: The EL bus cycle states are as follows: Ti = idle, T1 = first state of cycle, T2 = subsequent state of cycle, and Tx = any state. Figure 11. EL Bus DMA Cycle Waveforms - Cascade

NOTE: The EL bus cycle states are as follows: Ti = idle, T1 = first state of cycle, T2 = subsequent state of cycle, and Tx = any state. Figure 12. AT Bus DMA Cycle Waveforms —- HOLD Request

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tT The EL CMDs are M/IO, WIR, and D/C. +The AT CMDs are SMEMW, SMEMR, MEMW, MEMA, OW, and IOR. NOTE: The EL bus cycle states are as follows: Ti = idle, T1 = first state of cycle, T2 = subsequent state of cycle, and Tx = any state. Figure 13. AT Bus DMA Cycle Waveforms — EL Bus Signals

AT BUS INTERFACE UNIT (ATU) el ATU MASTER CYCLE: AT BUS DMA CYCLE - AT BUS SIGNALS timing requirements, Tg = 0°C to 70°C [t=20mHe [ t=25wHz | 1=39MHz _| eg eer [Min Max MIN” MAX | MIN, MAX | [iewse Seupime OCHADYeeAT TTT | linge Hold ime, (OCHRDY afteraTOLKY —_—SSSCSCSC~iS | Cd dr switching characteristics, Ta = 0°C to 70°C, C, = 100 pF (unless otherwise noted) mma |aromonone agai ages] or [igor Deayame ATCIKTOBALE andAEN | G=80eF [6 asf as] eas ns Delay time, ATCLK to LA23-LA17, 'd24_Sa19-SA0, and SBHE 10 32 10 82 10 32 [gag Delaytme,ATCUKoTOR_—=tSSCSCSC~—~—SC TTC Delay time, ATCLK to IOW, MEMW, a TEXAS *% INSTRUMENTS

38 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

Figure 14. AT Bus DMA Cycle Waveforms — AT Bus Signals

AT BUS INTERFACE UNIT (ATU) eee eee ATU MASTER CYCLE: AT BUS DMA CASCADE — RELEASE/CAPTURE timing requirements, T, = 0°C to 70°C FP a on | Taiz Seu tine, HOLDA before OLK2INT a switching characteristics, T, = 0°C to 70°C, C, = 50 pF(unless otherwise noted) PARAMETER TEST | Voeo=5V=10% | Voc =5V25% | Veo =5V=5% cones ane wax [win wax [MN aX | idan __ Delay tne, GUNS BAGH Le ee | Tend Enable timo, CLK2IN io EL GNDST a Od Enable time, CLK2IN to EA31-EA2 and ten44 BES_BEO 5 21 ns ‘agar _Disabio tine, ATGLK to AT OMDSF [eo |e =| 8 =, 8 [rs | Disable time, ATCLK to SAT9-SAO and iGsig Diablo ine, WASTER Lanta? | G-0 [| 8 | 5] sm] s_| 1 The EL CMDs are M/IO, W/R, and D/C. — +The AT CMDs are SMEMW, SMEMR, MEMW, MEMR, TOW, and iOR. el TEXAS ad INSTRUMENTS

40 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265

+The AT CMDs are SMEMW, SMEMR, MEMW, MEMR, IOW, and IOR. Figure 15. AT Bus DMA Cascade Waveforms — Capture/Release

The AT CMDs are MEMW, MEMR, IOW, and IOR.

1 I —r tas2 I | | —r- tas2

7 T T T H T 7 T

1 T T 1 1 T 1 7

t The AT CMDs are SMEMW, SMEMA, MEMW, MEMR, TOW, and iOR. Figure 16. AT Bus DMA Cascade Waveforms — AT-to-EL Bus Cycle Conversion

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NOTE: The EL bus cycle states are as follows: Ti = idle, T1 = first state of cycle, T2 = subsequent stale of cycle, and Tx = any state. The AT bus cycle states are as follows: Ti = idle, TS = status cycle, TC = command state, and Tx = any state. Figure 17. |OCHRDY Drive Waveforms

t The DPU control signals consist of SAO, IOCS16, MEMCS16, XDSEL, and the AT CMDS (SMEMR, SMEMW, MEMW, MEMR, IOW, and IOR). Figure 18. Select Code Waveforms

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t The AT CMDs are SMEMA, SMEMW, MEMW, MEMR, TOW, and TOR. Figure 19. ATLATCH Waveform — AT-to-EL Data Transfer Cycle

Figure 20. ATLATCH — EL-to-AT Data Transfer Cycle Waveforms

46 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265,

NOTE 5: System has no 387. BUSY is driven by the ATU.

When CPUSTEN is high, BUSY is held low for 10 CLK2 cycles after ERESET is driven low.
If there is no 387 installed, NPERR is sampled high at the falling edge of ERESET. In this case, BUSY and PEREQ toggle every 16

Figure 21. 387 Identification Waveforms

Figure 22. 387 BUSY/ERROR Waveforms

48 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

50 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265

Figure 25. FLUSH Waveforms

Figure 26. Interrupt Waveforms 52 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265.

Figure 27. OSC_12/SPEAKER Waveforms

AT BUS INTERFACE UNIT (ATU) A PERIPHERALS: READ/WRITE CYCLE timing requirements, T, = 0°C to 70°C fF i a | | Tguaa__Solup tine, SAT9-SAD and REN bore TORTOW] [so [| 0 | =| thge Hold timo, SAi9-SAO and AEN afer IOFOWL [200s] [was Pulse duration, OATOWnighorlow ————SSS*Y SC C* Ca C*YCOCd ns ['suss Setup time, x07 xOO below OW ————S—S~C~s SCY iY ids | ‘ge Hold time, XD7-XD0 after {OW a CO switching characteristics, Ta = 0°C to 70°C, C, = 50 pF TEST gl Voo=5V Voc =5V=5% | Voo=5V UNIT PARAMETER CONDITIONS ‘ase Disable time, TOR andiOWtoxo7-xD0__| ‘|? ss| 7 s| 7 35| ns _| "go7 Delay time, XD7-X00 0 KEYBCS [eo es] Teas Delay tine, SATS-SAO and AENIOREVEGS |__| 8 a0[ 6 a0] 8 40[ ns | Delay time, SA19-SAO and AEN to a TEXAS *% INSTRUMENTS

54 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

AT BUS INTERFACE UNIT (ATU) ee ee eee AEN \\ # | | [ | | | | << tuts Sera ioRiow | ‘ 7 | x

1 LOSS | hod

XD7-XDO H ! SOOO freed). —— REY xD7-XDO y | (Write Cycle) ‘ | —, tas7 ! — tas7 | i 1 1 tr taso hae taso Figure 28, Peripheral Read/Write Cycle Waveforms ——— TEXAS *y INSTRUMENTS POST OFFICE BOX 655903 ® DALLAS, TEXAS 75265 55

DATA PATH UNIT (DPU) WRITE CYCLE: CPU/CACHE CONTROLLER HOST timing requirements, Vcc = 5 V +10%, Ta = 0°C to 70°C TT [isut___Soupiime, DrEDobetorewOOKT CSCS [int _Holdiime, DisDoaferwWBCKT SSCS | [tw7e_ Pulse uaton,ATCATCHiow | ['sué Setup ime, D160 bofow AAT! SSCS [tng Hovd tine D15-00 afr ATLATCHY SSS | [tsug___Delaytime, WECLK to ATLATCH ts] switching characteristics, Vcc = 5 V «10%, Ta = 0°C to 70°C, and C, = 100 pF (unless otherwise noted) [anaes ne ['eas__Erablotine, ETS eDomBOE—CSSSCSCS~—C—~—CSCSCSS Bs | [iss Disable tine, EDISEDO rom DOE ———SSdSSS Os [lene Enabiotine, EDISEDOKomBTIA SSS | [tus Delay tine, WECLKiwEDTSEDO SSCS ts | [iss _Oalayiime, Dis-DoweDISEDO CSCS ts [iso Delayiine, ATLATCH to SIBSOO___—SSCd S| [isit Delaytine. PUSS DPUSI to SISO [tig Oeaytime, 075-DotSISSDO_——SSCSCSC~dSSSSSCSCSCSCSCSCSCSCSSSSdYC 2s | ltsia Delay tine, ATLATCH to XOTROO SPSS 8s [tis Delay time, DPUSS-DPUSTIoXOTXOO——s|SSSCSCSCSC~d 8s [ts17 Delay me, O1s-DOtoxD7 XDD SSS Ss 20s | LS TEXAS % INSTRUMENTS

56 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

Figure 29. Write Cycle Waveforms — CPU/Cache Controller Host

DATA PATH UNIT (DPU) Oe READ CYCLE: CPU/CACHE CONTROLLER HOST timing requirements, Voc = 5 V +10%, Ta, = 0°C to 70°C [{suaa _Setupiine, DPUSS_OPUSI before ATLATORT ——SSCSC~dCO os [ines Holdtine, DPUSS-OPUSI aferaTLATOHT [tsu25__ Setup time, SDIS-SDO bears ATLATOH? SSCS [ing6 Hold tine, SDIS-S00 aterATMATOHT Cd ds [1su2e Setup tine, XOTXOD below ATLATOHT SSCS is] [thes Holdtime, XO7-XOO after ATLATCHT, Ts switching characteristics, Voc = 5 V +10%, Ta = 0°C to 70°C, and C, = 50 pF [_____raraweten rs conoions [win waxy UNIT] [iene Enabietine DisDofemBOESSCSC~“‘“SSC“‘CSSC™#C(“‘(#NNNNNN“NUYNW st [as [usta Osebietine, DisDohomBOE ST tr [temo Enable time, DIsDofomBTA Pts] [gist Disabletine, DISDOMeMBTA Td Ls [ts20 Delayime, EDISEDOTODIEDD CT SSC~dC As [tsar Deleyiime, SATBtoDISDO SCT Si 8 | [toe Oelaytime, ATLATCH DISH Cid S| [isos _Oelayiime, DPuSs-DPUsieDIsDOCdESSSCSC~CSCSCSY Ss [tga5 Delay ine, SD15-SDOwOIEDO Sd SSSSCSC~d | [tsa7 Delaytime, XD7-XDOtoD1SDO 0s ee d TEXAS % INSTRUMENTS

58 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265

Figure 30. Read Cycle Waveforms — CPU/Cache Controller Host

Figure 31. EL-to-EL or EL-to-AT Data Transfer Waveforms:

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Figure 32. AT-to-EL Data Transfer: DMA Controller/EL Master Host (DOE High, BT/R Irrelevant)

Figure 33. Parity Generation Waveforms

62 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

Figure 34. Parity Check Waveforms

Figure 35. SD or XD Data Transfer Waveforms

64 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

T Vref is the reference voltage with respect to which the time intervals are defined. Figure 36. CLK2/ERESET Waveforms

MEMORY CONTROL UNIT (MCU) aa EL BUS INTERFACE timing requirements, T, = 0°C to 70°C [_t=20MHz | f=25MHz | f=99MHz ages agree or [MIN MAX] MIN’ MAX MIN’ MAX | [ta _Seupime ABSbeirecuRe Cd) PCT [ing Holdtime, ADSaherou@y 8 | [teyeSetuptime, EL CWDsTbeforeckey CY] ds [ing —_Foldtime, ELoMOsTafercu@t—SC*dYSCS [tsus Setup ie, A2-AQT (nctucing gated Aad) below OLK@T “|e ——S*d SYS [ins Holdtime, A2-AG1 (ncudng gated Azd) afer GuK@t———| 8 —*| sid | Setup time, A2-A31 (including gated A20) before CLK2t netomat Te fe fe | Setup time, A2-A31 (including gated A20) before CLK2t [wren enone et ee | [ious Setup ime, BES BEORoOwO@T—SSCSCSC~“‘“itCCSBSSC*dSC [ine Hottie, Be8-BeOatercu@r TAT i | [tsuie_Sctuptine,D1S-DD before cuK@i_——SSCSCS~C~iSCSCd | [imi _Holdtime, Dis-DoafterGiKat_—_——SsSSSSC«dT Sd T The EL CMDs consist of W/R, M/IO, and D/C. NOTES: 9. RAS/CAS active point is at the center of T2/T1P (RCAP bit of DRAM control register ~ 0). 10. RAS/CAS active point is at the end of T2/T1P (RCAP bit of DRAM control register = 1) switching characteristics,T, = 0°C to 70°C, C, = 15 pF (unless otherwise noted) [_f=20MHz | f=25MHz | f=33MHz | CONDITIONS [ MIN” MAX] MIN MAX "MIN MAX | [ts9__Delaytime, CLKatoREADYO TTP a Pas | [tao _Delaytime, A2-AB1, MAO, andD/CtoiAP [TST aa [sans | [tgi1__Delaytime, A2-A31, MMO,and DCtotANP | [Sa Tai Pia | ns | [ten13_Enabletime, CLk2toD1s-D0_ |= tooprF [4 sf 4 eof a 20 ns | [tais1s Disabletime, CLk2toDis-D0 TT ceso [ese a0 fa 20 ns | [tats Acvoss time, CLK2 10 Dis-D0 Sid = OF |S | SS TEXAS % INSTRUMENTS

66 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

mode, T2P = subsequent state of cycle in pipelined mode, Tx = any state. t The EL CMDs consist of W/R, M/IO, and D/C. Figure 37. EL Bus Interface Waveforms

Figure 38. EL Bus Interface Waveforms — READY 68 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265.

+ R2M = MA10-MA0 hold time from RASn. One to two CLK2 cycles as defined by MCU DRAM timing registers. +m2c = CASn hold time from MA10-MAO. One to two CLK2 cycles as defined by MCU DRAM timing registers. Figure 39. Memory Interface Waveforms

Figure 40. Cascade Waveforms

70 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

Figure 41. Refresh Hold Waveforms

MEMORY CONTROL UNIT (MCU) SS MECHANICAL DATA 208-Lead Quad Flatpack (ATU) 30,4 29,6 28,2 MAX 157 oy FS 104 28,2 ood Es 29,6

200 ES ss

0,5 NOM 0,2 NOM ote 3,9 MAX | CoM A Tl a oP 08 0,15 _| wz MIN STANDOFF ALL LINEAR DIMENSIONS ARE IN MILLIMETERS TEXAS % INSTRUMENTS

72 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

MEMORY CONTROL UNIT (MCU) ——— SS ~ MECHANICAL DATA 100-Lead Quad Flatpack (DPU and MCU) 25,4 24,6 | 80 51 | TNOORRRGAROARGARAAABRARAANo| | WOOO OOOO | 81 Co —rr— 50 184 == == we SS ES ax == == oI FESS a1 VO) RTA AY AYOUOTO AVA) AYRU AURA) RUA) OUULUUUUCUUUUUUUULUUOUUDCOUU0 _ |" 0,65 NOM 0,4 MAX 0,2 2,1 MAX 0,1 | _AUNNOOoOONNND mn im 00 00 Doon + TT qi 0,05

27 MIN STANDOFF

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. TEXAS % INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265 73

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Product Information

TACT83000 specifications and overview.

Summary

AT CHIP SET

Description

AT CHIP SET

Source title TACT83000 Datasheet(PDF) - Texas Instruments

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