TA8772AN TOSHIBA | Alldatasheet
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TENTATIVE TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC PAL/ SECAM/ NTSC BASE BAND 1H DELAY SYSTEM FOR COLOR TV OR VCR The TA8772AN has two chips, a bipolar chip and a CCD chip, in a package. CCD chip consist of two delaylines which operate to oN delay R-Y and B-Y signal. Bipolar chip operate to control a the signals which is processed by CCD stage. oo - wy S soy seh a FEATURES a a ud Bipolar stage ea ircui F i level GC circuit (For correcting output level) SD1P30-P-400-1.78 @ LPF. (For reducing CCD clock) Weight : 1.99g (Typ.) @ DC clamp circuit (For reducing the difference of DC level between delay signal and direct signal.) @ Mode sw (For control output signal by PAL, NTSC or SECAM ident) @ 225fq VCO circuit (For making CCD clock) CCD stage @ CCD drive circuit @ Sample & Hold circuit @ Input bias circuit @ Synctip clamp circuit (This device’s dynamic range bear no relation to change of APL on adopt this circuit) @ Delay time of 1H consist of supply 225fy clock. TOTAL @ This device can operate by the smallest external parts because of include CCD drive circuit, bias generator circuit and output amplifier for support CCD circuit.
961001 EBA2
@ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fall due, to theit inherent electrical sensitwity and vulnerability to physical stress. i i the responsibilty of the buyer, when utlizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified ‘operating rangot as tot forth in the most recent products pecificatione. Alzo, pleaze keep in mind the precautions and conditions tet forth in the TOSHIBA’ Semiconductor Reliability Handbook @ Ihe Products described in this document are subject to foreign exchange and foreign trade control laws The [Information contained herein is presented only as a guide for ‘the applications, of our products. No responsiblity is assumed by, TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. © The information contained herein is subject to change without notice 1997-11-05 1/22
af Halla a “d's 5 Lf rere ccs ai AGC Fad] f—1 4 3 L\\ L\\ Reon Ren aca F FR sn | | Je —— a ald on [Se hs A stp [ Ee4 Jj | fh lee Ko @ @ aon 6) © @ Ao ® io) (® (e) Oo ic) ie) & tLe ark Slade te as oJ deh | ohh de S4°h 49v St 2 ° 8, Oo eS oo Lo ——_ scp — O (Sand Castle Pulse) 1997-11-05 2/22
aN | PIN NAME FUNCTION INTERFACE CIRCUIT This is a terminal for Vee q R-Y Clamp Det. |detecting DC clamp level of R-Y signal. This is a terminal for B-Y Clamp Det. |detecting DC clamp level g of R-Y signal. This is output terminal of 2 |RY to ccD RY signal. A This terminal connects to Vee a 160mv, pin 15 of CCD circuit. g Ep ~< A: 4.30V 2 1000 B: 4.55V ® £ 8 nllliin This is output terminal of 4 3 B-Y signal. A 3 |B-Y to cD This terminal connects to 180mv . rn p-p pin 13 of CCD circuit. A: 430V B: 4.55V This is terminal for vec g R-Y AGC Det. - 8 GC Det detecting AGC. ry (10 | | acc | Ke C"] DC 3.9V B-Y AGC Det This is terminal for ° detecting AGC. Det This is power supply Vec terminal for supplying 9V (Typ.) to bipolar circuit. Yec S This terminal is connected : ‘ . to GND via 10kQ, This is Filter Adj. terminal for adjusting © Dg DC 1.3V internal filter. & 1997-11-05 3/22
aN | PIN NAME FUNCTION INTERFACE CIRCUIT Vee A je ie i A 1kQ c 7 |s.cp. in Wiss input terminal for @ a A: 7.80V B : 4.45V Cc : 0.40V Vee S This terminal outputs KO result of phase comparison © { [i PLL Det. between internal VCO and DC 4.2v horizontal input signal. #1 H Vec S This terminal outputs clock NW Clock pulse which is used by © CCD circuit. < g g 0.4Vp-p 3 DC 2.3V voo 50k 11 |Clock In This terminal receives clock MW pulse for CCD circuit. 0.4Vp-p DC 2.3V This terminal is Vss 2 Iv terminal for CCD circuit. 5S Connect this terminal to GND. This is input terminal of B- | Yoo . 13 {Vint Y signal for CCD circuit Vos 180MVp.p A: 2.50V i = B : 2.25V Sg «a anllin v This is input terminal of B- IN2 Y signal for CCD circuit 8 160mVp, pp A: 2.50V B: 2.25V 1997-11-05 4/22
aN | PIN NAME FUNCTION INTERFACE CIRCUIT This terminal is power supply terminal for v . DD supplying 5V (Typ.) to CCD circuit. aT Ly Vv This terminal outputs - ouT2 delayed signal of R-Y. Yoo 230MVp-p A: 3.50V Bs 3.15V 16, amo = 19 A V This terminal outputs = 8 ouT1 delayed signal of B-Y. 270MVp-p A: 3.50V B : 3.15V Fi A Vec wily This terminal controls OB2 output DC level of pin 16. vo Le 120 Me Dc 1.5V 18 |v This terminal controls ® oB1 output DC level of pin 19. This terminal is applied VGG Vcc x2 voltage by internal DC 10.5V voltage booster. This terminal is GND terminal for bipolar circuit. aT Wy This is input terminal of R-Y fi ccD . Mt rom delayed R-Y signal. ”° . 230MVp-p A: 4.50V 22 10 B : 4.15V
30 S rn
This is input terminal of < B B-Y from CCD | delayed B-Y signal. 270MVp-p A: 4.50V B: 4.15V 1997-11-05 5/22
aN | PIN NAME FUNCTION INTERFACE CIRCUIT Vee ch OF This terminal controls the ° pc gain of internal circuit for @ MODE SW PAL, SECAM or NTSC. PAL: 83V wey level is 6V > >| SECAM : 4.6v “ NTSC: 0.0V Vec ® bs This terminal controls sw 8 pc of calculator for delayed MODE SW2 signal and direct signal. © PAL = 8.3V ey level is 3V cit.| secam : 4.6v yp). NTSC: 0.0V 26 |B-Y In wns ss ynput terminal of B-| vc 3 yu u tgnal. “ 350MVp.p i” DC : 5.25V 20 rh anion 27 RY In wns i input terminal of R. g OF gna. 320MVp.p DC : 5.25V is i vec aprtllon. B-Y Out ms is output terminal of g gnat. 350MVp-p 29, DC : 4.55V O 30 < 30 |R-Y Out rs is output terminal of . gnet. 320MVp.p DC : 4.55V 1997-11-05 6/22
MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Power Supply Voltage Vec/Vppb 12/6 Pp (Note) [SSS SSS SW Operating Temperature —20~65 Storage Temperature -55~150 Input Signal Voltage a GND = 03-Vec +0.3/6ND=03-Vpp +03 (Note) When using the device at above Ta=25°C, decrease the power dissipation by 12.8mW for each increase of 1°C. RECOMMENDED OPERATING CONDITION [3 _|vec py | aa} a0] a5] Vv Wop (C0D)
ELECTRICAL CHARACTERISTICS
Bipolar electrical characteristics (Unless otherwise specified, Vcc =9V, Ta = 25°C) TEST } _eranacrensme | smoot] test conomon | wm | ve. | we. | unr | CUIT Power Supply Current | Tee | — | Wore 8) | 177] 250] 323 | mA_| (Note 62) | 395] 450 | 505 | [ote 62) | 428| 450 | 472 | [ote 82) | 4a 450 | 472 | (Note 63) | 285| 450 | 6.15 | [rine | Ve _| (Note Ba) a (Note 63) | 285| 450 | 6.15 | [ring | Va | [___(Wete ba) | 1.82) 215 | 28 | srerminal (Note 84) aii (Note 85) | 428| 450 [472] v (ote 85) | 428| 450 | 472 | [ete 82) | 3.95 450 | 5.05 | (Note 66) | _428| 450 | 472 | Pin 29 Difference] _dV29 (Note B6) -0.005] 0 | 0.005 | ete 87) | _428| 450 | 472 | Pin 30 Difference] _dV39 (Note B7) -0.005{ 0 | 0.005 1997-11-05 7/22
CCD DC electrical characteristics (Unless otherwise specified, Vpp =5V, Ta = 25°C) co CUIT [Power Supply Current | Icc_| —| (ote ci) | 40 | 120 | 240 | mA | [ote 2) 4a | 2a | 3a | [ Pints | Vis | | (Note cay) | 14 [24 | 34 | Terminal [| (Note c2)_ | 24 | 31 | 44 | Voltage [ote 2) 0s fa [a] CY [ote ca) os | 4a | at | | (Note ca) | 24 | 31 | at | Ppin2o | V2p | Note ca) 9.0 | 0.5 | 12.0 | AC characteristics Bipolar electrical characteristics (Unless otherwise specified, Vcc =9V, Ta = 25°C) cme [ome fren [on [ow [oe CUIT feeotoanidereGal Pa |, [Woes Tata tas tieariy OL tan [ete sro =a aa | 20 Linearity 7 1 % four vos (22 —[ Vo [eter fae [oan | oar [pins | Vor | ' | (Note 613) | 039 | 040 | 041] Yer ei ea Level [pins | Pur | | [ (Note 815) | 0225 | 0.25 | 0275 | [RP Pulke Delay Time | Rep | 1 | (Note 16) | 0.00 070 | 100 | 7a _| Pr fo) | For [1 | (Note 817) | 1.50. 1.60 | 1.70 wine | CPF fy @) | Fron [1 | WWete B18) | 1.50-[ 1.60 [1.70 | wine | [TRAP fo (1) | Tor | 1 | (Note 619) | 320 | 3.40 | 355| wire | FrRAP fp (@) | Toa | 1 | (Note 820) | 320 | 340 | 355 | Mine | [TRAP Attenuation Value 7] Tat1__| 1 | (Note 821) | — | -40 | -30] 3 _| [TRAP Attenuation Value 2| Tay2 | 1 | (Note 822) | — | -a0 | -30| 8 | row ne ee ef, | tern Peas | inpedance [Wote 624 [340 | 505 | 670 | [sw Threshold Voltage | Vani | 7 | (Note 825) | 59] 60 | 61] v_| [sw Threshold Voltage | Vena | 1 | (Note 826) | 29 | 30 | 31] v_| [VCO Center Frequency | feen | 1 | (Note 827) | 2.45 | 350 | 460 | wire | freqenge | fmon_| + | ores | 975 | ean | 60 | me | frequen” | fn [1 | esa | 0 220 | 930 | me 9997-11-05 8/22
CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. MAX. UNIT CUIT VCO Freq. Control Sensitivity fsen (Note B30) 2.30 | kHz/V APC Pull in Range (+) | fop | 1 | Wete sa) | 46] 53 — | Kee | APC Pull in Range (-) | Fpm | 1 | (Note 832) | -46 | -53 | — | kHz | VCO Output Level (ote 833) | 0.22 | 035 | 045 | Vpp | AGC Wax Gain [max 1 [ote 63a) [65 | 75 | 95 | ab | AGC Min Gain [Gmin | 1 | WWote 635) [-55 | -35 | -25 | a8 _| AGC Knee Level (7) | Ges | 1 | (Note 836) | 55] 65 | — | ob | AGC Knee Level (-) | G- | 1 | (Note 837) | — [| -65 | -55 | a8 | CLAMP DET (+) [tas [+ | WWote 838) | -10 | 0 | 10 | mv] CLAMP DET (-) [a- | + | (Note 639) | -10 | 0 | 10 | mv _| HP PULSE Threshold GP PULSE Threshold CCD electrical characteristics (Unless otherwise specified, Vpp =5V, Ta = 25°C) TEST CHARACTERISTIC SYMBOL TEST CONDITION fn, | ove. | ax. | UNIT CUIT VouT1 G Note C3, 6.2 Input-Output /MIN1 1 (Note C3) in (* /VIN2 Freq. Woe c) | =30 | -20 | =10 | Characteristic (*) Note C4) | -30 [ -20 | -10 | Output [Pint9 | Zor | ote cs) | 150 | 300 | 450 |, Inpedance (*) [Pin t6| Zor | (Note C5) >. [REF Pulse (Note ce) | 120 | 125 | 130 | = [Level [Pin 16 | Vipi2 | (Note C6) [120 | 125 | 130 | g [LOW Pulse [Pint9 | Vina | (Note C6) [| 95 | 100 | 105 | ,, 8 |Leve [Pin 16 | Viz (Note ¢6) | 95 [100 | 105 | [Towser LPim79] Var} = [WWete ce) | 95 [100 | 108 | (ote cs) | 95 | 100 [105 | Clock Leakage (Note C7) | — [| — | 700] Level [Pin 16 | LcHk2 (Note C7) P= | = | 700 fom (*) It is necessary that external bais voltage is added to input circuit when sine-wave is inpted. Please control external bias voltage so that input terminal voltage is 0.2V higher than no signal level. 1997-11-05 9/22
(Note) GP PULSE ON : Firstly, Apply SAND CASTLE PULSE to pin7. Then, Apply the voltage equal to GATE-PULSE ee 2 level to pin 7. RP PULSE ON : Firstly, Apply SAND CASTLE PULSE to pin7. Then, Apply the voltage equal to H-PULSE ee level to pin 7. PULSE OFF : Firstly, Apply SAND CASTLE PULSE to pin7. Then, Apply the voltage equal to LOW level fy fy to pin7. (Note B1) Power Supply Current. (1) Pin7 : Pulse OFF. (2) Measure the current that flow into IC. (Note B2) Pin 1~3, 26~28 Terminal Voltage. (1) Pin 7 : GP Pulse ON. (2) Measure the voltage of each terminals. (Note B3) Pin 4, 8 Terminal Voltage. (1) Pin 7 : RP Pulse ON. (2) Measure the voltage of each terminals. (Note B4) Pin6, 9, 10 Terminal Voltage. (1) Pin7 : Pulse OFF. (2) Measure the voltage of each terminals. (Note B5) Pin 22, 23 Terminal Voltage. (1) Pin7 : OPEN. (2) Measure the voltage of each terminals. (Note B6) Pin 29 Terminal Voltage and Change. (1) Pin7 : GP Pulse ON. (2) Apply OV to pin 24 (SW2 on). (3) Apply OV to pin 25 (SW1 on). (4) Measure the voltage pin 29 (V29). (5) Apply OV to pin 24 (SW2 on). (6) Apply 9V to pin 25 (SW2 off). (7) Measure the voltage pin 29 (V29q). (8) The voltage of pin 29 is Vag. (9) The voltage change at pin 29 is V29 -V29a. 9997-11-05 10/22
(Note B7) Pin 30 terminal voltage and change. (1) Pin7 : GP Pulse ON. (2) Apply OV to pin 24 (SW2 on). (3) Apply OV to pin 25 (SWy on). (4) Measure the voltage pin 30 (V3Q). (5) Apply OV to pin 24 (SW2 on). (6) Apply 9V to pin 25 (SW2 off). (7) Measure the voltage pin 30 (V3Qa). (8) The voltage of pin 29 is V39. (9) The voltage change at pin 30 is V39 - V3Qa- (Note B8) Pin 26 Input Dynamic Range. (1) Pin7 : Pulse OFF. (2) Apply 100kHz sin curve signal to pin 26 with, 5.2V bias. (3) Observe pin 3 with spectrum analyzer measure input signal amplitude when 3rd harmonic is -40dB against fundamental wave. (Note B9) Pin 27 Input Dynamic Range. (1) Pin7 : Pulse OFF. (2) Apply 100kHz sin curve signal to pin 27 with, 5.2V bias. (3) Observe pin 2 with spectrum analyzer measure input signal amplitude when 3rd harmonic is -40dB against fundamental wave. (Note B10) Pin 26 Linearity (1) Pin7 : Pulse OFF. (2) Measure V3q —V3¢ at condition mentioned in below table. (3) Calculate followings. ® Get the slopes. ® Get the linearitys. G1 =(V3b - V3) + 0.3 LN1 = 100 x (G1 - G2) + G2 G2 =(V3q - V3¢) + 0.3 LN2 = 100 x (G2 - G3) + G3 G3 =(V3F-V3e) +0.3 LN3 = 100 x (G3 - Gy) + Gq 9997-11-05 11722
(Note B11) Pin 27 Linearity. (1) Pin7 : Pulse OFF. (2) Measure V2q -V2¢ at condition mentioned in below table. (3) Calculate followings. ® Get the slopes. ® Get the linearitys. G1 =(V2b -V2q) + 0.3 LN1 = 100 x (G4 -G2) +G2 G2 = (V2q -V20) + 0.3 LN2 = 100 x (G2 - G3) + G3 G3 =(V2F-V2e) +0.3 LN3 = 100 x (G3 - Gy) + Gy (Note B12) Pin 2 Output Level. (1) Pin7 : Pulse OFF. (2) Apply 100kHz, 0.8Vp-p, sine signal to pin 27 with, 5.2V bias. (3) Measure the output level of pin 2. (Note B13) Pin3 Output Level. (1) Pin7 : Pulse OFF. (2) Apply 100kHz, 0.8Vp-p, sine signal to pin 26 with, 5.2V bias. (3) Measure the output level of pin 3. (Note B14) Pin2 Pulse Ins. Level. (1) Pin7 : Input Sand Castle Pulse. (2) Observe pin 2, Measure amplitude of pulse. (Note B15) Pin3 Pulse Ins. Level. (1) Pin7 : Input Sand Castle Pulse. (2) Observe pin 3, Measure amplitude of pulse. (Note B16) RP Pulse Delay Time. (1) Pin 7 : Input Sand Castle Pulse. (2) Observe pin7 and 3, Measure the period from leading at edge at pin7 to trailing edge at pin 3. (Note B17) L.P.F. fg (1) (1) Pin7 : Input Sand Castle Pulse. (2) Apply 2.0V to pin 8. 9997-11-05 12/22
(3) Apply 4.5V to pin 28. (4) Pin 24 : OPEN. (5) Apply 9.0V to pin 25. (6) Input 0.8Vp-p sin wave signal to pin 23, Measure frequency response at pin 29. (Note) Get the frequency when amplitude is -3dB against amplitude at 100kHz. (Note B18) L.P.F. fg (2) (1) Pin7 : Input Sand Castle Pulse. (2) Apply 4.5V to pin 1. (3) Apply 2.0V to pin 4. (4) Pin 24 : OPEN. (5) Apply 9.0V to pin 25. (6) Input 0.8Vp-p sin wave signal to pin 23, Measure frequency response at pin 30. (Note) Get the frequency when amplitude is -3dB against amplitude at 100kHz. (Note B19) TRAP fg (1) (1) Pin7 : Input Sand Castle Pulse. (2) Apply 2.0V to pin8. (3) Apply 4.5V to pin 28. (4) Pin 24 : OPEN. (5) Apply 9.0V to pin 25. (6) Input 0.8Vp-p sin wave signal to pin 23, Measure frequency response at pin 29. (Note) Get the frequency at the TRAP. (Note B20) TRAP fo (2) (1) Pin7 : Input Sand Castle Pulse. (2) Apply 4.5V to pin 1. (3) Apply 2.0V to pin 4. (4) Pin 24 : OPEN. (5) Apply 9.0V to pin 25. (6) Input 0.8Vp-p sin wave signal to pin 22, Measure frequency response at pin 30. (Note) Get the frequency at the TRAP. 9997-11-05 13/22
(Note B21) TRAP Attenuation Value (1). (1) Pin7 : Input Sand Castle Pulse. (2) Apply 2.0V to pin 8. (3) Apply 4.5V to pin 28. (4) Pin 24 : OPEN. (5) Apply 9.0V to pin 25. (6) Input 0.8Vp-p sin wave signal to pin 23, Measure frequency response at pin 29. (Note) Get the level at 3.54MHz against level at 100kHz. (Note B22) TRAP Attenuation (2) (1) Pin7 : Input Sand Castle Pulse. (2) Apply 4.5V to pin 1. (3) Apply 2.0V to pin 4. (4) Pin 24 : OPEN. (5) Apply 9.0V to pin 25. (6) Input 0.8Vp-p sin wave signal to pin 22, Measure frequency response at pin 30. (Note) Get the level at 3.54MHz against level at 100kHz. (Note B23) Pin 22 Impedance. (1) Apply 4.6V to pin 22. (2) Measure the current that flows into pin 22. (l22a) (3) Apply 5.0V to pin 22. (4) Measure the current that flows into pin 22. (l22b) (5) Calculate impedance. 400/(I22b -!22a) (Note B24) Pin 23 Impedance. (1) Apply 4.6V to pin 23. (2) Measure the current that flows into pin 23. (23a) (3) Apply 5.0V to pin 23. (4) Measure the current that flows into pin 23. (I23b) (5) Calculate impedance. 400/(I23b -123a) 9997-11-05 14/22
(Note B25) SW Threshold Voltage. (1) Pin7 : Pulse OFF. (2) Pin 25 : OPEN. (3) Input 100kHz, 0.8Vp-p, sine wave to pin 26 with, 5.2V bias. (4) Connect external voltage supply to pin 24 observe pin 29 with changing supply voltage, Measure the voltage of when output level is changed supply voltage to pin 24. (Note B26) SW2 Threshold Voltage. (1) Pin7 : Pulse OFF. (2) Pin 24 : OPEN. (3) Input 100kHz, 0.8Vp-p, sine wave to pin 23. (4) Apply 4.5V to pin 28. (5) Apply 4.5V to pin 8. (6) Connect external voltage supply to pin 25 observe pin 29 with changing supply voltage, Measure the voltage of when the signal appear at pin 29. (Note B27) VCO Free-run Frequency. (1) Pin7 : Pulse OFF. (2) Measure the frequency of output signal at pin 10. (Note B28) VCO Max. Frequency. (1) Pin7 : Pulse OFF. (2) Apply 3.0V to pin9. (3) Measure the frequency of output signal at pin 10. (Note B29) VCO Min. Frequency. (1) Pin7 : Pulse OFF. (2) Apply 3.0V to pin9. (3) Measure the frequency of output signal at pin 10. (Note B30) Frequency Control Sensitivity. (1) Pin7 : Pulse OFF. (2) Apply 4.2V to pin 9. (f19a) (3) Measure the frequency of output signal at pin 10. (4) Apply 4.8V to pin 9. (f19b) (5) Measure the frequency of output signal at pin 10. (6) Calculate frequency control sensitivity. (f19b - f19a) /0.6 9997-11-05 15/22
(Note B31) APC Pull-in Range (+) (1) Input 0.3V, 15.734kHz, 10s pulse to pin 7. (2) Observe pin 9 contain AFC is locked. (3) Increase input frequency due to unlock APC. Then decrease input frequency measure the input frequency when APC is locked again. (f7a) (4) Calculate pull-in frequency. (f7q - 15.734kHz) (Note B32) APC Pull-in Range (-) (1) Input 0.3V, 15.734kHz, 10s pulse to pin 7. (2) Observe pin 9 contain AFC is locked. (3) Increase input frequency due to unlock APC. Then decrease input frequency measure the input frequency when APC is locked again. (f7b) (4) Calculate pull-in frequency. (f7p - 15.734kHz) (Note B33) VCO Output Level. (1) Input Sand Castle Pulse to pin 7. (2) Measure amplitude of output signal at pin 10. (Note B34) AGC Max. Gain. (1) Input Sand Castle Pulse to pin 7. (2) Pin 24 : OPEN. (3) Apply 9.0V to pin 25. (4) Apply 2.0V to pin 8. (5) Input 100kHz, sine wave signal, which is synchronized with fy, to pin 23. (6) Observe pin 29, Measure input signal amplitude. At pin 23 when output signal amplitude is 0.8Vp-p at pin 29. (V23a) (7) Calculate gain. G=20€0g (0.8/V23a) (Note B35) AGC Min. Gain. (1) Input Sand Castle Pulse to pin 7. (2) Pin 24 : OPEN. (3) Apply 9.0V to pin 25. (4) Apply 7.0V to pin8. (5) Input 100kHz, sine wave signal, which is synchronized with fy, to pin 23. (6) Observe pin 29, Measure input signal amplitude. At pin 23 when output signal amplitude is 0.8Vp-p at pin 29. (V23b) (7) Calculate gain. G = 20€0g (0.8/V23pb) 9997-11-05 16/22
(Note B36) AGC Knee Level (+) (1) Input Sand Castle Pulse to pin 7. (2) Apply 9.0V to pin 24. (3) Apply 9.0V to pin 25. (4) Input 100kHz, sine wave signal, which is synchronized with fy, to pin 26. (5) Connect pin 3 to pin 23 via amplifier. (6) Set the input level at pin 23 is 0.8Vp-p by adjusting gain of amplifier. (7) Measure output signal at pin 29. (V29) (8) Measure input signal amplitude at pin 23 when the output signal amplitude at pin 29 is 0.5dB bigger than V29 with adjusting gain of amplifier. (V23a) (9) Calculate knee level. 200g (V23q/0.8) (Note B37) AGC Knee Level (-) (1) Input Sand Castle Pulse to pin 7. (2) Apply 9.0V to pin 24. (3) Apply 9.0V to pin 25. (4) Input 100kHz, sine wave signal, which is synchronized with fy, to pin 26. (5) Connect pin 3 to pin 23 via amplifier. (6) Set the input level at pin 23 is 0.8Vp.p by adjusting gain of amplifier. (7) Measure output signal at pin 29. (V29) (8) Measure input signal amplitude at pin 23 when the output signal amplitude at pin 29 is -0.5dB bigger than V29 with adjusting gain of amplifier. (V23b) (9) Calculate knee level. 20f0g (V23p /0.8) (Note B38) Clamp Det (+) (1) Pin7 : GP Pulse ON. (2) Apply 2.0V to pin8. (3) Apply 9.0V to pin 25. (4) Pin 24 : OPEN. (5) Apply 4.5V to pin 23. (6) Measure voltage at pin 29. (V29) (7) Apply 5.0V to pin 23. (8) Measure voltage at pin 29. (V29q) (9) Calculate voltage change. (V29a - V29) 9997-11-05 17/22
(Note B39) Clamp Det (-) (1) Pin7 : GP Pulse ON. (2) Apply 2.0V to pin8. (3) Apply 9.0V to pin 25. (4) Pin 24 : OPEN. (5) Apply 4.5V to pin 23. (6) Measure voltage at pin 29. (V29) (7) Apply 4.0V to pin 23. (8) Measure voltage at pin 29. (V29b) (9) Calculate voltage change. (V29b - V29) (Note B40) HP Pulse Threshold Voltage. (1) Input Sand Castle Pulse to pin 7. (2) Decrease H.BLK level until disappear normal pulse at pin 3. Then, Increase H.BLK level. Measure H.BLK level when normal pulse appear at pin 3. (Note B41) GP Pulse Threshold Voltage. (1) Input Sand Castle Pulse to pin 7. (2) Decrease Gate-Pulse level until voltage at pin 26 isn’t clamped to 5.2V, Then increase Gate-Pulse level. Measure Gate-Pulse level when voltage at pin 26 is clamped to 5.2V. (Note C1) Power Supply Current. (1) Input f =225fy, Lev=0.3Vp-p signal to pin 11. (2) Pin 13 and 15 are no input. ($4, $2 =b) (3) After 20s from (1), Measure the current from power supply. (Note C2) Pin 11~20 Terminal Voltage. (1) Input f =225fy, Lev=0.3Vp-p signal to pin 11. (2) Pin 13 and 15 are no input. ($1, $2 =b) (3) Measure the voltage at each pin. (Note C3) Input-Output Gain. (1) Input f =225fy, Lev=0.3Vp-p signal to pin 11. (2) Apply external bias voltage to pin 13 and 15 so that the voltage at pin 13 and 15 are 0.2V higher than voltage when no input. (3) Input f= 15kHz, Lev=0.3Vp-p signal to pin 13 and 15. ($4, $2=c) (VN) (4) Measure output signal amplitude at pin 16 and 19. (Vout) (5) Calculate gain. Gq (G2) =20€0g (VouT/ VIN) [dB] 9997-11-05 18/22
(Note C4) Frequency Response (1) Input f=225fy, Lev=0.3Vp-p signal to pin 11. (2) Apply external bias voltage to pin 13 and 15 so that the voltage at pin 13 and 15 are 0.2V higher than voltage when no input. (3) Input f=1.17MHz, Lev =0.3Vp.p signal to pin 13 and 15. (Sy, S2=c) (Vin) (4) Measure output signal amplitude at pin 16 and 19. (VoyT) (5) Calculate gain. G=20€0g (VouT/ Vin) [dB] Calculate frequency response. feht (fch2) =G1 (G2) -G [48] (Note C5) Output Impedance. (1) Input f =225fy, Lev=0.3Vp-p signal to pin 11. (2) Apply external bias voltage to pin 13 and 15 so that the voltage at pin 13 and 15 are 0.2V higher than voltage when no input. (3) Input f= 15kHz, Lev =0.3Vp-p signal to pin 13 and 15. (S4, $2=0) (4) Measure output level (15KHz component) at pin 16 and 19. (Vouta) (5) Measure output level (15KHz component) with load at pin 16 and 19. (Voutb) (6) Calculate output impedance. Vouta-Voutb (Note C6) Linearity (1) Input f =225fy, Lev=0.3Vp-p signal to pin 11. (2) Input 4 step signal to pin 13 and 15. (S1, $2=0) <Input Signal> c (*) Duty =50% (*) Input level A 8 R=0.25Vp.p R A,B, C=0.2Vp.p 1997-11-05 19/22
(3) Measure output signal (R, A, B, C) amplitude at pin 16 and 19. (4) Calculate linearity R ig Vrpl1 Wrpi2) = 100 [%] Vid (VHL2) = = x 100 [%] B Vit (VLL2) = nm x 100 [%] (Note C7) Clock Leak (1) Input f =225fy, Lev=0.3Vp-p signal to pin 11. (2) Pin 13 and 15 are no input. (Sy, $2 =b) (3) Measure clock level (225f,y component) with spectrum analyzer at pin 11. (Vin [dB]) (4) Measure clock level (225f,y component) with spectrum analyzer at pin 16 and 19. (Vout [dB]) (6) Measure clock leak. Vout=Vin 1 CLOCK LEAK (Lejk1/Lelk2)=10 7° 300 x 5 [mVrmsl 1997-11-05 20/22
a 1P30 1P29 TP28 P27 TP26 P23 TP24 o Of Oo oO o oO TA8772AN__ BASE BAND 1H DELAY SYSTEM i VOODOO DO DA ACYDNYDYVYDYDY & 5 Sais]: S 2 O.1ue el ha PS 1 Ss a O Oo oo ooo o QO 1P1 P2 1P3 TPa 1P61P7 TP8 TPS TP1O o) ) ov sv ATTENTION FOR HANDLING The input and output terminal is high impedance when this IC is not mounted. So, It is necessary that you must protect it from external electoronical stress. 1997-11-05 21/22
SDIP30-P-400-1.78 Unit : mm fo 30 16 * (oe ee ee ee ee ee ee ° | : ) 3 ° = 38 | ¥F “TILIttItititititit iti tititit 8 1 15 27.9MAX 27.440.2 yo gg HOMME UGE UU es os z Q mE —ie bd a Weight : 1.99g (Typ.) 1997-11-05 22/22