TA8667P TOSHIBA | Alldatasheet
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TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC TA8667P, TA8667F The TA8667P, TA8667F is generation of high-frequency TA8667P clock synchronized with horizontal sync signal. _ (The TA8667P/F is H AFC IC for TC9086F (3DYCS), oo S TC9097F (WAC).) _ 7. eons c tara ayy yt UNTHY i i l FEATURES 1 i vo @ Generate of Typ. 28MHz (1820fH) clock. DIP18-P-300-2.54D © Generate of vertical sync signal. TAS667F @ Generate of composite sync signal. SSOP24-P-300-1.00B Weight DIP18-P-300-2.54D__: 1.47g (Typ.) BLOCK DIAGRAM SSOP24-P-300-1.00B : 0.32g (Typ.) TA8667P tour V. Sepa OUT V. IN Vor 6) @ ® © || P “ Wave Wave GND1 P {78 cno2 © @ @ OD OD WO V. Mask IN H. ref IN P.D. OUT Bias filter VCO TANK 961001EBA2 @ TOSHIBA is continually working to improve the quality and the reliability of its products, Nevertheless, semiconductor devices in general can malfunction or fall due to their inherent electrical sensitivity and vulnerability to physical stress. itis the responsibilty of the buyer, when utliing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified ‘operating rangot as tot forth in the most recent products pecificatione. Alzo, pleaze keep in mind the precautions and conditions tet forth in the TOSHIBA Semiconductor Reliability Handbook. & The products described in this document ae subject to foreign exchange and foreign trade control laws The [Information contained herein is presented only as a guide for ‘the applications, of our products. No responsiblity is assumed by, TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. © The information contained herein is subject to change without notice 1997-11-05 1/13
TERMINAL CONNECTION DIAGRAM V. Sepa IN C1} [18) coz V. Sepa IN 1] [24) coz HV. Sepa in GQ] ‘eo HV. Sepa In GQ] 8) v. Sepa out (4) 5 (3) vec2 Qq . ey vING@} wo fDvect cSoTG) nN RDvcee vorg@), © [13 2gsN OUT V.SepaouT@} © (19) vect H. ret in GJ < [7D cnor vinG@] 2 f®@2¢sw our V. Mask in @} [5 titer Tor@ ¢ [Deno P.o. out G) [10) Bias @) a ®) H. ref IN @Q] ['5) V. Mask IN GJ [14 filter p.0. our @ [i bias TERMINAL FUNCTION 1TA8667P|TA8667F TYP. DC finkor[nnar| PM NAME |Otiage| 1/0 cRCU FUNCTION Vect @ V. Sepa IN : Inputs vertical sync signal separated from 1 1 V. Sepa IN video signal. (6.0V) @ H.V. Sepa IN : Inputs 2 2 H.V. Sepa IN horizontal and vertical sync z signals separated from [ video signal. GNo1 Vect © Outputs horizontal and CS. OUT vertical sync signals after S. ¢ wave shaping. 5 <p GnDt Veet © Outputs vertical sync V. Sepa OUT signal. Horizontal sync signal remains in V. Sepa OUT. GNo1 1997-11-05 2/13
TT A8667P] TA8667F TYP. DC St vec! F @ Inputs the signal outputted 7 V. IN from V. Sepa OUT after . O S000 horizontal sync signal was removed. GND1 Veet our © Outputs wave-shaped . vertical sync signal. = Oo: 5 * GND1 @ Phase Comp Input. The S. Vect reference input is the 2 15.7kHz signal derived through dividing the 2¢SN 7 10 H. ref IN O o OUT signal by N . (1820~2426) with an “hy GNDI external frequency divider (duty : 50%). Vec1 | @ Driving the V. Mask IN GS cc . : Fe signal to high turns off the (L: OV) - phase-comparison 11 V. Mask IN O operation. Inputs the signal (H: 5V) c which masks serrated and 2S nor equalizing pulses of video signal. Veet 12 P.D. OUT GND1 © Connect an external filter. Veet 10 13 6V _ O Ly) Gno1 1997-11-05 3/13
1TA8667P| TA8667F TYP. DC Vect 11 14 ‘| filter 6V td © Connects an external filter. not 12 17 GND1 18 24 GND2 @ Power-supply voltage and 14 19 |Vcc1 GND. 15 20 |Vcc2 Vee2 © Outputs the stable sin 18 |2¢SN OUT wave of N times the fH § frequency. GNo2 Vec2 16 2 5.2V e sets the oscillating ina th vco TANC requency by ai justing e value of external variable 17 23 5.2V . coil. Gno2 15 NC 1997-11-05 4/13
MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATINGS UNIT Power Supply Voltage input Signal Voltage [ein max | _6 | Vpp | Power TA8667P 1320 mw Consumption TA8667F | 830—s| Ta-Pp TA8667P TA8667F 1500, 1500) = = = 1320] & é é Saas) 2 830 . = S i & 500 8 530 : 25 70 150, 25 70 150 OPERATING TEMPERATURE (°C) OPERATING TEMPERATURE (°C) RECOMMENDED OPERATING CONDITION 8s iz os} 1997-11-05 5/13
ELECTRICAL CHARACTERISTICS (Vcc =9.0V, Ta = 25°C) All the pin numbers in the below description are those of the TA8667P. TEST TEST CONDITION CHARACTERISTIC SYMBOL (SEE “TEST CIRCUIT”) | wn. | ave. [ max. | UNIT Operating Power Supply ve Vv Voltage cc Operating Power Supply Current lec 15 27 mA 1) Measure Voltages V3 and V6 of Pin3 and Pin 6, respectively. 2) Connect variable voltage VOH (1) source to Pin2 and Pin 5. 2.5 5.5 3) Change variable voltage source and measure voltages High Level V3 and V6 when high. 1) Measure Voltage V4 of Pin 4. 2) Connect variable voltage source to Pin 1. Vou (2) 3) Change variable voltage 70 source and measure voltage Output V4 when high. Voltage 1) Measure Voltages V3 and V6 v of Pin 3 and Pin 6, respectively. 2) Connect variable voltage VoL (1) source to Pin2 and Pin 5. 0.5 3) Change variable voltage source and measure voltages Low Level v3 and V6 when low. 1) Measure Voltage V4 of Pin 4. 2) Connect variable voltage source to Pin 1 VoL (2) 3) Change variable voltage 0.3 05 source and measure voltage v4 when low. inpat (igh tewvel [Vg [sf | - Connect an ammeter to Pin7 Current (Connect an ammeter to Pin7 few tet Iu |refetimereasv | | of = | oa 1997-11-05 6/13
CHARACTERISTIC symeot| TEST] (SEE “TEST CIRCUIT") | win. | ave. [ max. | UNIT 1) Measure Voltage V4 (V3) of Pin 4 (Pin 3). 2) Connect variable voltage source to Pin 1 (Pin 2) through Sync Separator Input 1,2 an ammeter. pA Sensitivity Current *” 13) Change variable voltage source and measure the current outflowed from Pin 1 (Pin 2) on the high to low transition of V4 (V3). 1) SW1 : Off, SW2 : On 28.6 2) Measure the level of TP1 with noe sypets, counter. 1 Oscillating Frequency fo 13 3) Adjust the value of the 320 variable coil until it reaches (Note 15.73kHzxN. 2) Measure the level of TP1 at the V coon fie Reamer | 29] ale 1) Switch on SW1 in the same condition that fo is measured. . 2) Input the sync signal of Output Jitter Te 13 |" 45.73kHz to Pin 2. 3) Measure the output waveform of the frequency divider. (Note 1) VCO TANC : TRF3518D used (Note 2) VCO TANC : TRF3503K used 1997-11-05 7/13
[cece rome] PEPER [oe [rr [oe [or 1) SW1 : Off, SW2 : On Pin 2 : Open. 2) Measure the frequency of TP1. Hori 3) Adjust the value of the jorizontal Frequency , vane Phase Comparison fe variable coil until it reaches Range2 15.73KHZ XN (fg =32.2MHz). 4) SW1: On 5) Connect $.G* to Pin 2. 6) Measure the power supply of TP2. 7) Raise the $.G* frequency +700 starting from around 13.6kHz | ~ and measure the frequency when PLL is locked. 8) Raise the $.G* frequency further and measure it when Horizontal Frequency f PLL is unlocked. Hold Range H 9) Lower the frequency and measure it when PLL is locked again. 10)Lower the frequency further and measure it when PLL is unlocked again (See Figure 1). TS. OUT Delay Time vin? LI Ly tesd 3 — ted EE 350 (See Figure 2) ens LID LD AF 1) Switch on SW1 in the same condition that fo is measured. 2) Adjust the value of the H. ref IN - CS. OUT variable coil until it reaches Steady-State Phase t 7 15.73kHz XN (fp =32.2MHz). +350 Difference afce 3) Input the sync signal of ~ (See Figure 3) 15.73kHz to Pin 2. 4) Measure the signal waveforms of Pin3 and Pin7 simultaneously. * : §.G=Sync Generator 1997-11-05 8/13
TEST CIRCUIT (Pin assignment for TA8667P) ~o OP! alt TS ie ict ° Sit [= Fa Variable coil SF TS (| 2sc18is Orrz Mec yy were * G)_ G)_ G)_ GG) GD) GD GD GD) TA8667P Oo Oo Oo OG Oo Oo ODO O fe) fo) fe) fe) fe) fe) fe) Variable coil (VCO TANK) : Select an inductance suited for the oscillating frequency. PRECAUTIONS V. Mask IN (See Figure 4, "An example of V. Mask IN timing”) Driving the V. Mask IN signal to high stops phase-comparison operation. Adjust the signal so that equalizing pulse of video signal and vertical sync signal are masked. Masking some parts of horizontal sync signal and video signal do not cause a problem. However, the rise and fall of V. Mask IN must not occur while horizontal sync signal and equalizing pulse are low - the time indicated with " |” in Figure 4, for example. Figure 4 “An example of V. Mask IN timing” Equalizing pulse | Vertical sync signal Equalizing pulse a a 1 4 ! !
4 Equalizing pulse, Vertical sync signal Equalizing pulse
| | TTL rd Ue 5H Masking time | — _ ----- Vin V. Mask IN Vin 1997-11-05 10/13
© Example of VCO TANK Specification for 32MHz clock (TRF3503K) When f=7.96MHz : L=2.35H (Varied within more than + 15%) Q=47 © Example of VCO TANK Specification for 28MHz clock (TRF3518D) When f=7.96MHz : L=3.5H (Varied within more than +15%) Q=42 SAMPLE APPLICATION 1 (Pin Assignment for TA8667P) ‘An example of 28.6MHz clock generation. 51k O47 pF TRF3518D used. ce ani Ss
3 S| 28
Cs_ouT ae VOUT @)__v. Sepa ouT(4)__°G) V. IN (6) 0.07 uF Lie — [a he H.V. Sepa IN 2¥8N our ta 22H shaping 28.6MHz 3] A — * ° 12) GND1 [9 cnoz PD. OU’ filter v. Mask IN) H. ref IN) PePH Om—C) & tly | wl] t--Z___t eb VCO TANK Pa 7] (TRF3518D) 15.7kHz 7 28.6MHz The above illustration shows an example for application and may require modification in constant and circuit for practical design. 1997-11-05 11/13
DIP18-P-300-2.54D Unit : mm 18 10 o es | J 5 » $ 38 a 25.1MAX 24.640.2 fe) og UT hd FS bid Weight : 1.47g (Typ.) 9997-11-05 12
SSOP24-P-300-1.00B Unit : mm HRAARARRAR RRA ey N ise] = ° 5 Qe L | : | : a a 3 1 i 12 1.0TYP 0.440.1 e020) 13.5MAX 13.0+0.2 N x we ry oar lo} = : 70.15] Ps - o o 0.45+0.2 Weight : 0.32g (Typ.) — —. —— TToaTOSwTITNTOT TTI TST