TA8552AFN

TA8552AFN_02 TOSHIBA | Alldatasheet

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/Gb7/G20The TA8552AFN incorporates edge detector, data synchronizer, and latch for data separator. Also the TA8552AFN is available to correspond to ×1, ×2 and ×3 of data transfer rates by adjusting external devices. /Gb7/G20The data synchronizer is avalable to correspond to ±7% variation of data transfer rate. /Gb7/G20By employing full differential signal processing in PLL loop, the TA8552AFN eliminates the influence of external noise. Fast & stable locking is realized by switching between the frequency detective mode and the phase detective mode. /Gb7/G20Operating power supply voltage range: 4.5V to 5.5V /Gb7/G20Small package; SSOP30−P−300−0.65 Handle with care to prevent devices from deterioration by static electricity. Pin Connectoion To p view NC RVCO1 AGND2 CVCO1 RVCO2 CVCO2 AVCC2 TMON1 TMON2 XTMON2 V TTLO MODESEL TSTCPMP RD XRD COB COA AGND1 RCP2 RCP1 AVCC1 DETSEL TSTCLK DVCC3 PBDT PBCK DGND3 TSTSEL2 REFCLK TSTSEL1 Weight: 0.17g (typ.)

Charge − pump Detecter selector COB VCO 1 / 2 counter CVCO2 CVCO1 RVCO2 RVCO1TSTSEL1 TSTSEL2 TSTCLKTSTCLKPBDTPBCK QD Selecter Phase detecter Edge detecter Frequency detecter ECL / TTL REFCLK RD XRD Delay (2)

Pin No. Pin Name Function In / Out 1 NC NC terminal. (open at normal use) ― 2 RVCO1 VCO adjusting terminal. Connect an external resistor (RVCO1) between VCC. ― 3 AGND2 Analog ground for VCO. ― 4 CVCO1 VCO adjusting terminal. Connect a capacitor (CVCO) between this pin and pin6. ― 5 RVCO2 VCO adjusting terminal. Connect an external resistor (RVCO2) between VCC. ― 6 CVCO2 VCO adjusting terminal. Connect a capacitor (CVCO) between this pin and pin4. ― 7 AVCC2 Analog power supply voltage for VCO. ―

8 TMON1 NC terminal (open at normal use) ―

9 TMON2 NC terminal (open at normal use) ―

10 XTMON2 NC terminal (open at normal use) ―

11 V_TTLO Input terminal for TTL voh (high voltage level of pin20, and

pin21 output) limitting. ― 12 MODESEL Input terminal for switching the normal mode and the serching mode. (H: Normal mode, L: Serching mode) TTL/G2din 13 TSTCPMP NC terminal. (open at normal use.) ―

14 RD Input terminal of data (normal phase) ECL/G2din or

15 XRD

Input terminal of data (reverse phase). (this terminal is active when TSTSEL1 = L and TSTSEL2 = H. Otherelse, short with V CC.) (ECL/G2din) 16 TSTSEL1 Input terminal for test mode selecting. (refer the chapter of "test mode") ― 17 REFCLK Reference clock input of frequency synchronizer. TTL /G2din 18 TSTSEL2 Input terminal for test mode selecting. (refer the chapter of "test mode") ― 19 DGND3 Digital ground for TTL output. ― 20 PBCK Output terminal of data latch clock. TTL /G2dout 21 PBDT Output terminal of data latch. TTL /G2dout 22 DVCC3 Digital power supply voltage for TTL output. ― 23 TSTCLK Input terminal of ×1 / 2 vco test clock. (short with VCC at mormal use.) ―

24 DETSEL

Input terminal for switching the frequency detective mode and the phase detective mode. (L : The frequency detective mode H : The phase detective mode.) TTL/G2din 25 AVCC1 Analog power supply voltage. ―

Pin No. Pin Name Function In / Out 26 RCP1 Adjusting terminal of charge pump at normal mode. Connect an external resistor (Rcp1) between GND. ― 27 RCP2 Adjusting terminal of charge pump at normal mode. Connect an external resistor (Rcp2) between GND. ―

28 AGND1 Analog ground ―

29 COA Connecting terminal of loop filter. Connect an external loop filter between this pin and 30pin. ― 30 COB Connecting terminal of loop filter. Connect an external loop filter between this pin and 29pin. ― Absolute Maximum Rating (Ta = 27°C) Parameter Symbol Rating Unit Supply voltage AVCC 7 V Input voltage V IN /G2d0.3~VCC+0.3 V Output voltage V OUT /G2d0.3~VCC+0.3 V Storage temperature T stg −55~150 °C Recommended Operating Condition Parameter Symbol Condition Min. Typ. Max. Unit Supply voltage AVCC ― 4.5 5 5.5 V Operation temperature T opr ― /G2d5 ― 75 °C Power Supply (unless otherwise specifide, Ta = 27°C, VCC = 5.0V) Parameter Symbol Condition Min. Typ. Max. Unit Supply current IPLCC TSTSEL1 = H, TSTSEL2 = L DETSEL = L, MODSEL = H 65 mA

Electrical Characteristic (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter Symbol Test Circuit Test Condition Min. Typ. Max. Unit High level input voltage (1) V IH ― TTL input pins 2.0 ― ― V Low level input voltage (1) V IL ― TTL input pins ― ― 0.4 V High level input current (1) I IH ― TTL input pins ― ― 20 µA Low level input current (1) I IL ― TTL input pins ― ― /G2d360 µA High level input voltage (2) VIHE ― ECL input pins VCC /G2d1.0 ― ― V Low level input voltage (2) VILE ― ECL input pins ― ― VCC /G20/G2d1.5 V High level input current (2) IIHE ― ECL input pins ― ― 2.0 mA Low level input current (2) IILE ― ECL input pins ― ― 1.6 mA High level output voltage (1) V OH ― TTL output pins IOH = 400µA VTTLO /G2d0.2 VTTLO +0.2 V Low level output voltage (1) V OL ― TTL output pins IOL = 4mA ― ― 1.0 V Output rise time (1) TOR ― TTL output pins 1.5V to 3.5V CL≤30pF *1 ― ― 5 ns Output fall time (1) TOF ― TTL output pins 3.5V to 1.5V CL≤30pF *1 ― ― 5 ns Input voltage range to VTTLO terminal VTTLO ― 2.7 ― 3.3 V *1; Design guaranteed value. Charge Pump (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter Symbol Test Circuit Condition Min. Typ. Max. Unit ― At normal mode *1 30 ― ― Range of output current setting I CP ― At serching mode *2 ― ― 800 µA ― At normal mode /G2d6 ― +6 Accuracy of output current setting Iacu ― At serching mode /G2d8 ― +8 Leak current I reak Between COA pin and COB pin, at high impedance /G2d3.5 +3.5 µA *1; Output current is set by an external resistor (R cp1), as following; 2×1.3 / R cp1 = (output current at normal mode). *2; Output current is set by external resisters (Rcp1, Rcp2), as following; 2×1.3 / R cp1+8×1.3 / Rcp2 = (output current at search mode). (Note) The above values are all at open loop.

VCO (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter Symbol Test Circuit Condition Min. Typ. Max. Unit Input voltage of VCO (V (COB/G20/G2dCOA)) VVCO ― RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF *1 fVCO = 28.224MHz 0.25 0.45 V Upper limitation of VCO frequency fmax ― RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF *1 V (COB/G20/G2dCOA) = 0.6V

29.5 MHz

frequency fmin ― RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF *1 V (COB/G20/G2dCOA) =/G20/G2d0.6V

23.5 MHz

Control gain (F / V) GVCO ― RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF *1 Voltage (COB/G20/G2dCOA) Excursion 0.3V to /G2d0.3V 6 7.7 MHz / V VCO jitter t jit ― PBCK pin at ×3 transfer rate *2 300 ps *1; C VCO inclides the package capacitance. *2; Design guaranteed value. (Note) The above values are all at open loop, measured at the PBCK pin Closed Loop (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter Symbol Test Circuit Condition Min. Typ. Max. Unit VCO jitter in closed loop t jit2N ― In search mode lock to REFCLK 0.5 ns VCO jitter in closed loop t jit2S ― In normal mode lock to RD 0.4 ns Values of external parts are (R VCO1 = 3.75 kΩ, RVCO2 = 1.21 kΩ, CVCO = 39pF (including storage capacitor), RCP1 = 8.25k, RCP2 = 30.1k).

The connection of input voltage and output frequency of VCO (measured at PBCK after the 1 / 2 frequency counter) is written as following; /G28/G29ofsIOIVvcoC8 1 /G2b/Gd7/G44/Gd7/Gd7 ( V in>2Vop) f vco = )ofsI 2 OI Vin op4V OI( VvcoC8 1 /G2b/G2b/Gd7/G44/Gd7/Gd7 (2Vop>Vin>/G20/G2d2Vop) ofsIVvcoC8 1 /Gd7/G44/Gd7/Gd7 ( V in</G20/G2d2Vop) Where; C vco is an external capacitor between 4pin and 6pin, ∆V = 0.35V , Vop = 0.275V , Vin is the input voltage of VCO (differential), I O = 3×1.3 / Rvco1, and lofs = 2×1.3 / Rvco2･ So, the gain of VCO is defined as following (at PBCK); op4V OI VvcoC /Gd7/G44/Gd7/Gd78 fVCO I0 + IOFS

8 CVCO ∆V

+ IOFS − 2 Vop 0 2 Vop VIN

And, upper limitation f upper, and lower limitation of VCO frequency f lower is defined as follows; f upper = (IO+Iofs) / 8Cvco ∆V f lower =Iofs / 8Cvco ∆V I 0 can be determined by selecting R vco1, and I ofs can by Rvco2. So, you can independently determine the gain of VCO, upper limitation and lower limitation of VCO frequency by selecting C vco, Rvco1, and Rvco2･ 【Example】When, C vco = 22.1pF, Rvco1 = 2.6kΩ, Rvco2 = 2.6 kΩ, Gain of VCO ; 0.27540.351022.18 3)310(2.6 / 1.3 /Gb4/Gb4/Gb4/G2d/Gb4/Gb4 /Gb4/Gb4 12 = 22MHz / V Upper limitation of VCO frequency ; 0.3512-1022.18 /Gb4/Gb4/Gb4 /Gb4/Gb4/G2b/Gb4/Gb4 = 40.4MHz Lower limitation of VCO frequency ; 0.3512-1022.18 2)310(2.6 / 1.3 /Gb4/Gb4/Gb4 /Gb4/Gb4 = 16.2MHz f − 0.55V 0 + 0.55V V 16.2MHz 28.224MHz 40.4MHz Gain; 22MHz / V

Function Description: The angular frequency ( ωn) and dumping facter (ζ) are adjusted by external devices. The setting procedure is shown as following. The setting conditions to lock PLL inside a constant time; /Gb7/G20 Data transfer rate: 28.224Mbps (f M = 28.244MHz) /Gb7/G20The capturing signal of PLL: The rectangle wave of 14.112MHz (data pattern is 101010...), The term of this data is continuous 180 bits. /Gb7/G20The capturing time of PLL: 1 / (14.114×106) ×180 = 12.75×10/G2d6s 【The transfer function of PLL】 The transfer function (F (S)), the angular frequency (ω n), and the dumping facter (ζ) of the above composition are defined as following (However CL2 is ignored as CL2≪CL1): 21/G2f/G3d/G77 ) L1C K(n nL1CLR /G77/G3d/G7a 【Calculation of ζ】 The dumping factor (ζ) is set to 0.7 as the most stable response characteristic. Besides ωn t is assumed to set as 6. Phase comparater Loop filter VCO 1 / 2 counter K0 / s Z (s) K /G66 θi θo CL1 CL2 RL Z (s)

【Calculation of ωn】 The capturing time of PLL is expected as above 11.5µs. Therefore ( ωn) is deternimated as the following: ωn = 6 / (11.5×10/G2d6) = 552krad / s 【Calculation of K 0 (VCO control gain)】 K 0 is determined as the following; K 0 = 40MHz / V = 251.3Mrad / V 【Calculation of K/G66 (phase detector gain)】 K /G66 is estimated as the following (the current of charge pump is set as ±50µA.) K /G66 = 1 ･ /G702 The current of charge pump (Ichp) is set by an external resister (R cp1), connected with Rcp1 (26pin). When "H"level voltage inputs to MODESEL (12pin), Ichp is set as the following: I chp = 2×1.3 / RCP1→RCP1 = 2×1.3 / Ichp = 2×1.3 / 50×10/G2d6 = 52×103Ω Therefore, when R CP1 is 52kΩ, Ichp is set as ±50µA 【Calculation of external devices of loop/G2dfilter】 F6-1018002)310(522 2 610251.3-6103.98 0KK L1C /Gb4/G3d /Gb4/Gb4 /Gb4/Gb4/Gb4/G3d/G77 /Gb4/G66/G3d /G57/Gb4/G3d /Gb4/Gb4/Gb4 /Gb4/G3d/G77 /G7a/G3d 3101.5 31052212-101800 0.72 n L1C LR C L2 = CL1 / 10 = 180pF

Modesel Switching Function The TA8552AFN has a function to correspond with the high /G2dspeed serching mode of DAT streamer. In the searching mode, the data transfer rate will shift with small percentage error. The TA8552AFN is available to solve this problem by extending the lock /G2din/G2drange (∆ω L). In the serching mode the current of charge pump will be increased to raise the phase detecter gain, then the lock /G2din/G2drange (∆ωL) will extend. This function is selected by modesel (12pin). (H: Normal mode / L: Searching mode) 【Calculation of the charge pump's current in the searching mode】 The charge pump's current in the searching mode is estimated as the following (the shift rateX of data, transfer is assumed as X = 7% in this example); (A)6-10830 3.148610251.33101.5 3.1420.0761028.2248 0KR 2XMf chp /Gb4/G3d/Gb4/Gb4 /Gb4/Gb4/Gb4 /Gb4/Gb4/Gb4/Gb4/G3d/G70/Gb4/Gb4 /G70/Gb4/Gb4/G3d/G49 When "L" level voltage inputs to modesel (12pin), the charge pump's current (Ichp) increases. In the normal mode, the charge pump's current (I cp1) is set by an external resister (Rcp1). And in the searching mode, another current (I cp2), is set by an external resisiter (Rcp2), adds to Icp1. This (R cp2) is the resister to be connected with RCP2 (27pin) The additional current (I cp2) is determined by the following: I cp2 = 8×1.3 / Rcp2 Therefore, R cp2 is estimated as the following: /G57/Gb4/G3d /Gb4/Gb4 /Gb4/G3d 31013.3 6-1050-6-10830 1.38 cp2R Modesel function is summarized by the followings Mode Normal Mode High/G2dspeed Searghing Mode Modesel (12pin) H L Charge pump current Ichp I cp1 I cp1+Icp2 Setting definition 2×1.3 / R cp1 2×1.3 / R cp1+8×1.3 / Rcp2

4.704 MHz, 360 pulse for x1−Speed

9.408 MHz, 360 pulse for x2−Speed

14.112 MHz, 360 pulse for x3−Speed

Synk−byte D1 D2 D3 D4 D5 D6 D7 D8 D9 RD Locked by PLL Out of edge det. PBCK Out of latch

(Note) Test Monitor Output Terminal Tstsel 1 2 Datainput Function L L TTL input from 14pin (RD) ― H L TTL input from 14pin (RD) PBCK (20pin) & PBDT (21pin) becomes disable L H ECL input from 14pin (RD) and 15pin (XRD) ― H H TTL input from 14pin (RD) The internal PLL becomes disable, and the external clock from tstclk (23pin) becomes enable as input data signal. (Note) ● We commend the use of this IC under the comdition of ECL input from 14pin (RD) and 15pin (XRD) when (TSTSEL1, TSTSEL2) = (L, H)

• It is possible of the use of TTL input from 14pin (RD) when (TSTSEL1, TSTSEL2) = (L, L)

When the data transfer rate is 28.224Mbps, the application diagram is shown below. 1.5kΩ 1500pF RCP2 13.3kΩCOB COA 1500pF RCP1 52kΩ GNDAGND1 RCP2 RCP1 VCCAVCC1 DETSEL TSTCLK VCCDVCC3 PBDT PBCK GNDDGND3 TSTSEL2 TSTSEL1 REFCLK H / phase comparate mode L / frequency comparate mode OUT OUT TTL in 28.224MHz Test set 1 Test set 2 XRD RD TSTCPMP MODESEL 3.3V V TTL0 XMON2 TMON2 TMON1 AVCC2V CC CVCO2 RVCO2 CVCO1 AGND2 RUCO1 GND 2.7kΩ VCC 2.7kΩ RVCO2 0.1µF 0.1µF RVCO1 VCC NC1 CL2 CL1 RL 1800pF 180pF H / normal L / search 22.1pF CVCO ECL in Xdata in Data in TTL in VCC Data in or

Weight: 0.17g (typ.)

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