TA310

TPCE636 TEWS | Alldatasheet

Document overview

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Technical content

TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice. All trademarks mentioned are property of their respective owners. Issue 1.0.2 2021-05-20 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com The Embedded I/O Company TPCE636 Reconfigurable FPGA with 16 x 16 bit Analog Input and 16 x 16 bit Analog Output

Application Information

The TPCE636 is a half-length X4 PCIe compatible module providing a user configurable Kintex7 FPGA with 16 ADC input channels and 16 DAC output channels. The TPCE636 ADC input channels are based on the Linear Dual 16-Bit 5Msps Differential LTC2323-16 ADC. The TPCE636 provides 16 ADC channels. Each of the 16 channels has a resolution of 16bit and can work with up to 5Msps. The analog input circuit is designed to allow input voltages up to ±10V on each input-pin (results in ±20V differential voltage range). The TPCE636 DAC output channels are based on the Dual 16bit AD5547 DAC. Each DAC output is designed as a single-ended bipolar ±10V analog output. For customer specific I/O extension or inter-board communication, the TPCE636 provides 64 FPGA I/Os on a back I/O connector and 4 FPGA Multi- Gigabit-Transceiver on a Samtec FireFly© connector. Digital back I/O lines can be configured as 64 single ended LVCMOS25 or as 32 differential LVDS25 interface. All front I/O lines such as the ADC interface and DAC interface are connected to a 98-pin. Samtec ERF8-049 Rugged EdgeRate Connector. The User FPGA is connected to a 1GB, 32 bit wide DDR3 SDRAM. The SDRAM-interface uses an internal Memory Controller of the Kintex-7.

TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice. All trademarks mentioned are property of their respective owners. Issue 1.0.2 2021-05-20 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com The Embedded I/O Company The User FPGA is configured by a serial SPI flash. For full PCIe specification compliance, the XILINX Tandem Configuration Feature can be used for FPGA configuration. XILINX Tandem Methodologies “Tandem PROM” should be the favored Methodology. The SPI flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for read back and real- time debugging of the FPGA design (using Xilinx “ChipScope”). User applications for the TPCE636 with Kintex-7 FPGA can be developed using the design software Vivado Design Suite. A license for the Vivado Design Suite design tool is required. TEWS offers a well-documented FPGA Board Reference Design. It includes constraint file with all necessary pin assignments and basic timing constraints. The FPGA Board Reference Design covers the main functionalities of the TPCE636. The TPCE636 is delivered with the FPGA Board Reference Design. The user FPGA can be programmed via the on-board Board Configuration Controller (BCC). Programming via the JTAG interface using an XILINX USB programmer is also possible. In accordance with the PCI specification and the buffering of PCI header data, the contents of the user FPGA can be changed during operation. TA310 Technical Information o Form Factor: half-length X4 PCIe o Board size: 153 mm x 98 mm o PCI Express x4 Link (Base Specification 2.1) compliant interface conforming to ANSI/VITA 42.3-2006 o TPCE636 FPGA options: o -10R Xilinx XC7K160T-2FBG676I Kintex-7 o -11R Xilinx XC7K325T-2FBG676I Kintex-7 o -12R Xilinx XC7K410T-2FBG676I Kintex-7 o Serial Flash for FPGA Configuration o FPGA clock options: o Local clock generator as source for the FPGA internal PLL o Free programmable Si514 Oscillator o DDR3 SDRAM bank, 256M x 32 Bit (1GB) o Front I/O lines o 16 differential analog inputs o 16 bit resolution o 5Msps o Factory calibration o 16 differential analog outputs o 16 bit resolution o max. ±10V single ended output o Factory calibration o Back I/O lines o 64 single ended or 32 differential back I/O lines on a rear 68pin ERNI SMC connector. o 4 FPGA Multi-Gigabit-Transceiver on a rear Samtec FireFly(c) connector. o Operating temperature -40°C to +85°C o MTBF (MIL-HDBK217F/FN2 GB 20°C): 240000h

TPCE636-10R Kintex-7 FPGA XC7K160T-2 FBG676, 1GBDDR3 16 x Analog In, 16 x Analog Out and 64 direct FPGA Back I/O Lines, 4 MGTs on FireFly connector © TPCE636-11R TPCE636-12R Kintex-7 FPGA XC7K325T-2 FBG676, 1GBDDR3 Kintex-7 FPGA XC7K410T-2 FBG676, 1GBDDR3 16 x Analog In, 16 x Analog Out and 64 direct FPGA Back I/O Lines, 4 MGTs on FireFly connector © 16 x Analog In, 16 x Analog Out and 64 direct FPGA Back I/O Lines, 4 MGTs on FireFly connector © Documentation TPCE636-DOC User Manual Software TDRV018-SW-25 Integrity Software Support TDRV018-SW-42 VxWorks Software Support (Legacy and VxBus-Enabled Software Support) TDRV018-SW-65 Windows Software Support TDRV018-SW-82 Linux Software Support TDRV018-SW-95 QNX Software Support For other operating systems please contact TEWS.

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