TA100-Y230C2X01-00B-VAO

Microchip Technology

CryptoAutomotive??TA100 (B5) Summary Data Sheet Rev D

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Technical content

Features

Advanced Crypto Engine (ACE) for Execution of All Cryptography Commands
Fast Crypto Engine for SHA-256, HMAC and AES-CMAC Algorithms
Sign/Verify Support: – ECDSA – P224, P256, P384 and 256-bit Brainpool elliptic curves – ECDSA – SECP256K1 (Bitcoin/Blockchain) curve – RSA 2048-bit signature generation and verification – RSA 3072-bit signature verification only
ECDH/ECDHE/ECBD Key Agreement Support – Elliptic-Curve Diffie-Hellman (ECDH) Support for P224, P256, P384 and 256-bit Brainpool – Elliptic-Curve Burmeiseter-Desmedt (ECBD) Support for P224 Curve
Internal Symmetric and Asymmetric Key Generation and Derivation: – P224, P256, P384 and 256-Bit Brainpool – 2048-bit RSA keys – AES 16-byte keys
AES and RSA Encryption / Decryption Support – AES ECB/GCM Encryption/Decryption Supported directly – RSA 1024-bit and 2048-bit Keys Encryption/Decryption Support
NIST SP800-90 A/B/C Random Number Generator (RNG)
Multiple I/O Options for Security Commands Include: – 1 MHz standard I 2C interface – 16 MHz SPI interface
Package Options: – 8-lead SOIC – 14-lead SOIC
Voltage Supply Range: 2.7V to 5.5V
Automotive Temperature Range: -40°C to +125°C Ambient Operating Range

Applications

Full and Partial Secure Boot This is a summary document. A complete document is available under NDA. For more information, please contact your local Microchip sales office. © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 1

Secure Firmware Update
CAN Message Authentication
WPC 1.3 Qi High Power Transmitter Authentication
High-Bandwidth Digital Content Protection (HDCP) Cryptographic Support
Network Authentication and Session Establishment using TLS
Electric Vehicle (EV) Battery Authentication TA100 (B5) © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 2

Pin Configuration The TA100 device comes in three package configuration options based on the desired I/O interface. These include:

SPI only interface in 8-pin SOIC
I 2C only interface in 8-pin SOIC
SPI and I 2C interfaces in 14-pin SOIC Based on the configuration selected, different GPIO options are available.

1.1 SOIC-8 Pinout with SPI Interface

The 8-pin SOIC SPI interface consists of the four SPI signals, a Reset signal and GPIO_3. Table 1-1. 8-Pin SOIC SPI Pin Configuration Pin Name Pin Number Function CS 1 Chip Select for SPI RESET 2 Reset Input, active low GPIO_3 3 GPIO_3 VSS 4 Ground SI 5 SPI Serial Data Input SCK 6 SPI Clock SO 7 SPI Serial Data Output VCC 8 2.7V-5.5V Power Supply Figure 1-1. Pinout 4 SI SCK SO VCC 8CS GPIO_3 VSS RESET SPI I/O RESET GPIO Pwr/Gnd

1.2 SOIC-8 Pinout with I2C Interface

Pull-up resistors are required for proper operation of the I2C bus, sized according to the board configuration and bus speed per the I2C specification. Table 1-2. 8-Pin SOIC I2C Pin Configuration Pin Name Pin Number Function GPIO_1 1 GPIO_1 GPIO_2 2 GPIO_2 GPIO_3 3 GPIO_3 VSS 4 Ground TA100 (B5) Pin Configuration © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 4

Pin Name Pin Number Function SDA 5 I2C Data SCL 6 I2C Clock RESET 7 Reset Input, active low VCC 8 2.7V-5.5V Power Supply Figure 1-2. Pinout

4 SDA

VCC 8GPIO_1 GPIO_2 GPIO_3 VSS RESET GPIO Pwr/Gnd I2C I/O

1.3 SOIC-14 Pinout with I2C and SPI Interface

In the 14-pin package, there is access to both the I2C and SPI bus pins. Both can be used simultaneously. However, any concurrent transactions must be to different blocks in the device. Pull-up resistors are required for proper operation of the I2C bus, sized according to the board configuration and bus speed required per the I2C specification. Table 1-3. 14-Pin SOIC Pin Configuration Pin Name Pin Number Function CS 1 Chip Select for SPI GPIO_1 2 General Purpose I/O pin GPIO_2 3 General Purpose I/O pin NC 4, 5 Not Internally Connected GPIO_3 6 General Purpose I/O pin VSS 7 Ground SDA 8 I2C Data SCL 9 I2C Clock SI 10 SPI Serial Data Input SCK 11 SPI Clock SO 12 SPI Serial Data Output RESET 13 Reset Input, active low VCC 14 2.7V-5.5V Power Supply TA100 (B5) Pin Configuration © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 5

Figure 1-3. Pinout

7 SDA8

GPIO_1 GPIO_2 NC NC GPIO_3 VSS SPI I/O RESET GPIO No Connect Pwr/Gnd I2C I/O TA100 (B5) Pin Configuration © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 6

Overview The TA100 security device interfaces with a host MCU to provide a hardened root of trust with symmetric and asymmetric computation ability to facilitate a number of security-related capabilities within an automotive system.

Secure boot support: – Host code image and signature validation – Secure encryption key storage and image encryption – Authenticated update of the code validation public key
X.509 certificate storage, parsing, validation and revocation, supporting both ECC and RSA
Fully internal random key generation for RSA, ECC and AES
Monotonic counters protected against tearing
Elliptic curves support: – P224 – ECDSA sign, verify, ECDH and ECBD – P256 – ECDSA sign, verify and ECDH – SECP256K1 (Bitcoin/Blockchain) – ECDSA support – 256-bit Brainpool – ECDSA and ECDH – P384 – ECDSA sign and verify
RSA support: – 1024-bit and 2048-bit RSA OAEP/MGF encrypt/decrypt – 2048-bit RSA signature generation and verification – 3072-bit RSA verification
ECDH key management capability with integrated KDF, either PRF or HKDF
NIST SP800-90 A/B/C high-quality cryptographic random number generation
TLS V1.2/V1.3 – Full session establishment support in conjunction with host SW
AES-CMAC calculation and validation
AES-ECB and GCM encrypt/decrypt for general purpose use
SHA-256 and SHA-HMAC digest calculation
Input/output encryption and authentication using AES-GCM, AES-CMAC and/or SHA-HMAC
Flexible self-test support to meet FIPS 140 requirements
Cryptographic support for High-Bandwidth Digital Content Protection (HDCP) V2.2 The TA100 device contains two processing blocks: 1. A main command processor that implements an Advanced Crypto Engine along with the management and session establishment functionality. The ACE can implement all symmetric and asymmetric crypto functions. 2. A Fast Crypto Engine capable of implementing AES and SHA calculations in parallel with the operation of the main command processor. TA100 (B5) Overview © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 7

Device Features The TA100 device supports several broad features, including secure boot (host code authentication), MAC generation, secure key and certificate storage and management. Public information stored within the protected memory, such as code digests, certificate validation status, public keys, etc., can only be modified when properly authorized by using the specified protocols in this data sheet. The TA100 is powered by an internal microcontroller running dedicated software loaded into the ROM and nonvolatile memory during chip manufacture. Nonvolatile memory is used for certificate storage and secret/private key storage. There is no direct access to the memories from the external pins of the device and there is no available programming or debug interface. The block diagram of the TA100 shows the major architectural features of the device. Figure 3-1. TA100 Block Diagram Command ProcessorCommand Processor FAST Crypto EngineFAST Crypto Engine Digest Keys, Algorithm Power Management Power Management VCC I/O Logic I/O Logic Commands Results Instructions Data I2C SPI GPIO GPIO Circuitry GPIO Circuitry RESET TA100 (B5) Device Features © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 8

Nonvolatile Memory The nonvolatile memory within the TA100 device is split into three pieces: Configuration Memory: In general, this area is expected to be written prior to the placement of the TA100 device on the application board. Once the configuration is complete, this area must be locked to prevent further modification and for proper device operation. Shared Data Memory: This area can be used for keys, secrets, certificates, and/or data. The TA100 does not place any requirements on the arrangement or distribution of items stored within this block other than the overall limit on the space available to all the shared elements. Dedicated Data Memory: Certain other items are stored within the device and are managed directly by various commands. TA100 (B5) Nonvolatile Memory © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 9

Security Features The TA100 device includes protection against both active (invasive) and passive (noninvasive) attacks on the certificates, private and symmetric keys stored within the device. Specific hardware and firmware elements are included to prevent environmental (voltage, temperature and frequency) attacks, emissions attacks, fault attacks, physical attacks, cloning and many other attack methodologies. All internal memory for private/symmetric keys or other secret data is encrypted. TA100 (B5) Security Features © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 10

Electrical Characteristics

6.1 Absolute Maximum Ratings

Ambient Temperature under Bias(1) -40°C to +125°C Storage Temperature (without Bias) -65°C to +150°C Maximum Supply Voltage 6.0V DC Voltage on Any Pin(4) -0.5 to VCC + 0.5 ESD Ratings — Human Body Model (HBM) ESD(2) — Charged Device Model (CDM) ESD(3) ≥ ±4 kV ≥ ±750V Notes: 1. Recent Partial Networking Transceivers from Microchip and others use a spec throughout the document called the Virtual Junction Temperature, measured in accordance with IEC60747-1. An alternate definition is TVJ = TA + P x Rth(j-a), where P is the power and Rth(j-a) is the thermal resistance from virtual junction to ambient. TVJ would be higher than +125°C (maximum). 2. Specified by: JEDEC Standard JS-001-2017 3. Specified by: JEDEC Standard JS-002-2014 4. V CC is the supply voltage to which the device is driven and must be within the specified operating voltage range. Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

6.2 DC Characteristics

Table 6-1. DC Characteristics – All Interfaces Applicable over the recommended operating range from TA = -40°C to +125°C, VCC = +2.7V to +5.5V. Parameters Test Conditions Symbol Min. Typ. Max. Units Type(1) Supply Voltage on Pin VCC — VCC 2.7 — 5.5 V A Supply Current on Pin VCC Active mode(4) IIO_Active — 25 40 mA A Idle mode(2) (TA = +85°C) IIO_Idle — — 10 mA B Sleep mode IIO_Sleep — 7 15 uA B VCC Rise Rate — VRISE — — 0.1 V/µs C High-Level Input Voltage — VIH 0.7 x VCC — VCC + 0.3 V A Low-Level Input Voltage — VIL -0.3 — 0.3 x VCC V A TA100 (B5)

Electrical Characteristics

Notes: 1. Type means: A = 100% tested, B = characterized, C = design parameter. 2. Idle means that power is applied, the device is NOT in Sleep mode and no commands nor instructions are running. 3. The state of the V CC latches will be retained so long as VCC remains above the VPOR level. 4. Active current is measured with all GPIO pins either driven to ground or configured as inputs. Active current also excludes any DC load on the I/O pins. Table 6-2. DC Characteristics – SPI Interface, RESET and GPIO Pins Applicable over the recommended operating range from TA = -40°C to +125°C, VCC = +2.7V to +5.5V. Parameters Test Conditions Symbol Min. Typ. Max. Units Type(1) Input Current(2) 0.1VCC < Vi < 0.9VCC IL -2 — +2 µA A Programmable Pull-Up — RPU 24k 40k 62k Ω A High-Level Output Voltage IOH = -4 mA VOH VCC – 0.4 — — V A Low-Level Output Voltage IOL = 4 mA VOL — — 0.4 V A Notes: 1. Type means: A = 100% tested 2. This specification is only valid when the internal pull-ups are disabled. Otherwise, the input current is determined by the internal pull-up resistance value RPU. Table 6-3. DC Characteristics of SDA and SCL Pins for I2C Interface Applicable over the recommended operating range from TA = -40°C to +125°C, VCC = +2.7V to +5.5V. Parameters Test Conditions Symbol Min. Typ Max. Units Type(1) Input Current(2) 0.1VCC < Vi < 0.9VCC Ii -10 — +10 µA A Low-Level Output Voltage IOL = 20 mA VCC > 3.6V to 5.5V VOL 0 — 0.4 V B IOL = 14 mA VCC = 2.7V to 3.6V VOL 0 — 0.4 V B Programmable Pull-Up — RPU 2.3k 3.0k 4.5k Ω A Notes: 1. Type means: A = 100% tested, B = characterized on samples 2. The input current specification is only valid when the internal pull-ups are disabled. Otherwise, the input current is determined by the internal pull-up resistance value RPU.

6.3 AC Characteristics

6.3.1 All Interfaces

Table 6-4. AC Timing Characteristics – All Interfaces Applicable over the recommended operating range from TA = -40°C to +125°C, VCC = +2.7V to +5.5V. Parameters Symbol Min. Typ. Max. Units Type(4) Wake-up Time from Sleep State. VCC > 2.7V tPU.SLEEP(1) — 3 5 ms A Power-up Time from VCC < 2.7V tPU.POWERON(1) — 4 6 ms A TA100 (B5) © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 12

Parameters Symbol Min. Typ. Max. Units Type(4) Idle Tmer tIDLE(2) 0.85 1 1.15 s B Rate at which the Nonvolatile Portion of Monotonic Counter Increments tMONOTONIC 42 51 60 s B Noise Suppression on RESET Input Pin tRESET_NOISE(3) 0 — 0.150 µs A Minimum Allowed Reset Pulse tRESET_MIN(3) 1.0 — — µs A GPIO_3 Transition Ignored, Measured Starting with the Last Bit of Power (Sleep) tSLEEP_WAKE — — 250 µs A Low-Pulse Width for GPIO_3 High to Wake TA100 tWAKE_GPIO_LOW 40 — — µs A Watchdog Time-out Value tWATCHDOG 900 1000 1100 ms B Notes: 1. Various situations can cause the power-up delays to exceed these parameters as follows: – If the power-on or the wake self-test functions are enabled in the configuration area, the execution of those self-test operations will increase the delay. – If an internal failure occurs to cause a boot event, then, there may be an additional delay during the boot to write the internal failure log in the nonvolatile memory within the chip. – If a device update is started but does not complete due to a power interruption, on the next power-up, some cleanup may be required and may take additional time. – If the 1 minute timer is enabled and is being updated in the nonvolatile memory concurrent with the wake event, the device will accept an Input command after tPU_SLEEP/tPU_POWERON, but will not start the execution of that command until the nonvolatile update is complete. 2. The idle timer specifications here assume that the idle timer is enabled and configured for 1 second. It is recommended that these times be multiplied by the delay time value set in the idle timer configuration field if that is not 1. 3. All noise pulses ≤ t RESET_NOISE are assured to be suppressed. All pulse widths ≥ tRESET_MIN are assured to pass to the device. Pulses in between these values may or may not be suppressed. 4. Type Means: A = 100% Tested, B = Characterized.

6.3.2 I2C Interface Timing

Table 6-5. AC Characteristics of I2C Interface Applicable over the recommended operating range from TA = -40°C to +125°C, VCC = +2.7V to +5.5V. Parameters Symbol Fast-Mode Plus Units Min. Max. SCL Clock Frequency fSCL — 1000 kHz SCL High Time tHIGH 260 — ns SCL Low Time tLOW 500 — ns Start Setup Time tSU.STA 260 — ns Start Hold Time tHD.STA 260 — ns Stop Setup Time tSU.STO 260 — ns Data in Setup Time tSU.DAT 50 — ns Data in Hold Time tHD.DAT 0 — ns Input Rise Time(1, 3) tR — 120 ns TA100 (B5) © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 13

Parameters Symbol Fast-Mode Plus Units Min. Max. Input Fall Time(1, 3) tF 20 x (VDD/5.5V)(5) 120 ns Clock Low to Data Out Valid tAA — 450 ns Time bus must be free before a new transmission can start (1) tBUF 500 — ns Pulse width of spikes that must be suppressed by the input filter(4) tSP — 50 ns Notes: 1. Values are based on characterization and are not tested. 2. AC measurement conditions: input pulse voltages: 0.3 x V CC to 0.7 x VCC, input rise and fall times: ≤ 50 ns. 3. System designers must ensure that all AC parametrics are met. Rise fall times shown are for the Fast Mode Plus (1 MHz) of operation. For slower clock speeds, the rise and fall times may be increased but must still meet the industry standard I2C specification UM10204. 4. Input filters on the SDA and SCL pins will suppress noise spikes of less than 50 ns. 5. Backwards compatibility is necessary for the Fast mode (400 kHz) specifications. Figure 6-1. I2C Synchronous Data Timing SCL SDA IN SDA OUT tF tHIGH tLOW tLOW tR tAA tDH tBUF

6.3.3 SPI Interface Timing

Table 6-6. AC Characteristics of SPI Interface Applicable over the recommended operating range from TA = -40°C to +125°C, VCC = +2.7V to +5.5V. Parameters Symbol Min. Max. Units SCK Clock Frequency fSCK — 16 MHz SCK High Time tWH 20 — ns SCK Low Time tWL 25 — ns CS High Time tCS 100 — ns CS Setup Time tCSS 100 — ns CS Hold Time tCSH 100 — ns Data in Setup Time tSU 5 — ns Data in Hold Time tH 5 — ns Input Rise Time(1, 2) tRI — 2 μs TA100 (B5) © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 14

Package Marking Information As part of Microchip’s overall security features, the part marking for all crypto devices is intentionally vague. The marking on the top of the package does not provide any information as to the actual device type or the manufacturer of the device. The alphanumeric code on the package provides manufacturing information and will vary with assembly lot. It is recommended that the packaging mark not be used as part of any incoming inspection procedure to identify the device. TA100 (B5) Package Marking Information © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 16

Package Drawings 8.1 8-Lead SOIC

0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-OA Rev F Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC] © 2020 Microchip Technology Inc. R 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

Microchip Technology Drawing No. C04-057-OA Rev F Sheet 2 of 2 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2020 Microchip Technology Inc. R Foot Angle 0° - 8° 15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top 0.51-0.31bLead Width 0.25-0.17cLead Thickness 1.27-0.40LFoot Length 0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10A1Standoff --1.25A2Molded Package Thickness 1.75--AOverall Height

1.27 BSCePitch

protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: Footprint L1 1.04 REF 5. Datums A & B to be determined at Datum H. TA100 (B5) Package Drawings © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 18

Microchip Technology Drawing C04-2057-OA Rev F BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2020 Microchip Technology Inc. R Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC] TA100 (B5) Package Drawings © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 19

8.2 14-Lead SOIC 0.20 C N 2X N/2 TIPS TOP VIEW SIDE VIEW VIEW A–A Microchip Technology Drawing No. C04-065-D3X Rev D For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2017 Microchip Technology Inc. R A e B E D E D NX b A2AC SEATING PLANE 0.10 C 14X

0.10 C D

c hh H SEE VIEW C (L1) L R0.13 R0.13 VIEW C NOTE 1 3 0.10 C NOTE 5 NOTE 5 14-Lead Plastic Small Outline (D3X, UEB, M5B, UEB) - Narrow, 3.90 mm Body [SOIC] Atmel Legacy Global Package Code SVQ TA100 (B5) Package Drawings © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 20

Microchip Technology Drawing No. C04-065-D3X Rev D Sheet 2 of 2 14-Lead Plastic Small Outline (D3X, UEB, M5B, UEB) - Narrow, 3.90 mm Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2017 Microchip Technology Inc. R Foot Angle 0° - 8° 15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top 0.51-0.31bLead Width 0.25-0.10cLead Thickness

1.04 REFL1Footprint

0.50-0.25hChamfer (Optional)

8.65 BSCDOverall Length

0.25-0.10A1Standoff --1.25A2Molded Package Thickness 1.75-- AOverall Height Foot Length L 0.40 - 1.27 or protrusion, which shall not exceed 0.25 mm per side. REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimension D does not include mold flash, protrusions or gate burrs, which shall Pin 1 visual index feature may vary, but must be located within the hatched area. § Significant Characteristic Dimensioning and tolerancing per ASME Y14.5M not exceed 0.15 mm per end. Dimension E1 does not include interlead flash 5. Datums A & B to be determined at Datum H. Lead Angle 0° - - Atmel Legacy Global Package Code SVQ TA100 (B5) Package Drawings © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 21

E MAX Contact Pad Length (X14) Contact Pad Width (X14) Y X 1.55 0.60 NOM CContact Pad Spacing 5.40 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2017 Microchip Technology Inc. E X Y C SILK SCREEN Microchip Technology Drawing No. C04-2065-D3X Rev D 14-Lead Plastic Small Outline (D3X, UEB, M5B, UEB) - Narrow, 3.90 mm Body [SOIC] Atmel Legacy Global Package Code SVQ TA100 (B5) Package Drawings © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 22

Revision History Revision C (Dec 2021)

Removed References to 24-VQFN Package. Not an option for B5 Silicon.
Added Type of testing column to Table 6-4
Added Figure 6-3 for SPI Mode 3 Timing information. Revision B (Feb 2021)
Updated Feature List to include RSA signature generation and verification capabilities
Correction to Table 6-2 RPU Max value
Update to Product Identification System Revision A (Nov 2020) Original release of the document TA100 (B5)

Revision History

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Distributor or Representative
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Embedded Solutions Engineer (ESE)
Technical Support Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: www.microchip.com/support TA100 (B5) © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 24

Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO I/O Type - Temperature Range IC Revision Package Option Firmware Revision - OTS Shipping Format - Product Identifier xxxxx y - t xxx ppp ff - cc s - VAO Device: TA100 I/O Type Blank 14-Pin SOIC SPI and I2C Interfaces Blank 8-PIN SOIC SPI Interface Only T 8-PIN SOIC I2C Interface Only Temperature Range: Y -40℃ to +125℃ Package Option C2X 8-Pin SOIC D3X 14-Pin SOIC Firmware Revision

01 Firmware Release 01

02 Firmware Release 02

00 Standard Configuration

T Tape and Reel(1) B Bulk Units Product Identifier VAO Generic Automotive Product Examples: Customer Ordering Code I/O Interfaces Internal I2C Pull-up Package Delivery Personalization TA100T-Y230C2X01-00T-VAO I2C No SOIC-8 Tape and Reel Standard Configuration TA100T-Y230C2X01-00B-VAO I2C No SOIC-8 Bulk Standard Configuration TA100-Y230C2X01-00T-VAO SPI — SOIC-8 Tape and Reel Standard Configuration TA100-Y230C2X01-PDT-VAO SPI — SOIC-8 Tape and Reel SPI Pull-ups Disabled TA100-Y230C2X01-00B-VAO SPI — SOIC-8 Bulk Standard Configuration TA100-Y230C2X01-PDB-VAO SPI — SOIC-8 Bulk SPI Pull-ups Disabled TA100-Y230D3X01-00T-VAO I2C, SPI No SOIC-14 Tape and Reel Standard Configuration TA100-Y230D3X01-00B-VAO I2C, SPI No SOIC-14 Bulk Standard Configuration Notes: 1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2. IC Revision code indicates the base silicon revision and ROM code revision. TA100 (B5) © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 25

Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip products:

Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. Legal Notice This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/ design-help/client-support-services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, TA100 (B5) © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 26

dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM- ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020-2021, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. ISBN: 978-1-5224-8955-9 Quality Management System For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. TA100 (B5) © 2020-2021 Microchip Technology Inc. and its subsidiaries Summary Datasheet DS20006369C-page 27

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Product Information

TA100-Y230C2X01-00B-VAO specifications and overview.

Summary

CryptoAutomotive??TA100 (B5) Summary Data Sheet Rev D

Description

CryptoAutomotive??TA100 (B5) Summary Data Sheet Rev D

Source title TA100-Y230C2X01-00B-VAO Datasheet(PDF) - Microchip Technology

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