T7932 | DigiCamel IC Datasheet

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T7932 TOSHIBA | Alldatasheet

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TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC COLUMN DRIVER LSI FOR A DOT MATRIX GRAPHIC LCD The T7932 is a column (segment) driver for a small- or medium-scale dot matrix graphic LCD. The T7932 realizes a low power LCD system using the CMOS Si-Gate process. The T7932 stores 4-bit/8-bit display data transferred from aN a microprocessor. The built-in display RAM image a corresponds to the LCD screen and the data is converted & _ 5 to an LCD drive signal. The T7932 can be combined with ig pg qq a T7933 to construct an LCD system. An MPU can drive the 17932 directly. FEATURES QEFP80-P-1420-0.80A Weight: 1.5g (typ.) © Dot matrix graphic LCD column driver with display RAM. @ Interface : with 80-series MPU and 68-series MPU (4-bit /8-bit) @ Selectable column output pin arrangement (Optional mode : odd/even separate mode) © Relation of RAM data = Display @ RAM bit data 1--ON @ RAM bit data 0: OFF © Display RAM capacity : 50x8x4=1600 bits @ LCD drive output : 50 @ Duty : Can be controlled by external input signal. @ Various functions Display Data Read/Write, Display ON/OFF, Set Address, Set Display Start Page, Read Status, Set Up/Down mode @ Low power consumption @ Logic power supply : 5V+10% © 80-pin flat plastic package 961001EBA2 © TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in_general_ can malfunction or fail due to their inherent electrical sensitivity and vulnerablity to physical stress. itis the responsiblity of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating rangot a: tet forth in the most racont products epecificatione. Alto, pleate keep in mind the precautions and conditiont sot forth in the TOSHIBA Semiconductor Reliability Handbook. The Products described in this document are subject to foreign exchange and foreign trade control laws The lnformation contained herein is presented only as a guide for the applications, of our products. No responsibilty is assumed by, TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by imolication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others, @ The information contained herein is subject to change without notice. 1997-04-07 1/20

SEG1 , SEG3 ss SEGAB | SEGSO % rs & 1 1 FpRIVE circuits | $f _——— Vuc2 —— ¥ eh | tot ot (obit) ot ot ot FY vies ress 8) / [22] Fe=— 74 a rm : f g [4 FA Fy a LsB cS & 807 t Sh 2} ]. Lf iase race 0 cl. ||2 sc = as g a Poo fa 3 2 25 a SATT (UEWELED ve sommrmmom | 812 ae Peo a a 8 cy 4 8 M x fn e Y DECODER (TWO GROUPS) Vics. 1997-04-07 2/20

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 sec39 1 64 WVss se637 3 PIN INDEX 62 J ginc sec3e 4 6 fg2 sec3s Ms 6o yt seca4 6 59 Isc se633 7 58 im sec32 fs 57 ff oe7 sec31 9 56 fl oa6 3€630 Mf 10 35 Boas seG29 11 17932 54 [pea secze Mf 12 53 ff oa3 se627 13 ror view) 52 fez sec26 M14 51 fier sec2s Mf 15 50 ff 080 SeG24 ff 16 49 fos £623 17 48 BE R/w (RD) SEG22 B18 47 Whe (wr) see2t Mf 19 46 ics £620 ff 20 45 Wcs2 seGt9 21 44 [csi secre Mf 22 43 [rst ne Mf 23 42 Pies SeG17 I 24 41 Bvoo 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 4997-04-07 3/20

(Ms =L) geeeesesgggaes,' AaRRSRR RRR ES SS BB 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 sec2a 1 64 Mss se628 3 PIN INDEX 62 J ginc sec30 4 6 fg2 se632 5 6o fyi seca4 6 59 Isc sec36 7 58 im secas fs 57 ff oe7 secao 9 56 fl oa6 seca2 Mf 10 35 Boas secaa 11 17932 54 [pea secae Mf 12 53 ff oa3 secas Mf 13 «ror VIEW) 52 vez secso Mf 14 51 fier secao Bf 15 50 ff 080 seca7 Mf 16 49 fos seas 17 48 BE R/w (RD) SEG43 18 47 Whe (wr) seca Mf 19 46 fics3 e639 ff 20 45 Bcs2 se@37 Mf 21 44 [csi Se635 Mf 22 43 [rst ne 23 42 Biss $6633 Mf 24 41 Wvoo 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ARR RRRR RR RS 1997-04-07 4/20

SEG5O LCD drive signal outputs Vics cs1 to Vpp to ¢s3 Input READ / WRITE enable Vss [Ht | 1 [WRITE enable only | WRITE enable only WRITE enable only Lx [a | H [READ/WRITE enable | @® E (68-series MPU) @ R/W=L write data : Data of DBO to DB7 latch to the input register at the falling edge of E. E (WR) Input @ R/W=H read data: Data of DBO to DB7 output to MPU Vpp to when E=H Vss @® WR (80-series MPU) @ Write operation : Data of DBO to DB7 latch to the input register at the rising edge of WR. ® R/W (68-series MPU) @ R/W=H: Data output to MPU when E=H and CS2, CS3=H. @ R/W25L : The input register can accept data when CS2, _ CS3=H or CS1=H. Vpp to R/W (RD) | Input | © RB (B0-series MPU) Vss e RD=L : Data output to MPU when CS2, CS3 =H. @ RD=H: The input register can accept data when CS2, CS3 =H or CS1=H. Select data / instruction Vpp t D/I Input D/I=H : Data DBO to DB7 is display data. iv ° D/I=L_: Data DBO to DB7 is instruction data. Ss Data bus : bi-directional three-state bus. E (WR) | R/W (RD) STATE OF DBO TO DB7 a DBO to a ee ee Vpp to ba7 VO) | igh impedance ss OTHERS High impedance * : Don’t Care (Note) 68-series MPU 1997-04-07 5/20

sc Input 17932 output column signal corresponds to display data Vi synchronized to the rising edge of SC. SS Display synchronous signal Vpp to Input M sets the 5-bit display line counter and synchronizes a row V signal to the frame timing when M becomes high. ss Select CPU type 80/68 | Input | 80/68=H : 80-series MPU Yop to 80/68=L_: 68-series MPU SS 80/68=H : input terminal for ¢ or CLK signal. Vpp to Reset signal Vpp to RST Input RST=L sets display OFF, and sets mode to Y-address counter. Vi Maintains this state until changed by another command. ss Bus select BS=H : 4-bit interface (DB4 to DB7) first send upper 4 bits, then Vss lower 4 bits. Select pin assignment EES ec MS=H: Normal output Vss * See PIN ASSIGNMENT 1997-04-07 6/20

@ Interface The T7932 can interface to a 4-bit or 8-bit MPU. (1) 4-bit mode (BS = H) The T7932 can transfer 8-bit data (4 bitsx2) when BS=H. The T7932 uses the upper 4 bits (DB4 to DB7) for data transfer. The upper 4 bits are transferred first, then the lower 4 bits. (2) 8-bit mode (BS =L) When BS is held at L, the T7932 uses DBO to DB7 to data transfer. @ Input register 8-bit data from the MPU is latched to this register. The D/I signal distinguishes between instruction data and display data. © Output register 8-bit data is read from the display RAM, latched to the output register, and the address is automatically incremented or decremented by 1. The MPU cannot read correct data on the first data reading, but reads the correct data on the second read operation. @ X-address register This register stores a page address for display RAM reading or writing. @ Y-address counter The Y-address counter has a 50-bit Up/Down counter. The T7932 increases or decreases the address with the display data read/write operation. The Up/Down mode and start address are determined by the instruction. RST=L sets Up mode for this counter. © Z-address counter The counter points to the row of display data which will be displayed next. The senior two bits hold the page numbers, and the lower three bits hold the number of the row within the page. Data output is synchronized to SC, the row driver signal, and this counter is incremented by 1 on the falling edge of SC. e@ Y-decoder The Y-decoder changes the order of the input or output data according to the MS signal. This is to allow for the alternative pin assignment that is available for the LSI. When MS=H, the regular pin assignment is used in which pins SEG1 to SEG5O are adjacent to one another. When MS=L, the even and odd-numbered pins are divided into separate blocks. See the sections DISPLAY DATA RAM and PIN ASSIGNMENT. 1997-04-07 7/20

@ Display ON/OFF flip-flop This flip-flop is set to the display ON/OFF state by the instruction. In the OFF state, outputs from the display RAM are set to 0 (display is all OFF). In the ON state, the T7932 outputs the display data held in the display RAM. This command never changes the display data in the display RAM. @ Display page register This register stores 2 bits of data which point to the display start page. The “M” signal sets the contents of this register to the value in the upper 2 bits of the Z-address counter. @ Up/Down flip-flop This flip-flop determines the count mode of the Y-address counter. In Up mode, the Y-address counter is increased by 1. If the Y-address=49, the address becomes 0 after the operation. In Down mode, the Y-address counter is decreased by 1. @ Busy flag During the execution of an instruction, the T7932 sets the Busy flag (except for when it executes the Status Read instruction). The MPU can poll the Busy flag when the MPU performs a Read Status operation. While the T7932’s Busy flag is set, the T7932 cannot accept any instructions other than Status Read. Hence the MPU must perform a Read Status before sending the next instruction. * Busy state time (T) is always shown as follows : 1/FSTS2/F [s] F: 41, $2 frequency (T7933 oscillation frequency x 1/2) @ Latch The T7932 latches the data from the display RAM at the rising edge of SC. @ LCD drive circuit The T7932 has 50 column drivers. The display data in the latch circuit and the FR signal select one of four levels of LCD drive voltage. DISPLAY CONTROL INSTRUCTIONS Y-Address (1) Set X, Y-address 0, 2," 3, 1 (MS=L) .)o]| 0 Page 0 00 o | 0 | o 0 to 49 (binary) Page 1 01 0 | 0 1 (Address) Page 2 10 o fol: page3| 11 Display Data RAM 1997-04-07 8/20

(2) Set Up/Down row] on [er [ooo] [ove om [om [or [ooo] | 1 1 1 1 Up mode 1 1 1 0 |Down mode This instruction selects the Up/Down mode for the Y-Address counter. (3) Display Start Page vw] on [oer [ow [oes oo [ows [ow[on fom] ————————*| 0 0 0 1 1 1 1 0 |Start page 0 : See Fig. 3-a 0 0 0 1 1 1 1 0 | Start page 1 : See Fig. 3-b 0 0 1 1 1 1 1 OQ |Start page 2 : See Fig. 3-c 0 0 1 1 1 1 1 0 | Start page 3 : See Fig. 3-d This instruction specifies the RAM page whose data will be displayed at the top of the LCD screen. Data is displayed starting form the first line of the indicated page up to the end line at the duty factor specified by the T7933. The relation between RAM page and display position is as follows: (3-a) When start page = page 0 N lines [A [n lines a display duty = N (N=8, 12, 16, 24, 32) Display data RAM LCD screen (3-b) When start page = page 1 Nines FBT ines Display data RAM LCD screen 1997-04-07 9/20

(3-c) When start page =page 2 ‘|n lines B Page 1 a lA a N lines Display data RAM LCD screen (3-d) When start page = page 3 [> |s lines B_ Page 1 JA fe Display data RAM N lines LCD screen (4) Display ON / OFF nw] on [om [one [oos]om [os [om [on [omo] | 1 1 1 Display ON 1 1 0 Display OFF This instruction controls the display ON/OFF setting. This instruction does not change the contents of the display RAM. (5) Read/Write Display Data iw] on [oer [oes |oas]oes]oe [on fon foo] —————d| 1 . Read : MPU<-T7932 LiL tom This instruction sends data to or receives data from the display RAM address which is pointed to. However, the MPU cannot read the correct data on the first reading. (Refer to Output Register in the Section FUNCTION OF EACH BLOCK.) 1997-04-07 10/20

(6) Status Read ow] om | oor | ome | [vu [oe [om [om] [7 [0 [easy urrpown | orFron ast] o fo [ol] L, : Reset 0: operation 1: Display OFF 0 : Display ON 1: Y-Address counter Up mode 0 : Y-Address counter Down mode 1: Busy state (except for Status Read) 17932 cannot accept any other instruction EXAMPLE OF TIMING @ 4-bit mode, 68-series MPU interface (80/68 =L) R/W (RD) J LO LO L E (WR) | LJ LJ LJ LSJ LJ LJ L_ » XM DODO MOD ROM oa 1D CUED GD CED GD GZ CD CUED ED) GED CD GEM Cl CD Gl os (Dex XO OO OX XO oe XXX KK KK XO | status | High Address | Low Address | status | High Data | Low Data | status | Read Write Write Read Write Write Read The Busy flag is set on the falling edge of the second E signal. In this mode, it is not necessary to check the Busy flag between sending the upper data nybble and sending the lower data nybble. 1997-04-07 11/20

© 4-bit mode, 80-series MPU interface (80/68 =H) bi ee | Le a ee oe ae "1! LF LF Ll — ov X= XX XK KK KO XK KEK XE os [X= XIX XD KEK KX XK XX XE oes [Xero Xs XK KON = KK KOON ow PDX XX XK KKK KK KKK | Status | sac | swat | Status |" Data | yea | Status | Read Write Write Read Write Write Read © 8-bit mode, 68-series MPU (80/68 =L) om JD LI LI! LU) LI LI Le oer LX eux KOK XX us X07 XX use XOX XX ves [Xv KX XX XX 08 KX ve XX x0 KX oes [XorevonX Xs KX XorrvonX X05 KX XorevonX Xs KX] oes LX reser XX XX eset XX oe XX eset XX XX o3 [) (X23 XD «X23 KX) CX» XX] oe [) CX X) KX 2 X_) KX XX] ot ED KX X) CX X) CX XO XJ oo ED KX XD KX X_) «XX _X_] | status | Address | status | Data | Status | Address | Read Write Read write Read Write 1997-04-07 12/20

© 8-bit mode, 80-series MPU (80/68 =H) bi l R/W (RD) J J “™ LY LF. LI — os LX sux XX XX sey KX XX ees XK XK suse) ose LX ve X Xe KX Kw KX XX ve KK KX vo ) oss [_XorevonX Xs X_Xerrvone _X_05 X_XorevonX _X_v5_ XK _Xor/on) ose LX reser XX ve XX reser K X_0¢ KX ese XK Xv KK eset) os [) CX 3 X_) «X93 X_) CX 3 X_) a, CX X_) (X22 X_) CX X_) ot [1 (XX) «_X2 X_) KX“ X) | Status | Address | status | Data | status | Address | status Read Write Read write Read Write Read 1997-04-07 13/20

com ZARA aa] LAA La] com TTA TT rat Pea ratty coms TMT | TAY CoA TAT coma = TA TT | CATT CoA TATA coms TMA TTY | CAAA CA TGA come — TATA rar CYA ra TTY com ~TATIT CATA CYT TATA come TTT rrr Coo Coo ci Display coms | AAT CAAA TAT AAA Patten COMO ALTA | rar Qo rar com $A CAT eA rat) ato Ar att Tar coms AAA rx =i] CCCREEZD: = comer SA TA TA FATT Ati a Latte coms SA TTY | CATA Attn TATA comes 4A TA Ay Ca | Are ax AA | com30 SA TTA 1 TAT '7ZaaeZe7e -7aZon com31 —4 TA | Lat ZeEZeee TVA | comaz -Aaa TTA I rat Aaa rat SN 42] Wy bid 1 50: had fi \\Nazasa950 Do enon ToporT TO) Foner Toray Dt rolotstototol fo} fofitotototi| fotitohi for} CHotototo} b2 er elolifofofor fo} fof fofofofi} fof foritohy Tt) [1 Tofofoto} D3 re Holortrororor ro} forifototor| | _ 9 folortor tr FHotototo] |, _ 4 Da rH olatitotototrtol loth} lolttortor Holototo} f X= Ds ett Holotitoforot to} lolvotofohy| lolol for CHolototo} 06 —F ELT Holottotototon | fotitototoly| fotvotoni fol Cr tifototo}

07 Hololotototototo} lofototototo} fofototototol CHotototo}

[ Holshhitotototy} loth} folfolol fol Cohfonh} ty ototori fot To} foliforoforo} } yy fon titony yy [Tfototofo} | yy +} rtototoriior ta] lotrotototo} Totoro Hotototo} f X= fijelolor rt foritititit | fijeleter yt | | [1 lolojofo) Display Frttrrt ~ [[ TIF > x-2 [ [lolol > x-2 ram oatai } 1 11) Lffihifololofi py TT oh hel orth rid Hotels folol ol lotitotoroty| Htotot torr TT tater} tii riololol toll lottoloton| Holton CHotototo} i! tifofotofi fori ti folitititi fo} ¢ x=3 fof hyor ry [1 Tifoloto} ¢ x=3 i (ololol tol fol lolol foto} Hott nto FI CHotototo} tifololifolol ol loltotoli fo} Hotolstolol Color fo} Chitolotoriior___ foffototot} Chieti Tr ___ Fr tototoh) Yoly2 |¥4|¥6 YaalYagl Yaa Yo] Y2| Ya] Ye Yaal¥a6| Ya Y1 Y3 Ys Y7 YasYa7¥4g Y1 Y3 Ys Y7 Yas¥a7Ya9 (Y Address) (Y Address) (Ms =) (Ms =) ALTERNATIVE PIN ASSIGNMENT MODE This mode allows selection of the pin assignment. In order to facilitate wiring, two alternative pin assignment layouts are available. lf MS=H, the standard assignment is selected. If MS=L, the odd and even output pins are divided into separate blocks. See the PIN ASSIGNMENT sections. 1997-04-07 14/20

In each case, the address assigned to the T7932 is shown as follows. @ Example of connection to MC6800 AIS CI O Read/Write the display data e Top & sree vine =a “3 O Write the display instruction 80 bil MS6800 jy Py aay 17932 $FFFE

2 Cl Read the status

ee |__| Rey SFFFE RST RST @ Example of connection to MC6809 AIS cst O Read/Write the display data to |p ose SFFFF “ os CO Write the display instruction a0 Dil Mcé6s09 , yf B/W ®D) 17932 $FFFE Fd ee BOS CO Read the status to to me |__| her SFFFE eS RST MC6800 and MC6809 is a registered trademark of Motorola Semiconductor Products Inc. @ Example of connection to 280 AIS CI O Read/Write the display data cle b & pea “ os C Write the display instruction a0 Dil WR wR) =17932

7932 Read the status

280 is a registered trademark of Zilog Inc. 1997-04-07 15/20

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) ITEM SYMBOL RATING UNIT Supply Voltage (1) Vpp (Note 1) -0.3 to 7.0 Vic2, Vic3. Vics Vpp - 13.5 to Supply Voltage (2) (Note 1, 2) Vpp +0.3 v Vin (ote 7) Storage Temperature -55 to 125 (Note 1) Referenced to Vss =0V (Note 2) Ensure that the following condition is always maintained. Vop= Vic2= Vic3= Vics

ELECTRICAL CHARACTERISTICS

ITEM SYMBOL| CIR- TEST CONDITIONS TYP. | MAX JUNIT| CUIT Output | Hievel | ROW | — [Vour=Vpp-05v [| — |—| 15[> Resistance [tL tevel | ROL | — [Vour=0.5v | — | — | 0.2[ ka | [H Level | ROH | — |Voyt=Vpp-o5v_| — | — | 50] ka] Vi =V2, bon Se ee ee) Resistance M Level Vic3 =V3, SEG1 to Vics = V5, L Level ROL | - | Vout=Vs +0.5V 5.0} kQ Operating Frequency | fosc_| — [Ta=~-10 to 70°C | 25 | — | 300 [kHz[s1, 2 | Vpp =5.0V Vics =0V Vic3 = V3 Current Consumption Vic2=V2 (Note 1) Iss frp = 35Hz 200 | xA| Vs fop = 215kHz SEG1 to SEGSO : no load (Note 3) Vpp =5.0V Vics = 0V Vic3 =V3 Current Consumption Vic2=V2 I 20 A Vi (Note 2) 55 fpR=35Hz - 5s fep = 215kHz SEG1 to SEGSO : no load (Note 3) (Note 1) Current consumption while the internal data receiver is operating. (Note 2) Current consumption while the internal data receiver is sleeping. (Note 3) V3=Vpp-= (Vpp- Vics) V2=Vpp-5 (Vpp- Vics) Data Level : H=5.0V, L=0V 1997-04-07 17/20

@ 80-series MPU é wah (| * troH *RDH RD *wRH Pw a |/_oa tasw, [ase | Mal CS1 to CS3 tpHW, TEST CONITIONS (Vss = OV, Vpp =5V + 10%, Ta= -20 to 75°C) ITEM SYMBOL | min | max | UNIT & Cycle Time | tyes | 250 [| — J ns | ¢ Pulse Width H, L Pw9H, PwsL| 110 | — [ns | § Pulse Rise/Fall Time [tte | — | 30 | ns | Test Load RD Hold Time | tron | 0 | 100 | ns |WR Hold Time | twrn | | 100 | ns g |WR Pulse Width L | Pwwet_ | 300 | — | ns _| . Write mode Address Set-up t Tepons ale Time ASW By Read mode Address Set-up t Fr Time ASR Address Hold Time [ tay | 10 | — J ns | Data Set-up Time | tosw | 100 | — | ns _| Data Delay Time | tppr | — [200 | ns | Write Mode Data Hold Time | tow | 10 | — | ns _| Read Mode Data Hold Time | tor | 20 | — J ns _| 9997-04-07 18720

© 68-series MPU teycE E KF tas TAH, — —| vw ‘Sas: — —| Dil | fog —e iy 1 ae TEST CONDITIONS (Vss = OV, Vpp = 5V + 10%, Ta = -20 to 75°C) ITEM SYMBOL | min | max | UNIT E Cycle Time | tye | 500 [| — | ns | [EPulse Width H | PweH | 220 | — | ns | E Pulse Width L PWEL [ 220 | — | ns | Test Load E Pulse Rise Time pt | = [20] ns | E Pulse Fall Time ee ee g Address Set-up Time [tas | 40 ~ [ins | . Address Hold Time [tay | to | — [ons J Ph TTS Data Set-up Time | tosw | 60 | — | ns | BPE Data Delay Time a I [Write Mode Data Hold Time | toyw | 10 | — | 1s | Read Mode Data Hold Time | tpyr | 20 | — [ ns_| 8997-04-07 19/20

QFP80-P-1420-0.80A Unit : mm 24.8103 20.040.2

64 Ps)

& IAA AAA | 24-65 =r! 540 —— = = = = =n cor] Erg] cor For 3} CO = Er s| 2 == = == = 4 = re} —— 801} Tr 125 ig UpAPNTATI(/RUNTAVAVA/ANRONYAQOTN]NONVA]A]NINIG ee ep eee Tepe eae papa CRT ayayepane iaina nel 4 24 O.8TyP 0.3540:1 pera TEGy ns fl Fed JW = ee o 1.2+0.2 Weight : 1.5g (Typ.) 1997-04-07 20/20

Product Information

T7932 specifications and overview.

Summary

COLUMN DRIVER LSI FOR A DOT MATRIX GRAPHIC LCD

Description

COLUMN DRIVER LSI FOR A DOT MATRIX GRAPHIC LCD

Source title T7932 Datasheet(PDF) - Toshiba Semiconductor

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