T7779

Toshiba Semiconductor

CRT/LCD CONTROLLER LSI

Manufacturer: Toshiba Semiconductor

Document: 49 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Toshiba Semiconductor Browse T parts

Online Datasheet

Read T7779 online.

T7779 TOSHIBA | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 49

Technical content

TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC CRT/LCD CONTROLLER LSI The T7779 is a controller LSI for a raster-scan-type CRT display and large-scale dot matrix LCD. It can be used in applications ranging from small-scale character display systems to large-scale graphic display systems. _- — aN FEATURES << SS @ Refresh memory address : MAO to MA15 (21%) As eo™ @ Line scanning address : LAO to LA4 (25) LEO @ Frame buffer capacity : Max 64 KBytes (character) Max 2 MBytes (graphic) @ Number of characters per line : 1 to 255 QFP100-P-1420-0.65) @ Number of character rows : 1 to 255 Weight: 1.69 (typ.) © Scrolling, Paging @ Light pen @ Horizontal dots per character according to font : 5, 6, 7,8 © Vertical dots per character according to font : 1 to 32 @ Data output : 1-bit output, 2-bit (odd/even) output, 4-bit output © Various attribute functions : Underline Cursor ON/OFF Underline Cursor Blink Character ON/OFF Character Normal / Inverse Character Blink Blink Frequency Change @ External synchronization (Non-Interlace mode only) @ HMCS6800-family-compatible bus interface @ Single 5V power supply @ High speed operation : 18 MHz @ Low power consumption @ CMOS, Si-Gate structure @ 100-pin flat plastic package 96100184: @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fall due to thei inherent electrical sensitivity and. vulnerability to physical stress. it's the responsibilty of the buyer, when utlizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified Operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. 3 The products described in this document are subject to foreign exchange and foreign trade control laws. The information contained herein is presented only as a guide for the applications ‘of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. © The iHformation contained herein is tubject to change without notice. 1997-04-07 1749

TOSHIBA Ci*T 7779” BLOCK DIAGRAM RIWE Re D0 t0D7 ca ae | a a {ra[_nevwonat roa Reg} Sor Same ||| ol a ™ sins Rig] SCF End Position Reg} {cu lS KT a {re [vertical Total nog. | Teme pees TS ees Ec Ce ol Gamat ark, ce =e — 5PM or > ee Fe rn ol =A a fi] _ worsens voc (ee ET a ———— BE ons o (g[saaero Ir" * —— tang? owe Cah pi | Eo a Cee ( Es aras wn when 11779-2

e o£ 3 wwe syoys as ag of a ee So EBay voaspibsessh Goo Uks>s 2x 2x> SIE SS TTVOG 10099 98 97 96 95 94 93 92 91 90 89 G8 7 86 85 84 63 82 81 exrint coh nce O 79 LS CRT/LCD 3 78 Rs HR/LR 4S 77 eE Hso 5 76 R/W Hsi 6 75 Bi LPsTB seve? 74a RES neces A ca 72 906 ne. if 10 co 70 fla di ffi2 69 03 a3 6s flo2 als o7 flo aos 17779 66 fl 00 ois (ror view) 65 ANC

66 B17 64 mais

UBLNK §§ 22 59M MAIO ceunk if 23 58 fl mas uten ff 24 57 fl mas CHREN §§ 25 56 MA7 amooe if 26 55 fl mas ne. 27 sa fl mas nc. 28 53 MAG sce if 29 52 mas nec. 30 si flnc 3132 33 34 35 36 37 38-39 40 41 42 43 44 45 46 47 48 49 50 1997-04-07 3/49

(Memory Address) MA MA1 0 to 5 Output Memory refresh address (Line Address) LAO to LA4 Line scanning address for character generator (Data) Data I/O terminal for built-in registers (Data) do to d7 Input Parallel data input for LCD (Address Float) ADF Input |For LA/MA outputs in High Impedance mode. High impedance when set to (Cursor Enable) CSREN Input | Underline cursor enabling signal Display of cursor is enabled when set to 1 (dO to d7 are inhibited) (Reverse Enable) RVEN Input | Reverse attribute signal. Display of dO to d7 is inverted when set to 1 (except for the cursor) (Blink Clock) BCLK Input | ciock input for blink. 0=ON, 1=OFF UBLNK (Underline Blink) Underline blink attribute signal. Blink is enabled when set to 1 CBLNK (Character Blink) Character blink attribute signal. Blink is enabled when set to 1 (Underline Enable) ULEN Input Underline attribute signal. Underline is displayed when set to 1 (Character Enable) CHREN Input Data input enabling signal. Display is enabled when set to 1 (Blink Mode) BMODE 1 To change an external/internal blink BMODE Input |<ock BCLK pu fecik : Clock frequency supplied to the BCLK . frp: Frame frequency Blink Freq. | facik | ffr/8 | fer/16 SET (Set) To set built-in registers. Set when SET=1 and CRT/LCD=1 (High Resolution / Low Resolution) HR/LR High Resolution /Low Resolution mode select. High Resolution mode is selected when set to 1 CRT/LCD (Cathode Ray Tube/ Liquid Crystal Display) CRT/LCD mode select. LCD mode is selected when set to 1 1997-04-07 4/49

(Chip Selec) [S_]|_fs_] Register name _| Chip select signal input [1 [= finvalid 5 cmon | Reaister Select [0 [0 Address register | s Put | Register select signal input [0 [1 [control register | Input | Enable) P Enable signal input. Usually connected to system ¢2 clock. (Read / Write) R/W Input R/W signal input. Read when set to 1 EC (Reset) RES Input Reset signal input. Reset when set to 0 (Light Pen Strobe) LPSTB Input Light pen strobe signal input psptuG _| Output | (isPlay Timing) Display timing signal cuDISP Output | (Cursor Display) Cursor display signal (Cursor Display /Latch Pulse) CuDISP/ LP Output Cursor display /latch pulse (Horizontal SYNC) HSYNC Output Horizontal synchronization HSYNC/FR Output (Horizontal SYNC/ Frame) Horizontal sync/ frame (Vertical SYNC) VSYNC/FP Output (Vertical SYNC/Frame Pulse) Vertical sync/frame pulse (Shift Clock Pulse) Shift clock pulse for column driver cs Output (Multi Controller Sync) — Multi controller synchronization (Upper / Lower) uit Output Upper /lower screen signal. Upper screen when set to 0 (Cycle Steal) CYCLE Output Cycle steal signal ee (Chip Enable) ce Output Chip enable signal (Data Sending Control 1) DSc1 | sc nput Serial data format select (Lower Data 3/Data Sending Control 0) LD3 /DSCO onl Serial data for column driver/serial data format select 1997-04-07 5/49

(Lower Data 0 to 2) Serial data for column driver (Upper Data 0 to 3) UDO to UD3_ | Output Serial data for column driver a (External Sync) EXS Input External synchronization (Horizontal Select) [so ToT tot Hso, HS1 Input |To determine the number of [ Hsi1 [ofofi{|1 | horizontal dots per font [Horzontal det| 5 | 6 [7 | 8 | [ Qo __[Output| Built-in dot counter output Q41/CLK Built-in dot counter output/word clock input Q2/ gE Built-in dot counter output/dot clock input (External / Internal) EXT/INT | rout | External /internal clock select. Internal clock when set to 1 | xi,xO | — [Connect to crystal oscillator TeeTT (Test) [—Vpp | =| Power supply (5¥) L_Vss | = [Power supply (OV) (Note 1) DSC1=0 : LD3/DSCO=DSCO (input) (a) DSCO =0 (1-bit mode) UDO : for dots in the upper area LDO : for dots in the lower area (b) DSCO = 1 (2-bit mode) UDO : for even dots in the upper area UD1 : for odd dots in the upper area LDO : for even dots in the lower area LD1 : for odd dots in the lower area (Note 2) DSC1=1 (4-bit mode) : LD3/DSCO =LD3 (output) UDO to UD3 _ : for dots in the upper area LDO to LD3 : for dots in the lower area 1997-04-07 6/49

@ HR/LR The HR/LR input is used to select either High Resolution mode or Low Resolution mode, in the LCD mode. The difference between the High Resolution mode and the Low Resolution mode is shown in the following diagram. reLers ec aeD:¢ dee: + Pater Creer reser Se © PD DD CPP Pe | TT REP PPPPree TT recess Tee ToT Te ere Bane PP iy yt Tey ey ee “A” displayed in High Resolution mode “A” displayed in Low Resolution mode © —EXS In Non-Interlace mode only, the EX$ input is used to synchronize the slave-CLC to the master-CLC. Ly CLK Pt a Q1/CLK Q2/ gE Qy/CLK Q2/ gE MASTER CLC SLAVE CLC (77779) (77779) mcs BS 1997-04-07 7/49

@ SET The SET input is used to set the internal registers. In LCD mode, a high level on the SET input forces the internal registers into the following state: [Rp ___|Herzontal Total | 47] 87 | a7] a7] [a1 [Horizontal Displayed | * | * | * | | [Rs [syne with i Pe [Rg [Vertical Total ————+| a | a | si | ai [as _|Vrtotal Adjust | of of] of oj} [Re __|Vertical Displayed | 255 | 255 | 255 | 255 | [Ry | Vsyne Position | 255.| 255 | 255 | 255 | [Ra [Interlace Mode and skew | 0 0] 0] 0} [Ro |Max. Scan Line Address [| * | * [| * | | [Rio |eursorstae SST * | 7 Pe [81 [eursorend Sid dP [Rig Start Adares (HP * P| | [Rig [Start Address‘ sd * |? pp | [Ria [Cursor Address (+ * | * | * [| [Ris [Cursor Address (Qi * | = p= P| [mig [tight Pen tw) Pe [iy [tight Pen sd * Pt] [Rig [SCP start Position | 128 | 128 | 128 | 728 | [R29 [Display Start Position | _o| o| o| 0 [Rp [Additional Address (7) | 2] 4] 8| 8] [893 [Additional Address (| @| 16] 32 | 32] LR : Low Resolution mode HR : High Resolution mode * —: Does not change 1997-04-07 8/49

The CE output is a low-active signal which indicates the presence of a valid data address (dO to d7, attribute) to the external logic x ‘ ‘ if DSPTMG J c The initial MA is determined by Ry2/Ry3 (Start Address Register), which is zero in this timing example. BUILT-IN REGISTERS Internal operation of the T7779 is determined by the value of the built-in registers. When you want to write to these registers, first you must write the control register address into the address register (Rg =0). Then you can write (or read) the value into (or from) the control register (Rs = 1). REGISTER READ | WRITE [0 | 0 [Address Register |x | O_| Lo [ 1 [contro! Register [ — | — | REGISTER No. REGISTER NAME SYM. I7TeTsta{3{T2ztijto} [Ro __[Hozontal Tow iW SSSCSCSC*d Horizontal Displayed [Nhd Po Horizontal Syne Position® | Nhsp [SSCS syne Width Ww3 to vwo HW3 to HWO Nhsw [Ra | Vertical Total pw [SSS [Rs Vertical Total Adjust [Na | — [SSS [Re [Vertical Displayed [wa [C—S Vertical Syne Position®™ | Nwp [SS [Re interlace Mode and skew |__| i |] [Oo] — [Vv] s] [Ro [Max Sean Line Address [We | — [| SSS [Rio |cursor stare SSS Nr “cup ep P| CC~*Y [Ry leur end Sid Neer | CSCS 1997-04-07 9/49

Rp [sar Address) iP PCS | Rag_[Start Address) PP | Riq_[Cursor Address (H) | P | Ras [Cursor Address (t) PP | Rig [tight Pen (Hy | Riz tight Pen (4) PT | Rig [SCP Start Position | Nssp_ [sc | Rig [SCP End Position | Nsep [OO | R29 [Display Start Position | Ndsp [oO | Ra [Display End Position | Ndep | | R2z_[Additional Address (H) || L_ R23 | Additional Address (L)_ TT (Note 1) Write Value of register marked by "*” (Write value) = (fixed value) -1 (Note 2) Write Value of Rg ° Intevince Sync mode ve --» (Write Value Nr) =(Appointing value) -1 @ Interlace Sync and Video mode (Write Value Nr) =(Appointing value) -2 (Note 3) For Interlace mode, the horizontal total register (Ro) must be odd. (Note 4) Bits 0 to 3 of R3 determine the width of the horizontal sync. pulse. Bits 4 to 7 of R3 determine the width of the vertical sync. pulse. po o o af 1 | Jo o o af we | jo o 7 of 2 | Jo o 7 of 2 | po o 1 if 3 po o 1 if 3 jo 1 o of 4 | po 7 oo af os | po 7 oo af os | po 1 1 of 6 | po 1 1 of 6 | ji o o of 8 | Ji o o of 38 | pr o o af 9 | Jr o o af 9 | Ji oo 7 of 10 | pr o 7 af om | pr oo 7 af om | pu o1 1 of a pra 1 of Le ts H : Scan-line time HC : Character time 1997-04-07 10/49

(Note 5) Bits 0 and 1 of Rg control the Interlace mode. Bits 4 and 5 of Rg control the DSPTMG skew. Bits 6 and 7 of Rg control the CUDISP skew. DSPTMG CUDISP }o 0] No Character No Character | 1 0 |Interlace Sync Mode One Character One Character Interlace Sync and Skew Skew Video Mode Two Character Two Character Skew Skew Not Available || 11 [Not Available (Note 6) Bit 5 of R1Q is used for blink period control, bit 6 is used to select blink or non-blink, and Bit 7 is used to select the cursor display screen for the LCD. Je P| CURSOR DISPLAY MODE CURSOR DISPLAY SCREEN | 0 0 [Non-Blink | 0 [Upper Screen [0 1 [Cursor Non-Display Li [tower Screen | 10 [Blink 1/16 Field Rate Blink 1/32 Field Rate (Note 7) Bit 7 of R1g determines the number of the LCD screen. NUMBER OF LCD SCREEN pot ot 1997-04-07 11/49

@ Address register Fi [rw 6 [on [ons [on [on [on [on [oo] [0 |wrte [| __REGISTER ADDRESS This 5-bit write-only register contains the address of one of the other 24 registers. When you want to write or read one of the registers (Ro to R23), first you must write the address of the register in this register. © Control register (Note) YW =CRT mode, W =LCD mode (1) Horizontal total register (Rg) [rw wr oes [os] ob [ons] vm [a [write] ETSY VY This 8-bit write-only register determines the horizontal sync. frequency. The value entered in this register should be one less than the total number of characters on one line. ¥ This 8-bit write-only register determines the non-displayed character times (retrace). If there is no retrace period, this LSI does not operate correctly. The retrace period is the difference between Nht+1 and Nhd (=Nht+1-Nhd). Usually this value should be set to Nhd +1. In 1 Character Skew mode, set the value to Nhd +2. In 2 Character Skew mode, set the value to Nhd +3. (2) Horizontal displayed register (R1) [5 [eons os [oe m5 [oe [ on] [a [wtf SSC CSC—~SY VV This 8-bit write-only register determines the number of characters displayed per line. The contents of R1 must be less than the contents of Rg (Nhd<Nht). (3) Horizontal sync. position register (R2) [Jew] on [ose] oss [ose [on [on [on [>] YV This 8-bit write-only register determines the horizontal sync. position. The value held in this register is one less than the computed number of characters. ¥ The horizontal sync. pulse is not necessary. However, you can use it if you wish. 1997-04-07 12/49

(4) Sync width register (R3) [ee Jrvw| on [os [oes ons [on [on [on [om] VV This 8-bit write-only register determines the width of the vertical and horizontal sync. pulses. When Nvsw=1 to 15, pulse width =1 to 15H (H : time to scan 1 line) When Nvsw =0, pulse width = 16H When Nhsw =1 to 15, pulse width=1 to 15HC (HC : time to scan 1 character) When Nhsw =0, don’t care. (5) Vertical total register (R4) [Jw] on [ose [oss] ons [on [on [on [oo] V This 8-bit write-only register determines the vertical sync. frequency. The value entered in this register is one less than the number of lines of characters. ¥ This 8-bit write-only register determines the number of rows displayed on the screen. The value held in the register is one less than the number of lines of characters. (6) Vertical total adjust register (Rs) [rw] er [oes [os [on | on] [ovo a V This 5-bit write-only register adjusts the total number of scan lines per frame. Vv Usually set to 0. (7) Vertical displayed register (Rg) saw] er [os [os [on [ons om [ono [a wel Sd V This 8-bit write-only register determines the number of character rows displayed on the screen. The contents of Rg is less than the contents of Rq (Nvd<Nvt). ¥ The contents of Rg must be more than the contents of R4 (Nvd>Nvt). Usually set to FF (Hex). 1997-04-07 13/49

(8) Vertical sync. position register (R7) [ee Jew] on [ose [oss |ose [on [on [on [oo] V This 8-bit write-only register determines the vertical sync. position. The value entered in this register is one less than the computed number of character lines. ¥ The vertical sync. pulse is not necessary. However, you can use it if you wish. (9) _ Interlace mode and skew register (Rg) [aw er [os [os [on [on | [ovo [wee | |p PS lv] s| INTERLACE MODE [Ps [Do| DSPTMG CUDISP }o [0 | | 0 | 0 [No Character Skew || 0 | 0 [No Character Skew poli] Non-Interlace Mode | 0 | 1 [1-Character Skew |] 0 | 1 |1-Character Skew | 1 | 0 |Interlace Sync Mode | 1 | 0 [2-Character Skew |] 1 | 0 [2-Character Skew [1 [1 interlace syne and video Mode| [1 | 1 [Not Available | [1 [1 [Not Available | Y Interlace modes are selected using the two low order bits of this 6-bit write-only register. DSPTMG skew is controlled by bits 4 and 5 of Rg. CUDISP skew is controlled by bits 6 and 7 of Rg. V Non-Interlace mode only is available. The skew function is the same as for CRT mode. (10) Max scan line address register (Ro) es [aw er [oes [os [op ]ons [ove Lo Writely Nt V This 5-bit write-only register determines the number of scan lines per character row. In Non-Interlace or Interlace Sync mode, the value programmed in the register is one less than the number of scan lines. In Interlace Sync and Video mode, the value is two less than the number of scan lines. ¥ This 5-bit write-only register determines the number of horizontal dots per character row. The value is one less than the number of horizontal dots. 1997-04-07 14/49

(11) Cursor start register (R19) os Jw on [ns vs os [os [oe [ox [oo] [wef [P| Nr CS V This register determines the start scan line of the cursor and the cursor display mode. Bits 0 to 4 of Rig determine the start scan line of the cursor. Bits 5 and 6 (P, B) of R19 determine the cursor display mode. ¥ In LCD 2-screen mode, bit 7 of R19 determines the cursor display screen. If you want to program the cursor position anywhere in the lower screen, bit 7 of R1q must be set to 1. (12) Cursor end register (R14) [aw] or [ on [ons [oe es [on [on om a VV This 5-bit write-only register determines the last scan line of cursor. eS Ep SE Eee > EeEeeeey 3 ECCeeeeH 2 fe] P| CURSOR DISPLAY MODE Hee: EEE; EH Non Bink Eee $ lec $ HHH? = LO | 0 [Non-Blink a ie a CTT 6 | 0 | 1 [Non-Display EEEEEEEH s Heed | 1 | 0 [Blink 1/16 Field Rate Eee 9 Eee 1 Li [1 [Blink 1/32 Field Rate PEE 12 Perey 12 PE 13 COOP 13 a COO 1a EEEETEET is COOP Tr) is Max Scan Line Address= 15 Max Scan Line Address=15 Max Scan Line Address =7 Cursor Start=0 Cursor Start=5 Cursor Start=7 Cursor End = 15, Cursor End = 10 Cursor End =7 (13) Start address register (R12, R13) 5a] or [on 5 [oe os] oo [on om | 1 [R/w| START ADDRESS (H)-R12 | 1 [R/w] START ADDRESS (L)-R13 VV This 16-bit read/write register pair determines the memory address corresponding to the first line on the screen. Hardware scrolling by line or page may be accomplished by modifying the contents of this register. 1997-04-07 15/49

(14) Cursor address register (R14, R15) os [ew] cr [on [on [oe os [on [ow [om | 1 [R/W] CURSOR ADDRESS (H)-R14 | 1 [R/w| CURSOR ADDRESS (L)-R15 VY This 16-bit read/write register pair determines the cursor display address. WV The built-in address counter generates only upper screen addresses. If you want to program the cursor position anywhere in the lower screen, this register pair must be programmed with the upper screen address corresponding to the lower screen address. (15) Light pen register (R16, R17) ox [ew] or [on 05 os os [on [on [os | 1 [Read] LIGHT PEN ADDRESS (H)-R16 | 1 [Read] LIGHT PEN ADDRESS (L)-R17 YV This 16-bit read-only register pair captures the refresh address on the positive edge of LPSTB. (16) SCP start position register (R1g) as [rw] 7 [on] 85 os | os Jono] YW This 8-bit read/write register determines the SCP (Shift Clock Pulse) start position. The value held in bits 0 to 6 of this register is one less than the computed number of characters. This value is set to 0. Bit 7 of Rig determines the number of LCD screens. (17) SCP end position register (R19) os Jw on [as ]os os [os [oe [ox [0] OD WY This 8-bit read/write register determines the SCP end position. The value held in the register is one less than the computed number of characters. This register is usually set to the same value as R41. 1997-04-07 16/49

(18) Display start position register (R29) os Jv on |e] os os os [oe [ox [0] i VV This 8-bit read/write register determines the display start position. The value held in the register is one less than the computed number of characters. The register is usually set to 0. (19) Display end position register (R21) os Jonas os sos [oz [ox [0] [7 [Rw] —SSdep SS SCC—S VV This 8-bit read/write register determines the display end position. The value held in the register is one less than the computed number of characters. This register is usually set to the same value as Ry. (20) Additional address register (R22, R23) ox [ew] or [one [ons [oe oes [on [on [om | 1 [R/w] ADDITIONAL ADDRESS (H)-R22 [1 [R/w| ADDITIONAL ADDRESS (L)-R23 YW The built-in address counter generates only upper screen addresses. The T7779 adds the contents of this 16-bit register pair to the address counter value to form the lower screen address. 1997-04-07 17/49

@ Register functions (1) An example of register values An example of register values in LCD 2-Screen mode is shown below Horizontal Total (Rg = 15H) Horizontal Displayed (Ry = 10H) —————*=— Retrace Period [oofo+]o2 Jos [o« os Jos or [os Jos oa] os]oc[oo] oe] or] 10] ss] 2] 13] 4] 15] [10 Start Address (R12, 13=00, 00H) Vertical Total (Rq = 03H) bo | Max Scan Line Address! Eee /]50 [Lower screen Start Address (R22, 23 =00, 40H) Bisplay Period (@9=07H)) HEH / Too] Cursor start (R10 =87H) ‘Cursor End (R14 =07H) { f Cursor Address (R14, 15=00, 00H) SCP Start Position (Rig = 80H) SCP End Position (R19 = 10H) Display Start Position (R29 = 00H) Display End Position (R21 = 10H) (2) Horizontal scroll function (LCD mode) Hardware horizontal character scrolling may be accomplished by modifying the contents of the SCP start position register (R1g) and SCP end position register (R79). RRO Rana BORo Ean [0offor [oe os [oe] os [0s [or [os [os Joa] os [oc Joo] oe [or] 29] [50 Bisplay Period [50 Bisplay Period SCP Start Position (Ryg=80H) SCP End Position (R19 = 08H) | | SCP Start Position (Rig=81H) SCP End Position (Ryg= 09H) | Display Start Position (Rz9 = 00H) Display End Position (R21=10H) Display Start Position (Rag =00H) Display End Position (Rz1 = 10H) 1997-04-07 18/49

(3) | Mask function Hardware character masking may be accomplished by modifying the contents of the display start position register (R29) and display end position register (R21). This function is useful for the multicontroller system. [oe [0+ [oz]os]os]os[os[or [os ]osfeafoe[ocfoo}oe]oe] [a [ei] 2] 63] 04] 05] 96] 027 [08 [09 [oa] 08] oc Joo] [oF | a es. SCP Start Position (Rig = 80H) | SCP End Position (R1g=10H) SCP Start Position (Rjg = 80H) | SCP End Position (R19 = 10H) Display Start Position (R29 = 00H) Display End Position (R21 = 08H) Display Start Position (Raq =08H) Display End Position (R21 = 10H) (4) Vertical scroll function Hardware vertical scrolling by line or by page may be accomplished by modifying the contents of the start address register (R12, 13) without modifying the contents of refresh memory. Horizontal Displayed (Ry = 10H) —————>| F-— Horizontal Displayed (Ry = 10) —————> [oa]: [oz]os[oe]os[os]or[os]os[oa]os[oc]oo[oe]or] [oof os [oz os [oa] os [oe ]or [os os [onl os [oc foo [oe [or | 10 [Start Address (R12, 13=00, 00H) [ro] [20] ‘start Address (Ry2, 13=00, 10H) E Disp [=| re Ta A 1997-04-07 19/49

(5) Skew function If the memory access cycle and the data latch are not synchronized to each other, this function must be used. DSPTMG (No Character Skew) / : DSPTMG (1-Character Skew) : / DSPTMG (2-Character Skew) : / @ SCREEN FORMAT Nht+1 Nsep Nhd Ndep NdsP NssP, Upper screen start address ——= Newt | Non-display (OFF Data) Lower screen start address ——> cP scp stopped stopped Next line address } fetch position SCP start t Position SCP end position Non-display (OFF Data). { Display end position Display start position 1997-04-07 20/49

@ Relationship between memory address (LAO to LA4) and memory data (dO to d7) The addresses of vertical dots are in hex. format. Horizontal dot Vertical dot d7 d6 d5 d4 d3 d2 di dO [J yy yy yy | EEEEE EE CEE Je b : Valid data when these are 6 horizontal dots (¥S0=1; HSY =O) he he I de iSO =0, HS1= 1) i o GL! Valid date wien these are horizontal dots (#501 HS 1) os Pt Tt ty yy Jos EX.) When address is 07H [TT Jo d 1997-04-07 21/49

@ Relationship between the display screen and memory addresses (MAO to MA15, LAO to LA4) CHAR- ACTER| Display period Retrace period une [Xf 000{ 0000 | 0001 ooar [| oo50 | 001 | 0000 ooar | ooo | | , pomp woof PT worp mofo PT 111] 0000 | ooo1 | > | ooar | oo50 [| 000 | 0050 coor [| ooao | | ‘ eff | Et “ 111 | 0050 0051 009F ooo | Po of yo ft yo fT ooo]_o3co | o3cr [| > | oaor [ oso [| aif o3co_[ o3c1 | > | oaor | oaio | 000 |__0410 0411 O45F o4co [| " et ft tL tt 111] 0410 0411 045F oaco | bt of vot yop | Lower screen 111] 0780 o7cr_[ 0700 [| (Note) State address : OOOOH LCD lower screen additional address : 0410H Nr (maximum raster address) : 07H 80 characters x 13 lines x2 screens 1997-04-07 22/49

@ OPERATING MODES The T7779 has two operating modes; CRT mode and LCD mode. LCD mode is further subdivided into 1-Screen mode, 2-Screen mode, High Resolution mode and Low Resolution mode. (1) CRT mode When CRT/LCD =0, the T7779 operates in CRT mode. The 17779 consists of a CRT controller and LCD interface circuit. In CRT mode, the T7779 uses the CRT controller circuit only. When the T7779 is operating in CRT mode, you can use the parallel-to-serial circuit that is included in the LCD interface circuit. However, when you have to operate the P/S circuit at more than 18 MHz, you cannot use the built-in P/S circuit. (2) LCD mode When CRT/LCD =1, the T7779 operates in LCD mode. When the 17779 is operating in LCD mode, the CRT controller circuit generates only upper screen addresses. a) 2-Screen mode When the T7779 is operating in LCD mode, the cycle time of the built-in address counter is twice that when the T7779 is operating in CRT mode. In 2-Screen mode (Rjg-bit 7=1), the 17779 generates the lower screen address by adding the built-in address counter value and the contents of R22, R23. When U/L=L, the upper screen address is sent out from the MAO to MA15 pins. When U/L=H, the lower screen address is sent out from the MAO to MA15 pins. In this case, however, the LAO to LA4 outputs do not change. So it is impossible to set a row that extends from the upper screen to the lower screen. The cycle time of the U/L-signal is twice as long as that of the CYCLE-signal. The CYCLE- signal is L in the first half of the U/L-signal, and H in the second half of the U/L-signal. If the CPU accesses the display memory when CYCLE =L, you can rewrite the display memory without disturbing the display. b) 1-Screen mode When the T7779 is operating in LCD mode, the cycle time of the built-in address counter is twice that when the T7779 is operating in CRT mode. In 1-Screen mode (Rjg-bit 7 =0), the upper screen address is sent out from MAO to MA15 pins during the cycle time of the U/L- signal. The CYCLE-signal is sent out using the same timing as in 2-Screen mode. ©) High Resolution mode High Resolution mode is usually set (HR/LR = 1). d) Low Resolution mode In Low Resolution mode (HR/LR=0), each horizontal dot is displayed twice. When the total of horizontal dots=640 and the number of horizontal dots per character =8, 80-characters are displayed in High Resolution mode and 40-characters are displayed in Low Resolution mode. When you change the High Resolution /Low Resolution mode setting, you must change not only the HR/LR pin but also the contents of the built-in registers to match 40-character display. 1997-04-07 23/49

@ MEMORY INTERFACE If the CPU accesses the memory while the T7779 is accessing the memory, the display will be disturbed. There are two methods for rewriting the display memory without disturbing the display. One is to rewrite the display memory during the retrace period (DSPTMG =L). The other is to rewrite the display memory while CYCLE =L. A detailed explanation of the second case is shown below. (1) Interface for CRT mode The interface circuit must be constructed so that the CPU can access the memory when CYCLE =L. Internal oscillation mode XI l l l J l J J J External oscillation mode ck cycle J ‘Address Cycle Time Address Cycle Time When fg = 16 MHz, address cycle time=500 ns (2) Interface for LCD 2-Screen mode The interface circuit must be constructed so that the CPU can access the memory when CYCLE =L. Internal oscillation mode XI | l | J | J J J © UUUUUU UU UU $e External oscillation mode ck cycle J ‘Address Cycle Time Address Cycle Time When fg = 16 MHz, address cycle time=500 ns 1997-04-07 24/49

(3) Interface for LCD 1-Screen mode The interface circuit must be constructed so that the CPU can access the memory when U/L=L. Internal oscillation mode x! l l l J l J J J « WUUUUUU UU $e External oscillation mode ck ui ‘Address Cycle Time When f¢ = 16 Mz, address cycle time = 1000 ns @ MONITOR INTERFACE (1) CRT (NTSC) The resistance-mixing circuit generates a monochrome composite signal. S0pF Ste 5v bo Le 2 LE HSYNC —y 20 © vane > P +5V S - VIDEO 1997-04-07 25/49

(2) LCD You can connect the T7779 (directly or through a CMOS buffer) to various types of LCD module that are on the market, and make various settings, such as 1 or 2 screens, the number of data bus lines, the number of horizontal dots and the duty. The relation between data transmission, the shift clock and latch pulse is as shown below. The shift clock frequency becomes low as the number of data lines increases. Hence it is useful for the low power system. eo LL ‘bit Serial (scp l mM mM | ceeeee ih n eo FD $ 2-bit Even/Odd < SCP l l J J l l [ en $ Abit Parallel 4 SCP J [ @ Timing Chart (I) (HR/LR=1 : High Resolution mode) (1) Internal clock (Qy/CLK =Qy, Q2/ $E=Q2) a) Hor. dots per font=5 b) Hor. dots per font=6 (HSO =0, HS1 =0) (HSO = 1, HS1=0) 40 1 2 3 ao 50 1 2 3 gs to x! xi a0 0 a a e Q2 1997-04-07 26/49

° Hor. dots per font=7 d) Hor. dots per font=8 (HSO =0, HS1 = 1) (HSO = 1, HS1 = 1) 60 1 2 3 4 5s 6 0 701 2 3 gs 6 7 0 xi xi a0 Q0 Qa a e Q2 (2) External clock (Q1/CLK=CLK, Q2/ gE = gE) a) Hor. dots per font=5 b) Hor. dots per font=6 (HSO =0, HS1=0) (HSO = 1, HS1=0) cK cK ge ge ° Hor. dots per font=7 d) Hor. dots per font=8 (HSO =0, HS1 = 1) (HSO = 1, HS1 = 1) cK cK ge ge @ Timing Chart (II) (HR/LR=0 : Low Resolution mode) (1) Internal clock (Q1/CLK =Q4, Q2/ gE =Q2) a) Hor. dots per font=5 b) Hor. dots per font=6 (HSO =0, HS1 =0) (HSO = 1, HS1=0) xi xi 20 0 a a Q Q 1997-04-07 27/49

° Hor. dots per font=7 d) Hor. dots per font=8 (HSO =0, HS1 = 1) (HSO = 1, HS1 = 1) xi x! Qo 0 a a @ a (2) External clock (Q1/CLK=CLK, Q2/ gE = ¢E) a) Hor. dots per font=5 b) Hor. dots per font=6 (HSO =0, HS1 =0) (HSO = 1, HS1=0) cK cK ge ge ° Hor. dots per font=7 d) Hor. dots per font=8 (HSO =0, HS1 = 1) (HSO = 1, HS1 = 1) cK cK ge ge @ Timing chart (II) $<. —+4 c 1 1/ (24fgR)=Hor. dots per font x Columnsx Ver. dots per font x Rows x 2/fosc ff: Frame frequency Columns : Total number of horizontal characters Rows: Total number of vertical characters fosc __: Oscillator frequency fosc=¢ =2-SCP (1-bit mode) =4SCP (2-bit mode) =8:SCP (4-bit mode) 1997-04-07 28/49

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) ITEM SYMBOL RATING UNIT Supply Voltage Vpp (Note) -0.3 to 7.0 Input Voltage Vin (Note) | -0.3 to Vpp +0.3 Operating Temperature -20 to 75 (Note) Referenced to Vss =0V

ELECTRICAL CHARACTERISTICS

TEST CONDITIONS (Unless otherwise noted, Vss =0V, Vpp =5.0V + 10%, Ta= -20 to 75°C) TEST ITEM ISYMBOL| CiR- | TEST CONDITIONS TYP. | MAX |UNIT CUIT Operating Voltage [Yoo |—-[ | 45 | so] ss[v] —_] Input Voltage PHevet| Vin [== |Vpp-08[ — | Vpn |v | Wate 7 of [ttevel [vu [=f = | = Tos [Vv [note 1) Input Voltage Htevel| Vy [— f= 2.2 | — [vp [VJ Note 2) [utevel | Ve [=| — | oo | =~ T 08] v [Note 2)| Output Vorage [Htevel| Vou |— | Wpp=03[ — [Vo [wT —— Output Resistance |Htevell Row | — |Vour=Vpp-05v[ — { — [ aoof a | — | . i Operating Frequency | fax {[—[ oo — | = | = J 4.0 [Mite] (note 4) icarrent Consumption [pp [= [upp =S0v = 60 | ma [Note 5) (Note 1) Applied to EXT/INT, HSO, HS1, LD3/DSCO, DSC1, TEST1 (Note 2) Applied to inputs other than those marked (Note 1) (Note 3) Applied to Q2/¢E (Note 4) Applied to Qy/CLK (Note 5) LCD, High Resolution, 2-bit transfer, 8 dots/font 640 x 104x2 screens, fg =9 MHz 1997-04-07 29/49

@ CRT/LCD=1 (LCD mode), EXT/INT=0 (External clock) tgc

3 Pwo

*$R pwet [| # LJ tCKE. ECKH, tcyD, t tuLD tULD. uit \\ tcep. ‘SCP TEST CONDITIONS (Vss =0V, Vpp =5.0V + 10%, Ta= -20 to 75°C) ITEM SYMBOL TEST CONDITIONS | mine | max | UNIT gE Cycle Time a G1 Pulse Width pweH [Sid — |_| gE Rise and Fall Time [ tyrtgr | | = [20 ns | CLK Rise and Fall Time [tex tcxe [= 20 Ts CLK Set-up Time [tes | Tt | = Ts | [ck Hold Time | tex | ——*dY tof — | rs | CYCLE Delay Time [typ [| = 80 Ts U/L Delay Time [tuo | = 80 Ts SCP Delay Time [tcp [| | 80 Ts] 1997-04-07 31/49

@ CRT/LCD=1 (LCD mode) scp a = U0 to ub3 nD ee we treo tERD FR TEST CONDITIONS (Vss = OV, Vpp =5.0V + 10%, Ta= -20 to 75°C) Data Delay Time a FP Delay Time a FR Delay Time [tro [T= 20 nsf 1997-04-07 33/49

@ CRT/LCD=0 (CRT mode), EXT/INT=1 (Internal clock) twsD. wc tDTD. tCDD tHSD tvsD. tLAD. Lan ose ry tMAD, tds tdH dO to d7 Qo teyD. tcyD. tdD tdD TEST CONDITIONS (Vss =OV, Vpp =5.0V + 10%, Ta= -20 to 75°C) symeot_| Test conorions | win | max | unrr | CS Delay Time a a DEPTMG Delay Time [oro | 200] CUDISP Delay Time [eo | 100] HSYNC Delay Time a VSYNC Delay Time a [tA Delay Time | wap | i || | MA Delay Time [wap | 900s] Tos¢=10Mrz [-200-| =| s_| Data Hold Time [an Tose = TOME [of — |_| CYCLE Delay Time 7 [Data Delay Time | tgp | a0 | 1997-04-07 34/49

@ CRT/LCD=0 (CRT mode), EXT/INT=0 (External clock) tMsD. — TCKR ‘MSD | MCs DsPTMG cupise HSYNC tvsp tvs VsYNC LAD a0 wins mx MAD MAO to MAIS tas ta dO to d7 Attribute ra ig $e tckD. -— Toko cK Pw gH pws tgo wo Xk KX XK XX KX) 1997-04-07 35/49

TEST CONDITIONS (Vsg = OV, Vpp =5.0V + 10%, Ta = - 20 to 75°C) [rem sve] test conprions | win | max | unrr | fax Cycle time | exe Si | [CLK 7 Pulse width| pween [ot | [CLK Rise and Fall Time | ‘exe, tee | —+4| — | 20 | re | [Mics Delay Time | tsp [| Si 20 | rs [OsPTMG Delay Time | toro | 140 [CUDISP Delay Time | tev. | 180 |r [SYNC Delay Time | tsp [| | — | 120 | ms | [VSYNC Delay Time | tvsp [180s | [tA Delay Time ‘| tap | 110s [MA Delay Time | tmap | — +4 — | 140 |r| [Data Set-up Time | tas [fosc= 10. WHe | 200 — |r | [Data Hold Time | tau |fosc=10.wHz | _o[ — | rs | [gE Cycle Time | tse [| Si | [se 1 Pulse width| _PwgH [| 775 [ — | re | [SE 0 Pulse Width | _Pwgt_[ + 775, — | re | [gE Rise and Fall Time | tyr tge | _— ‘| — | | ms | [ctx Delay Time | tcp | Sid — | | [Data Delay Time | tap) 60 | 1997-04-07 36/49

@ LPSTB timing Mao to MAS ee > Ga >, Gc, [or tLPD2 tLPD1 Memory Address “M+2” in the LIGHT PEN REGISTER tLpD1, tLpD2 : Period of uncertainty for Refresh Memory Address. e ADF, EXS timing Bor tMAH tMaAS MAO to MAIS ax tess tESH Bs TEST CONDITIONS (Vss =OV, Vpp =5.0V + 10%, Ta= -20 to 75°C) ITEM SYMBOL TEST CONDITIONS | rain | naa | UNIT LPSTB Minimum Pulse Width [| PwiPpH [| 60 | — | ns | LPSTB Disable Time LPO tipp2 | CC —C~dTsC = Cs 20 ns MA Hold Time tmanH [| — —C~dEC = ‘| 50: [fs | LA Hold Time tan | OT = 50 Ts MA Set-up Time twas | O——~dTsC CTs | s LA Set-up Time tas [| — Si — | 60 | ns | EXS Set-up time tess | ST 20 | = os EXS Hold Time tes [ = — iT 40 « [ — J ns | 1997-04-07 3789

@ BUS timing (1) | Read sequence tec tas _1 J a je AH wwis ——_—F TH, D0 to D7 ¢ (2) | Write sequence tec Sp _| yb || _ elem G, Rw Rg (Cont. Reg) Dn bo 07 {> TEST CONDITIONS (Vsg =0V, Vpp =5.0V + 10%, Ta = -20 to 75°C) CPU read timing E Cycle Time [ee ro E 1 Pulie Width pweR [80 os | E-0 Pulse Width pwet [ot Pos [E Rise and Fall Time | ter, ter | | — | 5 ons | Address Set-up Time [tag | | — [os | Data Delay Time [tp | | 180s | Data Hold Time [toy | = Pr Address Hold Time [ign 10 Ps | [Data Access Time tpg 250 Tins CPU write timing ITEM SYMBOL TEST CONDITIONS | rain | naa | UNIT E Cycle Time [ tec | 500 | = ins [E 1 Pulse Width | PWEH J 220 | — Tos | E 0 Pulse Width PweL [OS 210 | — Ts E Rise and Fall Time | ter ter [| | TT ns | Address Set-up Time [ tas | 0 | — Ts | Data Set-up Time | tps [60 | — Tf ns | Data Hold Time | tpy | Ot | — Ys Address Hold Time [tay ft ns TOO 9-04-07 38/4

@ CG ROM +attribute RAM cpu 17779 ef TTT? address -y-+f oecoorn P 3 cro] | Fe viv [fp 5 actrbute oe ct U CE SRAM. WR LAH] 7RD O {> nest Data dO to d7 CGROM ] aces «J Lio to Lat TR Ba ee Address Attribute : CSREN tano to Mats on ‘Ss UBLNK ww oink aa E CHREN ad BMODE CYCLE (U/L) (| ye LeD wm Xo Xs KX 2 Ke KX =} osetus | | | : : H t fi t t t cuose | Hi i t t t i wawour | Xo i Xt Xt Xt Xt) H H i H H H rowoor FX Xb Xe XX 7997-04-07 30/49

@ Bit map RAM ou 17779 a ra Address Ss (+ /IORQ) a dO to d7 te} +5 WR Data WR a ae | iro LL ft E> ice SRAM Reset ] Address MAO to MAIS a saw Lat Attribute : CSREN=0 | Cod Rs RVEN=0 BCLK=0 RIW UBLNK=0 E CBLNK=0 —_ ULEN=0 RES CHREN=1 Attribute BMODE=1 cycLe (U/l) J J | ( -teo i i i H i H H H H H H H ww YEA HEHEHE} H H H H H H t H t H psemG | i i H i i H i i i t i ! Hi { ! Hi cupisp ! \\ h ' ' i i i i ' t 1997-04-07 40/49

@ CG ROM (1-character skew) cu 17779 ep EH? (+ /IORQ) id Data dO to d7 cGROM [Fe Address G wa > 7WR Data Lo to Lag a io L-| FES ICE SRAM = TL T {mex MAO to MAIS Attribute : CSREN=0 Rs RVEN=0 i BCLK=0

3 CBLNK=0

= ULEN=0 RES CHREN=1 Attribute BMODE=1 1 1 1 1 ' 1 CYCLE (U/L) J J | ( y-teo 1 1 1 Hf I H i i i i I i H ' H ' H Npeseceeeed H H i H pseTwG H H ! H ! H Hf i i ' i H i i i ' i ! ! | pecseeeaed H cupisP it 1 \\! y i i u ! Meeeeeeeed ! t i i i i i H i i H i H i i i i i ' i i i 1 t 1997-04-07 41/49

@ CG ROM (2-character skew) cpu 17779 eT ep Ss? o (+ /10RQ) Data d0 to d7 ccrom Address a awe a ae ee ae Data mo LL FES; ice SRAM iReset | ‘Address | Attribute : CSREN=0 MAO to MAIS RVEN=0 J UBLNK=0 R/W CBLNK=0 ULEN=0 E CHREN=1 TS BMODE=1 Attribute CYCLE (U/L) J J | (er LeD H H H H H H I I i I I I on eS CE Ge GHEE GaCEe 1 i H i H H H H t H osermc 1 \\ i i H i i t i ' i baeeeeeeeed ! cupise | ' a " \\ ’ : * : : Veeveeeeeeet H H t H ' H H i H H ' ' vrs KX Xt Ke XD) wre XXX KX) 1997-04-07 42/49

APPLICATION CIRCUIT-::640 x 400 (1/200 duty) LCD An application circuit for an LCD is shown overleaf. ES] _recisren name [sve [AE [ Ro. [ Horizontal Total [NRT] 52H | Refresh Memory [Ra [Horizontal Sync. Postion [Nhsp| 50H | Access Method oat\\_S\\_/S \\__ Nvsw [ Rs [Vertical Total Adjust _[Nadj | 00H | ol wan | [Rg | Vertical Displayed |vd_| FFA | sn [Ri1| Cursor End __|Neer | 07H | [Riz [Start Address (A) | — | 00H | om | [Ria [Cursor Address (FY) | — | 008 | ent [R15 [Cursor Address () | — | 00H | [R17 [tight Pen | — | — | [Rig [SCP Start Position [Nesp | 80H | [Rig [SCP End Position |Nsep | 50H | [| tco srecirication | [Rap | Display Start Postion —[Ndsp| 0H | Dot Size $A0%400 [R21 [Display End Position _[Ndep| 50H | Duty 17/200 [R22 [Additional Address (H) | — | 07H | Frame Frequency| 60 Hz [R23 [Additional Address (L)_ | — | DOH | Dot Frequency 16 MHz Character Font |8x8 Displayed Chars | 80x50 Cursor Mode Scan Line 0 to 7, Non-Blink 1997-04-07 43/49

Z Z 8 4 ol "] ] TTTTTALA $ o Ee 8 ie 8 8 . iS 2 ettees 2200 ce ven engage: wok assasass as_9 Ssaasi8 secserse —$8953_—_«S08 852338792059 TH oO yy = COT fa Al TUTTI MTs TU aN S88SEE58 | SSSSTSSS | tH} =i ba Tier reece ereceeeal BSESESEE, sfeeneusauze|™ | Lpseseas net (_— z WW z (tha ITT § 5 A "Teese" lessee ere S88S8S58| BSSEERSE| Repetet ce bese = Chott oy ER al eee | i EASRNRBRBED thm ganasges genes tet = ce | aR ER TRESS Preceerertrees de COC CLL i J TITY ta} fa Ah OA EEOTSETDY BBEISSSSSSESS| R p> A Soagsees Etereeteceetcd 2 eel i BL COC pee guns = ay te 2 x eit |] 2) wy a t 28 |_| eeggyessssassy] | | Se TERE SE 7 £ ERR ERR ERE PRES ef mo I ges tls cz aPSANDRBREE a EreeRecceecets ' in WITITIIIIIIS A) cnn ie Grsawasn g grsnesonemsenese al 2 g 4 5 2 7 3 E 5 ge bee g gees © ass 22 a 2} FA = 3 peepee i oo A - 1

8 Itt E

N N y 8 N : ee go a A s ¢ E E 1997-04-07 45/49

3 17779 DEMO SET PROGRAM VER1.00 ; SOURCE PROGRAM for TMPZ84CO0P ; 15-FEB.-1991 ; REGISTER NUMBER DEFINITION CMD —_EQU OFFFEH COMMAND REG. DAT — EQU OFFFEH ;DATA REG. ATRAM EQU 4000H ;ATTRIBUTE RAM ADDRESS DPRAM EQU 8000H ;DISPLAY RAM ADDRESS ; MAIN PROGRAM ORG 0000H START: LD SP, 3FFFH ;INIT STACPOINT LD HL, CMD ;HL <- COMMAND REG. ADDRESS LD D, 00H Lo BC, TBL ;BC <- REGISTER DATA ADDRESS LOOP1: LD (HL) ,D ;SET REGISTER NO. Lo A, (BC) LD (DAT) ,A ;SET REGISTER DATA INC BC ;INC REGISTER DATA ADDRESS INC D ;INC REGISTER NO. LD A,D cP 18H ;LAST REGISTER ? JP NZ,LOOP1 Lo HL, ATRAM ;HL <- ATTRIBUTE RAM ADDRESS LD A, 80H ;ATTRIBUTE RAM END ADDRESS LD B, 40H 3CHREN="H" Loop2: LD (HL) ,B INC HL cP H ;END ADDRESS ? JP NZ, LOOP2 LD BC, 4000 ;LOOP COUNT LD DE , DPRAM ;DE <- DISPLAY RAM ADDRESS LD HL, DISP ;HL <- DISPLAY DATA ADDRESS LDIR ;BLOCK TRANS. HALT ;END OF PROGRAM 8997-04-07 46/49

TBL: DEFB 52H, 50H, 50H, 11H, 18H, 0OH, OFFH, OFFH,50H,07H,60H,07H DEFB 00H, 00H, 00H, 00H, 00H, 00H, 80H, 50H, 00H,50H, 07H, ODOH

3 DISPLAY DATA

DISP: DEFB " 17779 (CRT/LCD CONTROLLER) " DEFB" " DEFB "1.GENERAL DESCRIPTION " DEFB " " DEFB "The 17779 is a controller LSI for a raster-scan-type CRT display " DEFB" " DEFB "and large-scale dot matrix LCD. It can be used in applications " DEFB " " DEFB "ranging from small-scale character display systems to large-scale " DEFB " " DEFB "graphic display systems. " DEFB" " DEFB "2. FEATURES " DEFB " " DEFB "-a)Refresh memory address : MAQ-MA15 " DEFB" " DEFB " b)Line scanning address : LAQ-LA4 " DEFB " " DEFB "c)Frame buffer capacity : Max 64 KBytes (character) " DEFB " " DEFB " Max 2 MBytes (graphic) " DEFB" " DEFB " d)Number of characters per line : 1-255 " DEFB " " DEFB " -e)Number of character rows : 1-255 " DEFB" " DEFB " f)Scrolling , Paging " DEFB " " DEFB =" g)Light pen " DEFB " " 1997-04-07 47/49

DEFB " h)Horizontal dots per character according to font : 5,6,7,8 " DEFB " " DEFB " {)Vertical dots per character according to font : 1 to 32 " DEFB" " DEFB " j)Data output : 1-bit output , 2-bit (odd/even) output , 4-bit output” DEFB " " DEFB "k)Various attribute functions : Underline Cursor ON/OFF " DEFB" " DEFB " Underline Cursor Blink " DEFB " " DEFB " Character ON/OFF " DEFB " " DEFB " Character Normal/Inverse " DEFB" " DEFB " Character Blink " DEFB " " DEFB " Blink Frequency Change " DEFB" " DEFB" " DEFB " END!!" END 4997-04-07 48/49

QFP100-P-1420-0.65) Unit : mm 24.8+0.3 20x02 Fa 80 51 ,

4 HONDO DOO (OOD DOORN OND OO MOOD J

be UUEGRAUGOURVAOUOUEOAOREORUOVOOORUOCEOROCOOOTRERUOU OTT f Stef Lx 50 cS =| = = == = | « = =— E= § ¢g = =o E= + & = =| =, = POTATO ECCT O ORT EOD OR aE ~ ite ADIN Fanotoancann \\ 4 loss) lbsroreroae 0: ‘YP. dz Sl nnn nnn A #3 . 3 +7 19203 Weight : 1.6g (Typ.) 1997-04-07 49/49

Product Information

T7779 specifications and overview.

Summary

CRT/LCD CONTROLLER LSI

Description

CRT/LCD CONTROLLER LSI

Source title T7779 Datasheet(PDF) - Toshiba Semiconductor

Related Parts

More parts from the same family.

Browse manufacturer