T74LS378 STMICROELECTRONICS | Alldatasheet

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STi T; SGS-THOMSON "OT (0 MICROELECTRONICS T74LS378 HEX PARALLEL D REGISTER WITH ENABLE « 8-BIT HIGH SPEED PARALLEL REGISTER — = POSITIVE EDGE-TRIGGERED D-TYPE FLIP- . ny ze FLOPS = eaGa : Le > « FULLY BUFFERED COMMON CLOCK AND re i = INPUT CLAMP DIODES LIMIT HIGH SPEED iit Ae fit, wl TERMINATION EFFECTS Y i = FULLY TTL AND CMOS COMPATIBLE ; B1 5 Di ‘ DESCRIPTION (Plastic Package) (Ceramic Package) The T74LS378 is an 6-Bit Register with a buffered : . en common enable. This device is similar to the . | Ey T74LS174, but with common Enable rather than —. Key common Master Reset. en eS? : , mi C1 PIN NAMES (Micro Package) (Plastic Chip Carrier) = ENABLE (active LOW) INPUT . ORDER CODES: | Do-Ds_—_| DATA INPUTS . T74L8378 D1“ T74L8378:C1 cp Mtl (active HIGH going edge) T74L$378 Bi == T74LS378M1.- ~~ f Qo-Qs__| TRUE OUTPUTS ! PIN CONNECTION (top view) . rn DUAL IN LINE CHIP CARRIER [je Yec fe] ; gut # foes a : E}a0 O55] OOo : 3921 2 19 ae, [}, 0, 0s “7 Co, nc] 6 tence oo . . EI oat : o,7 . BEF 02 95 fy m{}8 «Oo 2 . 9 ON 12°73 ant E]o2 93 fy OMOnM Me . g2ggg88 : [Jono cp {5 SEBS S “NC = No intemal Connection : a September 1988 : ; 14-

. 13460 Bm 2 bee ssa. E Dy Dy Dy Dy Dy Ds ore 9 cp a QoQ O2 Oy A, O54 ic-o077 rn | . 25 7 101215 Dy D o 03 D, Ds , Le] (a) (6) Cat} 3} {16} : my pp. tee tee! te] ed J oo prog, | | [tT ot tT pt yo a a a a; a, Os - tented . Veo = Pin 16 . . : GND = Pin8 0) = Pin numbers : ABSOLUTE MAXIMUM RATINGS ° | Symbol [Parameter Value | Unit | Supply Voltage _-05t07 = Input Voltage, Applied to Input : | =0sto1s |v | Output Voltage, Applied to Output | _ sostoto | ve] | th input Current, into Inputs |_ = 30t05 | ma | |__to | Output Current, into Outputs ee ee Stresses In excess of those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This isa stress rating only and functional operation of the device at these or any other conditions in excess of those indicated In the operational sections of this spéctfication Is not Impfied, Exposure to absolute maximum rating conditions for extended periods may affect davice reliability. 7 ° GUARANTEED OPERATING RANGE : - Part Numbers |__Supply Voltage _| - Temperature’ T7ALS378XX 4.75 V 5.25V O° to¥ 70°C . i XX = package type.

FUNCTIONAL DESCRIPTION ae rarest The LS378 consists of eight edge-triggered D flip- When E input is LOW, new data is entered intothe flops with individual D inputs ahd Q outputs. The register on the LOW-to-HIGH transition of CP input. Clock (CP) and Enable (E) input are common to all When the E inputis HIGH the register will retain the flip-flops. Present data independent of the CP input. TRUTH TABLE : : H ST x No charge L JT H H Crear Vatase Level . = ‘ottage Level L I L L X= Don't Care DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE [| timits Test Condition ed Vie Input HIGH Voltage Guaranteed Input HIGH Treshold Vv Voltage for All Inputs Vit Input LOW Voltage Guaranteed Input LOW Treshold Vv Voltage for All Inputs Input Clamp Diode Voltage |_| - 0.65 | - 1.8 | Voc =MIN, In = 18 mA Vou Output HIGH Voltage 27 3.4 Voc = MIN, lon = - 400 pA Vv Vin = Vin or Vi. per Truth Table Vor | Output LOW Voltage Vco = MIN, |__| 288 | 05 [tas 80m | pert rants Input HIGH Current 20 Voc = MAX, Vin = 2.7 V HA 0.1 | Voc = MAX, Vin = 7.0 V mA |_u [input ow current [|_| - 0.4 | Veo = MAX, Viv 20.4 V | | Output Short Circuit Current pe] [= | Veo = MAX, Vour = 0 V note 2) . Power Supply Current |__| 16 | 27 |Vec=maxSSSS*d ma Notes: 1. Conditions for testing, not shown in the table, are chosen to guarantee operation under “worst case" conditions. 2. Not more than one output should be shorted at atime. (*) Typical values are at Vec = 5.0 V, Ta = 25 'C. AC CHARACTERISTICS : Ty = 25°C Parameter [___ktimits Test Conditions Minimum Input Fig. 1 Clock Frequency V 50 V [| ten [Pte Qouput | a? far [re] | (Veo |_ns_| CP to Q Output a a [ns |

AC SET-UP REQUIREMENTS :Ta=25C (ie gS ne [ovo | renew Fao] soon [wt e io. “on | Min. | typ. | Max. | “ee Set-up Time, Data to Clock oe : . (HIGH or LOW) Oe : Hold Time, Data to Clock Fig. 1 a (HIGH or LOW) . fs Set-up Time, Enable to Veco =5.0V Clock (HIGH or LOW) : Hold Time, Enable to Clock Fig. 1 . bela (HIGH or LOW) . ~ AC WAVEFORMS , es mS Figure 1 : Clock to Output Delays, Clock Pulse Width, Frequency, Set-up and Hold: Times Data, Enable to Clock. a mon a Vfaay . : ; of. tw : : cP 13V . 13V: ; . tun = teuy LD. WU. tow. . teu : a 13 13V . . . scat : * The shaded areas indicate when the input is permitted to change for predictable output performance. . DEFINITION OF TERMS : HOLD-TIME (th)- is defined as the minimum: time SET-UP TIME (ts)- is defined as the minimum time _ following the clock transition from LOW.to HIGH that required for the correct logic level to be present at _the logic lecel muqt be maintained at the input in the fogic input prior to the clock transition fromLOW — Ofder to ensure ‘continued recognition.A negative - to HIGH in order to be recognized and transferred HOLD TIME indicates that the correct logic: level’ to the outputs. may be released prior to the clock transition from LOW to HIGH and still be recognized. Pee