T6K01 TOSHIBA | Alldatasheet

Document overview

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Technical content

Features

/G6c/G20Dot matrix graphic LCD column driver with display RAM /G6c/G20Display RAM capacity: 160 lines × 240 outputs = 38400 bits /G6c/G20LCD drive output: 240 /G6c/G20Interface: 8-bit MPU /G6c/G20Relation between RAM data and display RAM bit data = 1 → display ON RAM bit data = 0 → display OFF /G6c/G20Display OFF function /G6c/G20Low power consumption /G6c/G20Logic power supply: 2.7 to 3.3 V /G6c/G20LCD power supply: 8.0 to 26.0 V /G6c/G20CMOS Process /G6c/G20Package: TCP (Tape Carrier Package)

Note: The above diagram shows the pin configuration of the LSI chip; it does not show the configuration of the tape carrier package.

Pin Name Pin No. I / O Functions SEG1 to SEG240 46 to 285 Output Column driver outputs CL 10 Input Shift clock pulse FP 11 Input Display synchronous signal FR 12 Input Frame signal DB0 to DB7 13 to 20 I / O Data bus AD0 to AD12 21 to 33 Input Address bus R / W 34 Input Read / write select R / W = H → Read selected R / W = L → Write selected / CE 35 Input Chip enable Data write: Data write enabled on rising edge of / CE Data read: Data read out while / CE is at L level / DSPOF 36 Input Display off. Usually connected to VDD. / DSPOF = H: Display −on mode. (SEG1 to SEG240) are operational. / DSPOF = L: Display −off mode. (SEG1 to SEG240) are at the VSS level. / RST 37 Input Reset signal: / RST = L → Reset state DIR 38 Input Data direction select / TEST1, 2 8, 9 Input /G20 Test pin. Usually connected to VDD VDD, VSS 7, 39 ― Power supply VCCL, VCCR VLC0L, VLC0R VLC2L, VLC2R VLC3L, VLC3R VLC5L, VLC5R HVSSL, HVSSR 1, 45 2, 44 3, 43 4, 42 5, 41 6, 40 ― Power supply for LCD drive

  • RAM cell The RAM capacity is 160 lines × 240 outputs for a total of 38400 bits.
  • DIR This circuit changes the data flow direction and page selection sequence.
  • Address decoder This decoder selects one RAM address for read / write operation.
  • 8-bit counter + decoder The decoder selects one RAM cell from the 160 address lines for display operation.
  • Latch The data is latched from the display RAM on the falling edge of CL.
  • Column driver circuit and LCD voltage generation circuit The T6K01 has 240 column drivers and four different LCD drive output voltage levels. The display data from the latch circuit and the M signal determine which of the four LCD drive voltages is selected. This circuit is shown in the following diagram. Relation Between FR, Data Input and Output Level / DSPOF FR Input Data (RAM Data) Output Level L * * V SS / VLC5 H L L V LC3 H L H V SS / VLC5 H H L V LC2 H H H VLC0 *: INVALID
  • The relation between DIR and the memory map (1) DIR = H

(2) DIR = L

Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rating Unit Supply Voltage (1) V DD (Note 2) −0.3 to 6.5 V Supply Voltage (2) (Note 1, 2) −0.3 to 28.0/G20 V Input Voltage VIN (Note 2, 3) −0.3 to VDD +0.3 V Operating Temperature T opr −20 to 75 °C Storage Temperature T stg −55 to 125 °C Note 1: V CCL, VCCR, VLC0L, VLC0R, VLC2L, VLC2R, VLC3L, VLC3R, VLC5L and VLC5R Note 2: Referenced to V SS, HVSSL and HVSSR Note 3: Applies to all data bus and I / O pins. Note 4: Ensure that the following condition is always maintained. V CCL / R ≥ VLC0L / R ≥ VLC2L / R ≥ VLC3L / R ≥ V LC5L / R ≥ HVSSL / R

Electrical Characteristics

(Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V ± 10%, VCCL / R = 23.0 V ± 10%, Ta = −20 to 75°C) Item Symbol Test Circuit Test Condition Min Typ. Max Unit Pin Name Operating Supply (1) V DD ― ― 2.7 ― 3.3 V V DD Operating Supply (2) V CC ― ― 8.0 ― 26.0 V V CCL, VCCR H Level V IH ― ― 0.7 VDD ― V DD V Input Voltage L Level V IL ― ― 0 ― 0.3 VDD V DB0 to DB7 AD0 to AD7, / RST, / DSPOF, / CE, R / W, D / I, CL, FP, FR, DIR, / TEST H Level V OH ― I OH = −400 µA VDD −0.4 ― V DD V Output Voltage L Level V OL ― I OL = 400 µA V SS ― 0.4 V DB0 to DB7 Column Driver Output Resistance Rcol ― Load current = ±100 µA (Note 4) ― ―/G20 3.0 k Ω SEG1 to SEG160 Input Leakage I IL ― V IN = VDD to VSS −1/G20 ―/G20 1 µA DB0 to DB7 AD0 to AD7, / RST, / DSPOF, / CE, R / W, D / I, CL, FP, FR, DIR, / TEST Operating Freq. f CL ― ― 10 ―/G20 50 kHz C L Current Consumption (1) ISS1 ― (Note 1) ―/G20 410 520 µA /G20 VSS, HVSSL, HVSSR, VLC5L, VLC5R Current Consumption (2) I SS2 ― (Note 2) ―/G20 45 65 µA /G20 VSS, HVSSL, HVSSR, VLC5L, VLC5R Current Consumption (3) I SS3 ― (Note 3) −1/G20 ―/G20 1 µA /G20 VSS, HVSSL, HVSSR, VLC5L, VLC5R Note 1: Current consumption while internal data receiver is operating VDD = 3.0 V ±10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, 1 / 160 duty, no load, fFP = 70 Hz, f / CE = 5 MHz Note 2: Current consumption while internal data receiver is sleeping VDD = 3.0 V ±10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, 1 / 160 duty, no load, fFP = 70 Hz, f / CE = 0 Hz Note 3: Standby current consumption VDD = 3.0 V ±10%, VCCL / R = 23.0 V, Ta = 25°C, no load, fFP = 0 Hz, f / CE = 0 Hz Note 4: V CCL / R = VLC0L / R = 23.0 V, VLC2L / R = VCC × 11 / 13, VLC3L / R = VCC × 2 / 13, HVSSL / R = VLC5L / R = 0 V

AC Characteristics (1) Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V ±10%, Ta = −20 to 75°C) Item Symbol Min Max Unit Enable Cycle Time t cycE 250 ― ns Enable Pulse Width PWEH 160 ― ns Enable Rise / Fall Time t Er, tEf ― 20 ns Address Set-up Time t AS 0 ― ns Address Hold Time t AH 10 ― ns Data Set-up Time t DS 100 ― ns Data Hold Time t DHW 20 ― ns Data Delay Time t DD (Note) ― 180 ns /G20 Data Hold Time t DHR (Note) 20 ― ns /G20 Note: With load circuit connected Load Circuit

AC Characteristics (2) display data Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = −20 to 75°C) Item Symbol Pin Name Min Max Unit CL Pulse Width H t CWH CL 500 ― ns CL Pulse Width L t CWL CL 500 ― ns CL Rise / Fall Time t r, tf CL ― 50 ns FP Set-up Time t FSU FP 100 ― ns FP Hold Time t FHD FP 100 ― ns AC Characteristics (3) Item Symbol Condition Min Max Unit CL-to-FP-margin time t CF 20 ― ns FP-to-CL-margin time t FC 0 ― ns

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