T6C03

T6C03 TOSHIBA | Alldatasheet

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Technical content

Features

/G6c/G20Display duty application : to 1 / 480 /G6c/G20LCD drive signal : 160 /G6c/G20Data transfer : Column: 4 / 8 −bit bidirectional Row: Single / Dual bidirectional /G6c/G20Operating frequency : 8 MHz (V DD = 5 V ± 10%) /G6c/G20LCD drive voltage : 14 to 42 V /G6c/G20Power supply voltage : 2.7 to 5.5 V /G6c/G20Operating temperature : −20 to 75°C /G6c/G20LCD drive output resistance : 1.3 kΩ (max) (20 V, 1 / 13 bias) /G6c/G20Display−off function : When / DSPOF is L, all LCD drive outputs (O1 to O160) remain at the V5 level. /G6c/G20Low power consumption : Cascade connection and auto enable transfer functions are available. /G6c/G20EI / LP input : EI / LP input enables LSI operation. Connect EIO1 / 2 from the 1st LSI to L. /Gb7/G20TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibi lity of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, a nd to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury o r damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handlin g Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. /Gb7/G20The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energ y control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion cont rol instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this docume nt shall be made at the customer’s own risk. /Gb7/G20Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film . Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. /Gb7/G20Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and du ring inspection must be taken into account. /Gb7/G20The products described in this document are subject to the foreign exchange and foreign trade laws. /Gb7/G20The information contained herein is presented only as a guide for the applications of our products. No responsibility is assume d by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from i ts use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. /Gb7/G20The information contained herein is subject to change without notice. 000707EBE1

Note: The above diagram shows the pin configuration of the LSI Chip, not that of the tape carrier package.

Pin Name I / O Functions Level O1 to O160 Output Output for LCD drive signal V 0 to V5 (Column mode) Input / output for enable signal DIR selects In or Out. Connect EIO (IN) of 1st LSI to L. For a cascade connection, connect EIO (OUT) to EIO (IN) of next LSI. EIO1, EIO2 I / O (Row mode) Input / output for shift data DIR = L : EIO1 is output, EIO2 is input DIR = H : EIO1 is input, EIO2 is output (Column mode) Input for data signal DI1 to DI8 Input (Row mode) DI1 to DI7: Fix to H or L, DI8: when DF = H, use as DIN DIR Input (Direction) Input for data flow direction select / DSPOF Input (Display off) / DSPOF = L : Display−off mode, (O1 to O160) remain at the V5 level / DSPOF = H : Display−on mode, (O1 to O160) are operational. DF Input (Data format) Input for data bit select (Latch pulse) Display data is latched on falling edges of LP. When EIO (IN) = L, SCP · LP = H enables the 1st LSI. LP Input (Row mode) Input for shift clock pulse FR Input (Frame) Input for frame signal (Column mode) Input for shift clock pulse SCP Input (Row mode) Fix to H or L TEST Input (TEST) Fix to L S / C Input Input for mode select: H = Column mode, L = Row mode VDD to VSS

Pin Name I / O Functions Level VDD ―/G20 Power supply for internal logic (+5.0 V) VSS ― Power supply for internal logic (0 V) V5L · R ― Power supply for LCD drive circuit V3 / 4L · R ― Power supply for LCD drive circuit V2 / 1L · R ― Power supply for LCD drive circuit V0L · R ― Power supply for LCD drive circuit VCCL · R, VSSL · R ― Power supply for LCD drive circuit Relation Between FR, Data Input and Output Level F R Data Input / Dspof Output Level (Column Mode) Output Level (Row Mode) L L H V 3 V4 L H H V 5 V0 H L H V 2 V1 H H H V 0 V5 (Note) (Note) L V 5 V 5 Note: Don’t Care

Enable Pin Input Data Line and Output Buffers DIR DF BIT Mode EIO1 EIO2 (Note 1) DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 L O160 O159 O158 O157 ― ― ― ― H IN OUT F O4 O3 O2 O1 ― ― ― ― L O1 O2 O3 O4 ― ― ― ― L L 4 −BIT OUT IN F O157 O158 O159 O160 ― ― ― ― L O160 O159 O158 O157 O156 O155 O154 O153 H IN OUT F O8 O7 O6 O5 O4 O3 O2 O1 L O1 O2 O3 O4 O5 O6 O7 O8 L H 8 −BIT OUT IN F O153 O154 O155 O156 O157 O158 O159 O160 Note 1: L: Last Data F: First Data Row Mode Data Input Terminals DIR DF Data Flow EIO1 EIO2 DIN L O160 → O1 OUT IN ―/G20 H L O1 → O160 IN OUT ― L O160 → O81 O80 → O1 OUT IN IN H H O1 → O80 O81 → O160 IN OUT IN

Timing Diagram (Column mode)

Timing Diagram (Row mode)

(Ensure that the following conditions are maintained, VCC ≥ V0 ≥ V2 ≥ V3 ≥ V5 ≥ VSS) Item Symbol Pin Name Rating Unit Supply Voltage (1) V DD V DD −0.3 to 7.0 V Supply Voltage (2) V CC V CCL / R −0.3 to 45.0/G20 V Supply Voltage (3) V 0, V2 V 0L / R V2L / R −0.3 to VCC + 0.3 V Supply Voltage (4) V 3, V5 V 3L / R V5L / R −0.3 to 7.0 V Input Voltage V IN (Note 2) −0.3 to VDD + 0.3 V Operating Temperature T opr ―/G20 −20 to 75 °C Storage Temperature T stg ― −40 to 125 °C Note 2: SCP, FR, LP, DIR, DF, S / C, EIO1, EIO2, DI1 to 8, / DSPOF, TEST

Electrical Characteristics

(Unless otherwise noted, VSS = 0 V, VDD = 2.7 to 5.5 V, Ta = −20 to 75°C) Item Symbol Test Circuit Test Condition Min Typ. Max Unit Pin Name Supply Voltage 1 V DD ― ― 2.7 5.0 5.5 V DD Supply Voltage 2 V CC ― ― 14 ― 42 V CCL / R H Level V IH ― 0.8 VDD ― V DD Input Voltage L Level V IL ― (Note 2) 0 ― 0.2 VDD SCP, FR, LP, DIR, DF, S / C, EIO1, EIO2, DI1 to 8, / DSPOF, TEST H Level V OH ― I OH = − 0.5 mA VDD − 0.5 ― V DD Output Voltage L Level V OL ― I OL = 0.5 mA 0 ― 0.5 V EIO1, EIO2 H Level R OH ― V OUT = V0 − 0.5 V (Note 3) ― 0.6 1.3 ― V OUT = V2 ± 0.5 V (Note 3) ― 0.6 1.3 M Level R OM ― V OUT = V3 ± 0.5 V (Note 3) ― 0.6 1.3 Output Resistance L Level R OL ― V OUT = V5 + 0.5 V (Note 3) ― 0.6 1.3 kΩ O1 to O160 Current Consumption (Note 4) IDD ―/G20 VDD = 5.5 V VCC = 42 V fLP = 33 kHz fFR = 8.3 kHz fscp = 8.0 MHz Input Data: every bit inverted V IH = 5.5 V, VIL = 0 V ― ― 4.0 mA V DD Note 3: V CC = 20 V, 1 / 13 bias Note 4: Current consumption while the internal data receiver is operating

Test Conditions (1) (VSS = 0 V, VDD = 5 V ± 10%, VCC = 14 to 42 V, Ta = − 20 to 75°C) Item Symbol Test Condition Min Max Unit Clock Cycle t C ―/G20 125 ―/G20 ns SCP Pulse Width t CWH, tCWL ―/G20 50 ―/G20 ns Data Set−Up Time t DSU ―/G20 50 ―/G20 ns Data Hold Time t DHD ―/G20 50 ―/G20 ns SCP Rise / Fall Time t r, tf ―/G20 ―/G20 (Note 5) ns LP Rise Time t LRP ―/G20 50 ―/G20 ns LP Fall Time t LFP ―/G20 50 ―/G20 ns LP Pulse Width t LW ―/G20 45 ―/G20 ns SCP−to−LP Delay Time t SL ―/G20 40 ―/G20 ns LP−to−SCP Delay Time t LS ―/G20 40 ―/G20 ns EIO IN Fall Time t EIFP ―/G20 40 ―/G20 ns EIO IN Pulse Width t EIW ―/G20 40 ―/G20 ns SCP−to−EIO Delay Time t SE ―/G20 20 ―/G20 ns EIO−OUT Delay Time t EOD (Note 6) ―/G20 80 ns Note 5: t r, tf ≤ (tC − tCWH − tCWL) / 2 and tr, tf ≤ 50 ns Note 6: C L = 30 pF

Test Conditions (2) (VSS = 0 V, VDD = 2.7 to 4.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C) Item Symbol Test Condition Min Max Unit Clock Cycle t C ―/G20 500 ―/G20 ns SCP Pulse Width t CWH, tCWL ―/G20 240 ―/G20 ns Data Set−Up Time t DSU ―/G20 240 ―/G20 ns Data Hold Time t DHD ―/G20 240 ―/G20 ns SCP Rise / Fall Time t r, tf ―/G20 ― (Note 7) ns LP Rise Time t LRP ―/G20 220 ―/G20 ns LP Fall Time t LFP ―/G20 240 ―/G20 ns LP Pulse Width t LW ―/G20 240 ―/G20 ns SCP−to−LP Delay Time t SL ―/G20 70 ―/G20 ns LP−to−SCP Delay Time t LS ―/G20 100 ―/G20 ns EIO IN Fall Time t EIFP ―/G20 240 ―/G20 ns EIO IN Pulse Width t EIW ―/G20 240 ―/G20 ns SCP−to−EIO Delay Time t SE ―/G20 50 ―/G20 ns EIO−OUT Delay Time t EOD (Note 8) ―/G20 260 ns Note 7: t r, tf ≤ (tC − tCWH − tCWL) / 2 and tr, tf ≤ 50 ns Note 8: C L = 30 pF

Test Conditions (1) (VSS = 0 V, VDD = 4.5 to 5.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C) Item Symbol Test Condition Min Max Unit LP Pulse Width H t CWH LP 30 ―/G20 ns LP Pulse Width L t CWL LP 195 ―/G20 ns SCP Rise / Fall Time t r, tf LP, FR, EIO1, EIO2, DIN ― 20 ns Data Set−up Time t DSU EIO1, EIO2, DIN 80 ―/G20 ns Data Hold Time t DHD EIO1, EIO2, DIN 0 ―/G20 ns EIO−OUT Delay Time A (Note 9) t pdA EIO1, EIO2, DIN 5 ―/G20 ns EIO−OUT Delay Time A (Note 9) t pdB EIO1, EIO2, DIN ―/G20 150 ns LCD Drive Data Delat Time (Note 10) t PHL O1 to O120 ―/G20 800 ns Test Conditions (2) (VSS = 0 V, VDD = 2.7 to 5.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C) Item Symbol Test Condition Min Max Unit LP Pulse Width H t CWH LP 100 ―/G20 ns LP Pulse Width L t CWL LP 400 ―/G20 ns SCP Rise / Fall Time t r, tf LP, FR, EIO1, EIO2, DIN ― 20 ns Data Set−up Time t DSU EIO1, EIO2, DIN 100 ―/G20 ns Data Hold Time t DHD EIO1, EIO2, DIN 0 ―/G20 ns EIO−OUT Delay Time A (Note 9) t pdA EIO1, EIO2, DIN 5 ―/G20 ns EIO−OUT Delay Time A (Note 9) t pdB EIO1, EIO2, DIN ―/G20 400 ns LCD Drive Data Delat Time (Note 10) t PHL O1 to O120 ―/G20 1000 ns Note 9: C L = 30 pF Note 10: C L = 20 pF Note: Insert the bypass capacitor (0.1 µF) between V DD and VSS, to decrease power supply noise. Place the bypass capacitor as close to the LSI as possible.