T6A40

T6A40 TOSHIBA | Alldatasheet

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TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC ROW DRIVER FOR A DOT MATRIX LCD The T6A40 is a 68-channel-output row driver for an STN dot matrix LCD. The T6A40 features -28V LCD drive voltage. The T6A40 is able to drive LCD panels with a duty ratio of up to 1/240. It is recommended for use with the T6A39/T6A39A. >, FEATURES IN ge © Display duty application : to 1/240 ah ONT < qu uu © LCD drive signal : 68 RAM © Data transfer : 1-bit bidirectional ®D 068<-01 QFP92-P-1818-0.70B @ 06801 @ 01034, 035 <— 068 @ LCD drive voltage : -8 to -28V (max -30V) —— © Operating voltage : 4.5 to 5.5V a XN @ Operating temperature : -20 to 75°C >. @ LCD drive output resistance : 1.5kQ (max) (12.8V, 1/9 bias) oN - ag @ LCD drive output timing : Change on falling edge of LP QP sere BLOCK DIAGRAM TQFP100-P-1414-0.50 068 to 01 Weight { QFP92-P-1818-0.70B : 1.45g (Typ.) TQFP100-P-1414-0.50 : 0.45g (Typ.) Bidirectional Bidirectional directional Polarity Control Control Control yt —_ DIO2 Vpp Vss DUAL DIR -LP_ TSW IOI LP FR Viva V5 9809 10EBA2 ©@ TOSHIBA is continually working to improve the quality and the reliability of its products, Nevertheless, semiconductor devices in general can malfunction or ‘all due to their inherent electrical sensivty and vulnerability to physical stress. ts the responsibilty of the buyer, when tiizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted By implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others @ The information contained herein is subject to change without notice. 1999-09-29 1/9

QFP92-P-1818-0.70B SSS TTT RR RRR BARR RRARARAS SSSSSSSSSESSEFSSESSESSSESS 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 046 70 46 fl 023 oe 72 44 021 ong 73 | 43 fl 020 050 74 22 fl o19 ost 7s aff on

082 B76 ' 40 ff o17

055 Hs 37h o1

056 Heo 36 ff 013

(CHIP TOP VIEW)

057 Heo 3a ff o12

058 Has 33 ff om

060 Has 31 09

061 Bes Hl 30 ff o8

os2 Haz 29 [07

063 Hes 20 06

064 Hes 1 PININDEX ‘ 27 os

065 Ho 26 04

12.3 4 5 6 7 & 9 10:11 12 13 14 15 16 17 18 19 20 21 22 23 PSSELELE LEE RSS SLE LEE ES a a a 9999-09-29 29

TQFP100-P-1414-0.50 SST RRR YVR RRERRAR RAR $635656855558222555583555555 75 7A 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

046 B76 50 023

o49 B79 | 47 020 os0 so 46 O19 051 81 45 O18 os2 82 ' 44 O17 os3 ss 43 O16 os4 sa | 42 O15 oss B85 a o14 ose Mas | 40 013 nc 87 T6A40 39 NC nc Bee (CHIP TOP VIEW) s—i—<is~—sSC nc 89 37 NC 057 90 | 36 O12 oss B91 35 on oso B92 | 34 010

060 B93 33 09

062 B95 1 31 o7

063 B96 | 30 06

064 B97 29 os

1 Pin INDEX

066 B99 a | 27 03

067 100 | 26 02 12.3.4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ZSSEVPE SSeS sys EsSSoysyyss a a 3 1999-09-29 3/9

5 i Vp> O1 to O68 | Output | Output for LCD drive signal to Vs Input/output for shift data (Shift Clock Pulse) Input for shift clock pulse (Frame) Input for frame signal DUAL Input (Dual Mode) . . . Terminal for dual input mode or single input mode select Vpp to (Direction) Ve ss | ow | Input Input for data flow direction select (Terminal Switch) TSW Input | When tied to Vsg : (O1 to 068) output on the rising edge of LP When tied to Vpp : (O01 to 068) output on the falling edge of LP | _Vpp __|_— __ [Power supply for internal logic (5 V) | _Vss___| _— _ [Power supply for internal logic (0 V) pow | — | Power supply for LCD drive circuit | Va | — [Power supply for LCD drive circuit [| vs ___| — [Power supply for LCD drive circuit RELATION BETWEEN FR, DATA INPUT AND OUTPUT LEVEL DATA INPUT (DI01, DIO2) OUTPUT LEVEL a ee PV DATA INPUT FORMAT DUAL DATA FLOW DATA INPUT | dior io2 v vy 01> 034 DD DD 068 > 035 1999-09-29 4/9

(Ensure that the following conditions are maintained, Vpp = V1 2 V4 2 V5, Vss = 0V) ITEM SYMBOL PIN NAME RATING UNIT Supply Vortage 1 =03 1070 Supply Voltage 2 Vpp=300 to Vpp + 03 Supply Voltage 3 Vpp=30.0 to Vpp + 0.3 Supply Voltage 4 Vpp=30.0 to Vpp +03 input Voltage =03 to Vpp +03 Operating Temperature | Topr | — | =20 t0 75 Storage Temperature | Tag | _— | =55 to 125 (*1) : FR, DIR, DIO1, DIO2, DUAL, TSW, LP

ELECTRICAL CHARACTERISTICS

TEST CONDITIONS (unless otherwise noted, Vss = OV, Vpp = 4.5V to 5.5V, Vs = (Vpp - 23) V + 10%, Ta = -20 to 75°C TEST ITEM SYMBOL] CIR- TEST CONDITION TYP. | MAX | UNIT CUIT Supply Voltage

1 VpD v Vpp

2 Vs = 28 -80| ¥ Vs

Vpp FR, DIR, DIO1 H Level} V, *2) V * * 9 yo = P| LP, TSW = VoD oer oiecoeme (= [0 « [oo ° iol = 0SmA [= [= [05] oun Vout = Vop-0sv (3) | — |—| 12] Rese |m tevell Rom | _ [Your=Vitosv 3) [| = [= T1210 |g. i one Resis LRom | ~ |vour=Vatosv 3) | — | —| 12 Vpp = 5.5V Input Data : c V5 = -22.5V fplo = 71 Hz urrent ff = 35.5Hz (Duty : 1/100) Consumption 'ss fLp = 7.1kHz Input Voltage : 2.0 HA Vss 01 to 068 : H = Vpp no load L=Vss (*3) (*3) : Vpp = 5.0V, Vs = -7.8V, V1 = Vpp - 1/9 (Vpp - Vs), Va = Vpp - 8/9 (Vpp - Vs) 1999-09-29 6/9

town tow. te 90% k| e 10% tt tosu touo DATA IN toda, DATA OUT tod TEST CONDITIONS (Vss = OV, Vpp = 4.5 to 5.5V, V5 = (Vpp - 23) V + 10%, Ta = -20 to 75°C) SCP Pulse Width H [town [Pi | SCP Pulse Width L 2 a Input Rise /Fall Time LP, FR, DIO1, DIO2 | — | so | ns | Data Set-up Time DION, BIO2 [30 | — | ns Output Data Delay Time A pior, pion a | 80 | — | ns _| Output Data Delay Time pior, pion — | 1 | ys | (*4) : CL = 10 pF NOTE Insert the bypass capacitor (0.1 uF) between Vpp and Vsg to decrease power supply noise. Place the bypass capacitor as close to the LSI as possible. 1999-09-29 7/9

QFP92-P-1818-0.70B Unit : mm 69 | 47 ONOHOnOgengueggangqenge petal PPE ELE DTT.

70 CI] | 146

== = = | = == | = oe | ES al == | Ss | oo | ES == | = =| © | ==

92 CI) 1 I 24

N } Coo go ee sone UUUUUUUU 1 23 : 035+ 0.1514 B) AB 3 g Am __|_ JIMA os=0s Weight : 1.45g (Typ.) “<< 4999-09-29 8/9

TOQFP100-P-1414-0.50 Unit : mm 16.040.2 14.0+0.1 75 51 a BARBARRBRRRRARRRERRHABRAE I 2 76 Y= 50

100 SO FD 26

1.0TYP. 0.2240.08 rer oE ay g z —,-& FAN) & 15.0#0.2 br} ry a g oat ° > s osto.2| [|6 1,040.2 Weight : 0.45g (Typ.) 1999-09-29 9/9