T6A36S

T6A36S TOSHIBA | Alldatasheet

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TOSHIBA T6A36S,JT6A36X-AS TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T6A36S, JT6A36X-AS i T6A36S, JT6A36X-AS CMOS 1 CHIP LSI FOR LCD ELECTRONIC CALCULATOR The T6A36S, JT6A36X-AS is a 1 chip microcomputer for 8- digits 1-memory electronic calculator. T6A36S, JT6A36X-AS can drive the liquid crystal display (LCD) . Single power supply operation, low power ——wN consumption make it suitable for single battery operated < pocketable calculator. Ly _ < AAW

FEATURES

© 8 digits of data and one symbol digit for calculator. © Algebraic calculati 7 LQFP60-P-1414-0.80 gebraic calculation mode. Weight : 0.669 (Typ) @ Punctuation. @ Standard 4 functions(+, -, x, +), mark up percent with automatic add-On/discount, automatic constant calculations, chain calculations, memory calculations with memory overflow protection. @ Internal keyboard decoding and denouncing. © Complementary output buffer for direct driving of liquid crystal display (LCD : FEM type -3.0V, 1/2 bias, 1/3 duty). @ Single power supply (-1.5V typ.) . ®@ Quad in line flat package (60 PIN) . @ Very low power consumption (3.0W typ. at wait) . © Very wide range of operating voltage (Vss = - 1.2~ - 2.0V). @ Automatic power off (A time for about 7 min.) . 980910EBA1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. Ste products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-12-01 1/32

TOSHIBA T6A36S,JT6A36X-AS SYSTEM BLOCK DIAGRAM Battery Type

46 Ca Bg Ag C7 87 A7 CG BG AG C5 B5 As Ca Bq Aq |

Ag he} 41} 55 83 2 Pb bed Fr 42) 10 © 21810 8, 8 C10 Az os! q 4 Yoo T6A36S, JT6A36X-AS Yoo os2 (TOP view) 5 TS2, AY Bh Cy (+) os3 22 el-) coma BY Visco com2 H8 24 nc com H m ANC TS3 RESET Ky 7 NC TS4Vss1 TST Kg _K7_ Ke Ks Ka K3_K2 NC _NC RSReee Cages . [= [os [oo | sr] + |e) | > | - [+ |> | [of [=f e [> [x te [NOTE] Vpp -"" OFF MODE DISABLE 1s4{¥pP “++: OFF MODE ENABLE Rkey<20kQ (-1.2V) 1998-12-01 2/32

TOSHIBA T6A36S,JT6A36X-AS Dual Type F Ca Bg Ag C7 By Az CE BG AG C5 BS AS Ca Bq Ag ul Ag be} 8 89 83 8 BY cg 43 8 2] aro a Bio 82> C10 A2d os! cs) mbes T6A36S, JT6A36X-AS Yop ° (ToP view a Sh cy (+) os} - 1) c>(-) coma H2 BY sso com2 H8 NC comM1 SOc ‘TS3 RESET od NC TS4Vss1TS1 Kg Ky Kg Ks Kq K3 Ko NC NC Se} faa ONn/ac 7 [+ [is | [me fee [ett om | [= fos foo [ser | s [ aA C1 =C2=0.1 uF - * v oI [=] > [> Lx [so [NOTE] Vpp “"" OFF MODE DISABLE 1s4{¥pP “++: OFF MODE ENABLE RkeyS 20k (-1.2V) 1998-12-01 3/32

TOSHIBA T6A36S,JT6A36X-AS Solar Type F Ce Ba Ag C7 87 A7 Ce 8G AG C5 BS As Ca Bg Ag ul Ag G al °2 ed Fe = Cg A;— 2 aro a 810 7 C10 a2 ost cs) afve0 T6A36S, JT6A36X-AS Yoo ° (ToP view a Sh cy (+) os} - 1 c2(-) coma [12 8) Vcso come P8 NC comM1 anc ‘TS3 RESET od NC TS4Vss1 TS! Kg Ky Ke Ks Kq K3 Kz NC NC | (Ue 4 ame TL [= fe | foe [Pe fest [= [os [oo | omer | + [GBI px fe fe fm [eH C1 c2=0.1 uF [= |e fe L+ [> [NOTE] Vpp --": OFF MODE DISABLE 1s4{¥pP “++: OFF MODE ENABLE Rkey= 20kQ (-1.2V) 1998-12-01 4/32

TOSHIBA T6A36S,JT6A36X-AS CONNECTION OF LCD SEGMENT SHIFT +TAX -TAX abe! tax Tax hi ce sahihahiihit COMMON pig aig oh@ oho gio she oo a6 pig _9to to to oto ta gto pte 868 KEY LAYOUT kg Ky Ke Ks Ka 3 ka Ky Ls fs | | st fever] ta om | pote |e feed | Pete iste le Pete fete L- [+e |e 1998-79-01 5732

TOSHIBA T6A36S,JT6A36X-AS PIN LAYOUT SSIS SLESESELSSE 45 44 43 42 41 40 39 38 37 36 35 34 33.32 31 Ag Bs 303 89 47 20 fle; co 48 78 Aro 49 o-Ps Bio B50 26 fh 82 Cio St 25 Ar ost 52 2a cy Von 53 T6A36S 33 fl voo os2 If 54 os 152 55 (Tor view) 2A cr (+) B56 20 os3 c2(-) Bs7 19 COM3 Vss2 M58 18 com2 Nc 59 17 COM1 ne 60 16K 123-45 67 8 9 101112131415 2B RRR Ree eesle ee SPECIFICATION OF CALCULATOR Operational Features (1) 8 digits of data and one symbol digit. (2) Algebraic mode. (3) Full floating point. (4) Standard 4 functions +, -, x, =. (5) | Memory calculation and memory hold. (6) TAX calculation. (7) | Percent with automatic add-on and discount. (8) | Constant calculation (Automatic constant) . (9) Chain calculation. (10) Leading zero suppression. (11) Trailing zero suppression. (12) Square root. (13) Change sign. 1998-12-01 6/32

TOSHIBA T6A36S,JT6A36X-AS Capacity of Calculation (1) Numeral entry 8 digits (2) Addition / Subtraction 8 digits + (-)8 digits=8 digits (3) Multiplication / Division 8 digits x (+) 8 digits=8 digits (4) | Memory calculation 8 digits + (-)8 digits=8 digits Display Font M ea 7 U1 "c en fn an ErlLido'ittu tll tu, Arithmetic Operations 1. Addition Key Op. Display A A A B B A+B Cc Cc E] A+B+C D D D E E D+E E] D+E 2. Subtraction a) A A Al A B B E] A-B Cc Cc E] A-B-C El A-B-C 9998-12-01 7382

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display D D El A-B-C+D = - (A-B-C+D) 3. Multiplication (1) A A A B B E] AB AB Cc Cc El AB+C @ E 0. A A B B E] -AB 4. Division (1) A A El A B B E] AIB @ E 0. A A. E] -A B B E] -A/B 9998-12-01 8/32

TOSHIBA T6A36S,JT6A36X-AS 5. Power calculation Key Op. Display a1) A A A E] a E] a (2) A A E] A E] 1/A E] 1/ a2 8g E 0. A A E] a El =a @ El 0. A A E] -A E] -1/A E] 1/ a2 (5) A A A E] a a E] at 6. Mixed calculation a1) A A A B B AB c c 8998-12-01 9732

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display El AB+C D D Sl AB +C E E el A. +C 7. Constant calculation (1) A A A B B [=] AB Cc Cc E] AC @ E 0. A A B B E] -AB Cc Cc E] -AC (3) A A E] A B B E] AIB c c E] c/B D D D E] D 8998-12-01 10732

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display (4) A A A B B E] A+B c c E] C+B (5) A A | A B B E] A-B c c E] c-B (6) A A A B B E] AB c c c D D E] cD E E E] CE Ce F F E] CEF G G E] G H H E] G/H 9998-12-01 11732

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display ] ] E] W/H (7) A A A B B A:B/100 c c A-C/100 D D E] D E E 100-D/E F F 100-F/E 8. Mark-up/ Discount calculator (1) A A A B B AB [=] A+AB (2) A A A B B | AB E] A-AB (3) A A A B B A:B/100 9998-12-01 12/82

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display A-B/ 100 E] A+A:B/100 (4) A A A B B A:B/100 | A:B/100 E] A-A:B/100 (5) A A A B B A+A:B/100 (6) A A | A B B A-A:B/100 9. Memory calculation Key Op. Display Memory A A 0. A(M) A B B(M) A B(M) A+B c c(M) A+B =] c(M) A+B-C D D(M) A+B-C A+B-C(M) A+B-C A+B-C 0. (2) A A 0. A 0. 8998-12-01 13/32

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display Memory B B 0. A+B(M) A+B A+B(M) A+B A+B(M) 2(A+B) c c(M) 2 (A+B) [M=] c(M) 2(A+B) -C (3) A A 0. A 0. B B 0. AB (M) AB c c(M) AB c(M) AB D D(M) AB M-] C:D (M) AB-CD A:B -C:D (M) AB-CD [M=] AB-CD 0. (4) A A 0. A 0. B B 0. E] AB 0. c c 0. c(M) c E] A-C (M) c D D(M) c M-] D(M) c-D ES] A-D (M) c-D (5) A A 0. A(M) A B B(M) A 9998-12-01 14732

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display Memory B(M) A+B A+B(M) A+B A+B(M) A+B A+B(M) A+B (A+B)? (M) A+B c c(M) A+B E] (A+B)? +C(M) A+B (6) 1.0000001 1.0000001 0. 1.000001 (M) 1,0000001 99999999 99999999. (M) 1.000001 0. (M) 1.000001 0.(M) 1,0000001 1.0000001 (M) 1,0000001 10.Square root (1) A A Va B B (2) A A A B B VE E] AVE (3) A A A VK B B E] AB @ E& 0. A A 8998-12-01 15/32

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display Memory E] -A VAC) (5) A A 0. A(M) A A(M) A Ea] A(M) A B B(M) A -B(M) A vB (M) A 9. (M) A 11.Percentage calculation (1) A A A B B A-B/100 c c A-C/100 D D A:D/100 (2) A A A B B B c c c (3) A A | A B B A-A:B/100 8998-12-01 16/32

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display Memory | A-A:B/100 A-A:B/100 c c 12.Key correction (1) A A 0. A 0. E] A 0. | A 0. A 0. VA 0. A+VA(M) AsV - (A+VA) (M) A+Va A+/A(M) A+VA A+ A(M) 0. B B 0. B 0. | B 0. B 0. E] B 0. E] 1/B 0. 13.Others (1) A A A E] A (2) A A A E] A E] 1/A 8998-12-01 17782

TOSHIBA T6A36S,JT6A36X-AS Key Op. Display Memory (3) A A E] A A E] A (4) A A A E] A E] -A (5) A A El A E] A E] -A (6) A A A B B E] B (7) A A A B B Cc Cc E] AC 1898-12-01 18/32

TOSHIBA. CGA 36S, JTEA3EX-AS 14.TAX Calculation Key Op. Display a) A A A 2) 0. 3) B 8 B(1+A/100) B-A/ 100 B(1+A/100) B-A/ 100 (4) 8 B/(1+A/100) B-B/(1+A/100) B/(1+A/100) B-B/(1+A/100) mms TDOT TORT

TOSHIBA CT6A36S,JTEABEX-AS MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply Voltage Vss1 +0.3~ -2.2 Input Voltage +0.3~Vpp1 - 0.3 Operating Temperature +0.0~40 ELECTRICAL CHARACTERISTICS (Vss1 = - 1.5V£0.2V, Vog7 = -3.0V+4.0V, Vpp =0V, Ta=25°C) TEST PIN PARAMETER SYMBOL | ciR- TEST CONDITION Typ. | MAX. | UNIT CUIT NAME Operating Vonage | —Vesp | — | = | qe Ka~Kg, Vss1 non K2~Kg, w nan Segment, Vss2

3 Segment,

Fo) nn 1 Slower | vor |=[emmon| =| 9 | = |-22 |v | 4" Ki~Kg, Vss1 ao" Ki~K6, fous | vor |= [reser | = [of = | -02| [output 1” | Ron | — | Segment [Vour=Vopax05V [= | =| 7 [en] , [Outoutror— [Rot [= [segment [Yours -05V— [=| = | op a & [output 71” | Ron | — | common |Vout=Vop2+05V [= [= [70 Ka | § [output 0" | Rot [= [common [Voyr= -08V = = 70 | eo] RESET | — [RESET [VouT=0V [200-[ 300 [400 | [output Rot = eae WVour= 08 Supply Current 1 Vss1 = -1.5V _ (On Display) 'pp1 (No Keys) 22 HA Supply Current 2 Vgs1 = -1.2V A (Operation) (Peak OF A119V/_) a Supply Current 3 Vss1= -1.5V (off 'op3 (Off status) HA Oscillating Vssi= [on Daley | Sa] 9] 26] Frequency fosc (OP) -1.5V_ | On Operating Frame Frequency [fr | = | = [Vos = = 1.5 Wait Power off Timer | Ttimer | — | —[Vssy= = 1.5V 252 [a0] seats 1998-12-01 20/32

TOSHIBA T6A36S,JT6A36X-AS WAVEFORMS FOR DISPLAY 1(83Hz) NOTE Vop : ov a Vss2_: -3V T=4.016ms NOTE com2 — Vss2 : -3V ——— +3 Ay-COM1 —— +150 on) JJ df ov —— -15v — -3v orelon| oFF Jon] ore lon Ay-COM3 — + 15v OFF — 7 15V NOTE : f¢ =9kHz 1998-12-01 21/32

TOSHIBA T6A36S,JT6A36X-AS PAD LOCATION TABLE (um) mo name | xvont | veowr | [No name [ xvont | vromr | Paseo | ae eg 097 | [2 vesi | 62s toss | [2o[ cg | -946 | vai ‘| [s [reser | 172 | oss | [a2[ cs | -491_ | -1_| [e[ ke | 21 | toss | [33] as | -339 | -vi2 | [s7[ 87 | aes —i| =a [af ks | 738 toss 38] cy «dT Sota [ao[ es *| 7s ~| =a [aa[ co —*| toga 785 [sf ar «| en _— [as[ ost [toss [178 | [st[ tse [10a [26 1998-12-01 22/32

TOSHIBA T6A36S,JT6A36X-AS CHIP LAYOUT BoB as eevee eroeGEe fe OoOoooooooo0o000 Ky a a Vss2 com |} O OG |e coma|} O O |lq coma]} O OD flasz oss{} O O flose af} a OD hyo sj) O O |lost aff O JT6A36X-AS O |lco aj] O O |s10 s.|| O O lao o|| O D Icy a3|| O O |fe. 83]| O O la all o oO lic aaj] O oOooooogo0o0o0o00o00 PTILKSLPSTESLES Chip size 3.04 3.02 [mm] Chip thickness : 44030 [um] Substrate : Vpp PAD LAYOUT Active Element Y Bonding al Area Bum (100m) L - (138um) Scribe Line PAD Pitch 151m TT 1998-12-01 23/32

TOSHIBA T6A36S,JT6A36X-AS OUTLINE DRAWING LOFP60-P-1414-0.80 Unit : mm 18.2+0.3 14.0+0.2 45 31 ONC ON TOO CONT o & NOOO AAO A {246s Li 30 =a Er cor Fo cor fo or Fo «| o = BS slg = fr S| & car] cr +| = = Er cor = | =

60 Fr 16

1.4TYP. 0.3510.1 ba ea . —opnooooooooooooo hk =} 2 os 1,840.2 Weight : 0.66g (Typ.) 1998-12-01 24/32

TOSHIBA T6A36S,JT6A36X-AS GENERAL SPECIFICATION FOR CALCULATOR LSI BARE CHIP 1. Purpose This is to specify the quality standard for the integrated circuit produced by TOSHIBA CORPORATION (hereinafter referred as to VENDOR) to be delivered to PURCHASER. 2. Definition This specification applies only to the calculator LS! bare chip produced by VENDOR and purchased by PURCHASER and defined the general specification items. 3. Priority of specifications When the discrepancies or questions happen to the specifications and instructions provided by VENDOR, the priority shall be ranked as follows. 1) Individual specification for the calculator LSI bare chip. (Both PURCHASER and VENDOR are confirmed by the special sheets.) 2) General specifications for the calculator LSI bare chip. 3) Other related specifications and standards. 4. Characteristics To be shown in the individual specification sheets. The individual specification shall consist of the following 4 items in principle. 1) Rated specifications. 2) Electrical characteristics. 3) Pin configuration & mechanical dimensions. 4) Others. 5. Inspection of product for delivery

5.1 Inspection lot

a) Inspection lot shall consist of products produced by same material under same design, through same production process, and same facilities and assured same quality by same quality assurance method, and lot number shall be put on all trays to be able to trace the lot history. b) The quantity of products per Inspection lot shall consist of all the same VENDOR’s lot number. 1998-12-01 25/32

TOSHIBA T6A36S,JT6A36X-AS

5.2 Sampling plan

Statistical sampling and inspection shall be in accordance with MIL-STD-105D single sampling plans for normal inspections, general inspection level II. The acceptable quality level (AQL) shall be specified in following table : TEST ITEM AQL (%) [visual [40

5.3 Electrical criteria

Criteria of Electrical Characteristics are prescribed in Attachment-1.

5.4 Visual criteria

Visual Criteria are prescribed in Attachment-2. 6. Incoming inspection

6.1 General

a) PURCHASER’s incoming inspection should be done within 15 days after PURCHASER receives the quantity of products in principle. b) PURCHASER shall report the results of incoming inspection to VENDOR and provide VENDOR with detailed data in failure rate and items regarding VENDOR’s lot number respectively, if VENDOR demands the report from PURCHASER.

6.2 Inspection procedure

PURCHASER should do his incoming inspection according to the following procedure. a) First : Visual inspection should be done. b) Next : Electrical and other inspection should be done under condition with bare chip before going into PURCHASER’s process. 7. Treatment for defective lot and products Regarding the defective lot and defective products which are found through PURCHASER’s incoming inspection, PURCHASER can be returned to VENDOR with detailed description on failures concerned. However, if VENDOR cannot receive the defective items within 30 days after PURCHASER’s incoming inspection, VENDOR should be able to make no reference to the defective problem. 1998-12-01 26/32

TOSHIBA CCG A365S,T6A36X-AS 8. Packing and labeling a) Dice shall be placed in die tray with the top metalization facting up in order. b) In principle, a pile consists of 5 trays and several piles are packed in a package. These piles and packages are indicated with printed labels as shown below. [ Date TT [tot No | | Net | TOSHIBA MADE IN JAPAN ©) PURCHASER shall return these packing materials to VENDOR on VENDOR’s demand. 9. Storage criteria Solid state chips, unlike packaged devices, are non-hermetic devices normally fragile and small in physical size, and therefore, require special handling considerations as follows :

9.1 Chips must be stored under proper conditions to insure that they are not subjected to a

moist and/or contaminated atmosphere that alter their electrical, physical, or mechanical characteristics. After the shipping container is opened, the chips must be stored under the following conditions : A. Storage temperature, 40°C max. B. Relative humidity, 50% max. C. Clean, dust-free environment.

9.2 The user must exercise proper care when handling chips or wafers to prevent even the

slightest physical damage to the chip.

9.3 During mounting and lead bounding of chips the user must use proper assembly techniques

to obtain proper electrical, thermal, and mechanical performance.

9.4 After the chip has been mounted and bounded, any necessary procedure must be followed

by the user to insure that these non-hermetic chips are not subjected to moist or contaminated atmosphere which might cause the development of electrical conductive paths across the relatively small insulating surfaces. In addition, proper consideration must be given to the protection of these devices from other harmful environments which could conceivably adversely affect their proper performance. 8998-12-01 27782

TOSHIBA CCG A365S,T6A36X-AS 10.Handling criteria The user should find the following suggested precautions helpful in handling chips. In any event, because of the extremely small size and fragile nature of chips, care should be taken in handling these devices.

10.1 Grounding

a) Bonders, pellet pickup tools, table tops, trim and form tools, sealing equipment, and other equipment used in chip handling should be properly grounded. b) Operator should be properly grounded.

10.2 In-process handling

a) Assemblies or subassemblies of chips should be transported and stored in conductive carriers. b) All external leads of the assemblies or subassemblies should be shorted together. VISUAL INSPECTION CRITERIA 1. Visual inspection magnification shall be 40 x in principle. 2. Defects defined :

2.1 Thickness

See the technical data sheet.

2.2 Chip and crack

A die shall be rejected if : a) Any crack of chip extends greater than 35m in length into the inside of the scribble line. (see Fig.1) 2.3. Metallization A die shall be rejected if : a) More than 25% of the designed area of the metallization is missing at any bonding pad. b) There is a short or break which affects electrical characteristics in any lead pattern. (see Fig.2)

2.4 Glass protection coat

A die shall be rejected if : a) It exhibits glass protection coat which covers more than 25% of any active bonding pad. 9998-12-01 28/32

TOSHIBA CCCCCC#CTGAQ36S,JTGA\\3GX-ASS

2.5 Attached foreign material

A die shall be rejected if : a) A die is covered by stains or attached foreign material which size is more than 5 times as large as a bonding pad area. b) It exhibits residual ink, stains or attached foreign material which covers more than 20% of any active bonding pad. (see Fig.3)

2.6 Others

A die shall be rejected if : a) There have no evident probed impression on the bonding pads. b) A inked die, defective die, is intermized. 3. Limit samples should be fized, if necessary. + Scribe line Short Break _ Die edge a 35pm Fig.1 Fig.2 Lead pattern Stain or foreign materials Ay Fig.3 1998-12-01 29/32

TOSHIBA T6A36S,JT6A36X-AS OUTSIDE DIMENSIONS OF CHIP TRAY a xafx2 LAT ao nf] 45.8 51.0 z E | H ae re Tid —ho Unit : mm No. OF os Tray material : Carbon-containing polypropylene 1998-12-01 30/32

TOSHIBA T6A36S,JT6A36X-AS PACKING METHOD-1 he | pea pd fee] | TOSHIBA MADE IN JAPAN ‘® Label @ Tray cover © Anti-static plastic bag ZZ B A, B S <4 SSH 2 Packed trays a SSF a Chip ® Packing Heat seal the mouth of the bag. @ Carton ay, $e ‘® Packing > <S © Packing , SS == FH VA E (Oy 123mm Le (00) (O.D) Place eight bags of chip trays in each carton box @. Lay one sheet of packing © (7UF44F) before closing the lid of the cart box. (See the diagram above.) Prepare packing ® by cutting 7UF44F into halves and folding each in half as 1998-12-01 31/32

TOSHIBA T6A36S,JT6A36X-AS PACKING METHOD-2 Shipping box Jascm ‘a5cm 45cm © Inner box: Containing 20 boxes © Weight — : Approx. 15kg (including packing material) © Material: Corrugated cardboard © IC contents : 36x5x8x20=28.8kpcs. 1998-12-01 32/32