T6A11A

T6A11A TOSHIBA | Alldatasheet

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TOSHIBA T6A11A, JT6A11AX-AS TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T6A11A, JT6A11AX-AS i T6A11A, JT6A11AX-AS CMOS 1 CHIP LSI FOR LCD ELECTRONIC CALCULATOR The T6A11A, JT6A11AX-AS is a 1 chip microcomputer for 12-digits 2-memory or 10-digits 2-memory electronic calculator. T6A11A, JT6A11AX-AS can drive the liquid crystal display oo oN (LCD) with single power supply. — — . Single power supply operation, wide operating voltage iw a range and low power consumption make it suitable for <I eg 1.5V solar battery operated calculator. ¢ a Besides T6A11A, JT6A11AX-AS can selectable with a pin- programmable to function of Power timer and Memory hold. QFP67-P-1420-0.80 Weight : 1.20g (Typ.)

FEATURES

Operational Features : © Display : 12-digits or 10-digits (selectable with a pin-programmable) of data, 2-digits of sign, error symbol, memory load symbol. @ Algebraic mode. @ Standard 4 functions(+, -, x, =). @ Memory and grand total (GT) memory calculation. @ Accumulating GT memory register with count up (down) item counter. @ Automatic percentage operation with add-on, discount. @ Automatic delta percentage, mark-up and markdown operations. @ Square root. © Constant calculation. @ Chain calculation. @ Change sign. @ Floating point or momentary mode (selectable with a switch) . @ Fixed point ("0", "1", "2", "3", "4" or "6" places) or floating point (selectable with a switch) . @ Adding point mode (selectable with a switch) . i 280910684 malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In ceveloping your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook 1998-12-01 1/26

TOSHIBA T6A11A,JT6A11AX-AS @ Rounding switches (rounding up, down and off) . @ Leading zero suppression. @ Trailing zero suppression. @ Punctuation on display, commas for thousands. @ Memory and GT memory contents indicator, turned on with non-zero in the memory and GT memory. @ Registration overflow, indicating that too many digits are entered (the most significant digit are protected) . @ Result overflow, indicating during calculation (most function key are locked as it happened) . @ Memory overflow indicating to flashing of memory load mark. @ TAX calculation. Electrical Features © Complementary output buffer for direct driving of liquid crystal display (F.E.M LCD) . © Oscillator /clock generator internal to chip. @ Keyboard encoding internal to chip. @ Keyboard denouncing internal to chip. @ Automatic power on clear. @ Wide supply voltage range (-1.2~ -2.0V). @ Very low power consumption (3.3/W typ.) . © Quad in line flat package. 980910EBA2" & The Hrecucts described in his document are subiect to the foreign exchange ond foreign trade laws The Information contained herein is presented only as a guide for the applications, of our products. No_ responsibilty is assumed by, TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others @ The information contained herein is subject to change without notice. 1998-12-01 2/26

TOSHIBA T6A11A,JT6A11AX-AS SYSTEM BLOCK DIAGRAM se Js foe Js Jo fos [os for [os [os [os fos [oe Jos [oo fo Joe Jo fo Js J cqy BANCO BIOAI0 CH 89 AD Ce BS AB Cr By AT Ce BG AG CS BS AS Ca Be Bas) Aa Bia ce) Bh cy2 83 Cont of 3 od re 60}, T6A11A, JT6A11AX-AS © faa G24 55 (TOP VIEW) B p26 mes prema F od EY aly Pa Fra 661 yo) a, p22 TTT » W551 RESET com com3 HHH Vg TS1TS2 Ky Kz Ka Ka Ks Ke Kr Kg Ko KiokinKkiz2ki3kig COM2 a 14 ee | | mac ail |_| nn Kisral Gre | Gr | ore | orm | ore | orm | ote | ore keep | 10 | 10 | 12 | 12 | 10 | 10 | 12 | 12 ea [LA Le [Te [es fats [2 ti To [Ap) a-| 5 cere Fes fe fd fm fe R st R c mE} ic Le fe bet ef sree coe Ue 3 =10pF fkeys5k0 (1.20) aw | «| 1998-12-01 3/26

TOSHIBA T6A11A, JT6A11AX-AS CONNECTION OF LCD (1) — Select of 10 digits SEGMENT cy. \\ SHIFT = 4TAX = ~TAX é TRERB RRR RBS COMMON (2) Select of 12 digits SEGMENT g g 8 BE \\ SHIFT +TAX ~TAX TAX TAX% ‘PRRBRRBRBE BR COMMON 1998-12-01 4/26

TOSHIBA T6A11A, JT6A11AX-AS PIN LAYOUT =re00 SITS TSPLESLSSIESLSELSS 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 cu ss Ai Bpss 32M Ag 312 7 31 fics ciz 58 30 ff 63 si Wfs9 29 fh Ag so eo T6AIIA 28 co Voo Wt 27 Yop $3 962 (Top view) 26 ez 153 63 25 Az va Woe 2a fc ve Woes 23 fe Vss2 65 22MMAy Vss1 67 1.2.3.4 5 6 7 8 9 101112131415 1617 18 19 2021 OEE COLFE SS SP OH AM SED SpREreorsersoor sores Fs §8s 1998-12-01 5/26

TOSHIBA T6A11A, JT6A11AX-AS KEY LAYOUT @ Touch Key (Grand total memory type) vi Ky DD RESET k2 AC D—P—O- Ka cE D-DD 2 0.0 Kg 5 a 1 ff * Peeic¥e ON” ON @ Touch Key (TAX calculation type) v Kt Dp D—DP—P Ka TAX D5 PTR Pe Ps Pz ky D-DD P 2,05, Kg ff * Peeic¥e ON” ON 1998-12-01 6/26

TOSHIBA T6A11A, JT6A11AX-AS @ Lock Key OPEN 83 Ag C2 Bp AQ a By AY Kia (Nay ad a a a aN a aN aN Sd Y10-di jit Y10-4i jit Y12-4i jit 12-4 it P10-4i jit 10-01 jit 12-1 jit Y12-4i jit x Gah Aun Ot Ln, ota Lis or Lai, ote Lik, OTk Mik, OTH LM, TK A Mik, OTH Kz ce, Se, Se D O D Se Sr © J F F 6 4 3 2 1 0 App Kia... Selectable with calculated digits and memory hold status. 10digit / 12digit : Digits of calculation MH : Memory hold at auto power off or off function. MK : Memory kill at auto power off or off function. GTH : GT memory hold at auto power off or off function. GTk : GT memory kill at auto power off or off function. Ki3 Selectable with auto power off mode and TAX calculation mode and total (= mode) switch. A : Auto power off enable. xq : Auto power off disable. (+3)T : TAX calculation mode. T : GT memory mode. = : mode enable. = : © mode disable Ki2 Rounding switches. Ki Selectable with fixed point or floating mode. (1), (#2) : If K13 or K1 get opened, the status before these keys open is hold. In the case of power on with K13 ‘or K1q open, the status 10 digit and 5, A mode is selected automatically. (#3) : If exchange the mode of TAX calculation and GT memory, please reset the system for [AC] key. SPECIFICATION OF CALCULATOR Speed of Calculator (standard oscillating frequency f¢ = 48kHz) @ Numeral cee eee ee eee eeeeeeeecees 11.8~17.7ms @ Function (Ee 25.6ms © Addition and Subtract {i 2 3EF)1 EE]... eee. 891s @ Memory calculation 2 cece eee ee eeeeeeeeeeeeeeeees 143.3ms 1998-12-01 7/26

TOSHIBA T6A11A, JT6A11AX-AS Key for Calculator fog, (o]~] : Number : Changer Sign El [xk] EJ : Function es M=] : Memory wal Mc} [MR] Me cat : Exchange : Shift : Item Counter Grand total memory type --- MAX. count 999. TAX calculation type --- MAX. count 99. ICE [SA] ON Clear : OFF : SYSTEM RESET 1998-12-01 8/26

TOSHIBA T6A11A, JT6A11AX-AS Operation Example 1. Fixed Point calculation ® Key _ Display Fixed Point Place @ Key Display Fixed Point Place 2 2. 1 1. El 2. ca] 1. 3 3. 2 1.2 | 0.667 3 1.23 2 2. 1.23 O 2. 1 1. 3 2.3 | 1. 2.3 1 11 4 4. E] 3. 6.300 9 9. 1 1. 3. A 1. [x] 3. 2 1.2 1 1. 1.200 A 1. 1 1.1 DP=F 75 = 3.3 TO TOT «926

TOSHIBA T6A11A,JT6A11AX-AS 2. Adding Point mode calculation Key Display Key Display Key Display 0. 0.02M El 33.27M - 1 1. 3 3.M 2 2.M 23 123. : 3.M 0.02M 1.23 123 3.123M 9 9M 3 3. 3.12M A 9M E] 1.26 3.14M 3.M 3 3. 0M El 3.02M 2 32. 1 1M 32. 23 123.M 3 3. El 1.23M A 3. 3 3.M 000 3.000 4 34.M El 96.00 EG 34.M 2 2. 5 34.5M 8998-12-01 10/26

TOSHIBA T6A11A, JT6A11AX-AS 3. Constant Calculation @® Multiplication ®@ Division Key Display Constant Key Display Constant k k a a k El] a a a k k —] ka kx [Ee] ask +k b b kx b b +k E] kb kx E] b/k +k @ Addition ® Subtraction a a a a a E] a k k k k [—] atk +k [=] a-k -k b b +k b b -k [E] b+k +k [] b-k -k © Percentage © Percentage k k a a k [=] a a a k k k-a/100 kx 100-a/k +k b b kx b b +k k-b/ 100 kx 100-b/k =k @ Add-on ® Discount k k k k k El] k a a a a b b k+ b b k- TO 992-0126

TOSHIBA T6A11A, JT6A11AX-AS 4. 4% Calculations @® Key Display @ Key Display a a aoa a El a b b b ob 5. Mark-up, Mark-down Calculations @® Mark-up ® Mark-down Key Display Key Display a a aoa E] a —] a b b b ob a/(1-b/100) -b Ja/(1-b/100) -al a/(1+b/100) |a/(1+b/100) -al 6. Add-on, Discount Calculations Add-on Discount Key Display Key Display Oa a @aia a [k] a b b b ob a-b/100 a-b/100 arb/100 [] ab/100 @a a @®aia a El a b b b ob © a a ®©® aia a a b b b ob TT 992-1272

TOSHIBA T6A11A,JT6A11AX-AS 7. Average Operation use of the Item Counter Key Display Item Counter Key Display Item Counter A A 0 [] A+B+C+D 2 A 1 D D 2 B B 1 A+B4C 3 A+B 2 E E 3 Cc Cc 2 [=] A+B+C+E 4 A+B4C 3 [E] A+B+C+eE 4 D D 3 4 4 A+B+C+D 4 [E] (A+B+C+E)/4 5 8. TAX Calculation Key Op. Display (1) A A A A (2) 0. A (3) B B B(1+A/100) B-A/100 B(1+A/100) B-A/100 (4) B B B/(1+A/ 100) B-B/(1+A/100) [AX] B/(1+A/100) B-B/(1+A/ 100) [TAX] 1998-12-01 13/20

TOSHIBA T6A11A, JT6A11AX-AS MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply Voltage +0.3~-2.0 Input Voltage +0.3~Vg-0.3 Operating Temperature Storage Temperature —55~125 ELECTRICAL CHARACTERISTICS (Vg = - 1.5+0.2V, Vss2 = - 3.0+0.4V, Vpp = OV, Ta=25°C) TEST] PIN PARAMETER SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT cuit] NAME nan K3~K Vi renvne [we [a] [eal — fe | + | qe V. Frome [owe [= fete) [| = foe K3~K ec a nan SEGMENT Vi remo [ von |— st] = — [on ‘ema | vow [looms] — [S| — [SS Vv ‘onmnvnr [venin[— [aren] — [Sel = [ve | | 70" Output VoRage | Vora) |—|Kirka| | of — [-02[ v | Fanon rm | vox | eg pauevnses | [— | | EGMENT Fr onrne | wo [= [eat hen=-a0 [=| =| =| | ; RxevH(1)| — [RESET _[Vour=0V [ 156 | — | 364 | Key Pull Up Resistance kQ y [RKevH (2)| — | Ki~Kio [Vour=0v | 240 | — J 560 | Key Read Pull Up _ Resistance RKEYH (3) Ki~K10 | VouT=0V ka RESET zoom rnc =| ower | [=| wha Resistance [Revi (2) | — [K11~K1a [Vout=Vss2 | 120 | — | 800 | Oscilating WAM | tgwaiT|—| — [Vg=-t5V__ | 5a 90] 26], Frequency _|(OPERATE)| fgOP_ | — | — [Vg=-1.5V [ 28.8 | 48 | 67.2 | rman || rer-tee nam [ w supply LOAM [Iopwarr | = [= [Ve==75V | — [ 22] 34] Supply [a(OPERATE| Ippor | — | = |Ve==12V [= [70 [710] pa [Power Off Timer Times | T | — | — _[Vg=-15V [a29-[ 600 [7001 | 3 _| 1998-12-01 14/26

TOSHIBA T6A11A,JT6A11AX-AS WAVEFORMS FOR DISPLAY 1 (93.8Hz) NOTE-1 Vop : ov oy s2 8 }r=3.56ms NOTE-1 com2 SEGMENT ——vop : ov “LIL — Vss2_: -3V ay-comt ——— s15v (on) J ff eee oy —— -15v — - orelon| ore Jon | orF jon, a1-com3 —— +15v ‘OFF — 7 15v NOTE-1 at fd =9kHz 1998-12-01 15/26

TOSHIBA T6A11A,JT6A11AX-AS PAD LOCATION TABLE (um) [wane | xronr | veon ] [wane xront | vronr_| [Va | aaa [469 ee [ss | 252 | 469 _| | s2 | 203 | = 1469 | *csa) | 891469 po si |= 355 |= 1469 ee pociz |= 507 |= 1469 p Az | 3921469 | Biz |= 659 |= 1469 ee | Aw | 810 |= 1469 | 8: | 696 | 469 [ci |= 980 |= 1469 p Bi |= 1762 |= 1469 | coms [| 999 | 1469 [80 | 1408 | - 108 | [8 | 1408 [586 | [kro | 1408 [503] a a [86 | -™0s | 773 [Ag | 1408 [936 | [kr | 1408 [= 862] [85 | -1358 | 1469 [Ve 160 | 1469 *( ) Do not connect. 8998-12-01 16726

TOSHIBA T6A11A, JT6A11AX-AS CHIP LAYOUT = ges SLSSIOSTOE SI55zESGS oooooo0o0o0o0o0o0o0o000000o ci] o Ka ‘e6l] oO Oo fk sel] O O riz cl] O O fxn ~il a OF fro 7a i | OO |ko oo C1 fiks A k eG JT6A11AX-AS Oke cll Oo O ||ks sot} O O jks si] oO O fjks ol] Oo o fix Aol] O oO ]fk sol] O OF |freser col] O oO fsa. onoooooooo0o00000000 fas ESE FFB OB SS BBS Chip size + 3.28x3.46 [mm] Chip thickness : 440+30jm Substrate : Vpp PAD LAYOUT Active Element GY 40pm GY 4 Bonding Area f 100m Y |e | = LL 40 um as Scribe Line PAD Pitch 160m 1998-12-01 17/26

TOSHIBA T6A11A,JT6A11AX-AS OUTLINE DRAWING QFP67-P-1420-0.80 Unit : mm 24.140.4 20.0+0.2 2.0TYP 1.2TYP & 54 33

8 HOOD TIN OOAO COO anon

“ (LL TT EE E 55 = a | 3 — > 32 = = al « | a S| & 2 bard —| = + 3 } = = § |” a —r ms a 7 = =a 22 HOHE OHH UPR HOD UUWHOUUOUOOUO Ooo 1 21 2.0TYP 0.30.1 2.0TYP aq fl qa ATTA = . sl brid nu 1.3520.2 Weight : 1.20g (Typ.) 1998-12-01 18/26

TOSHIBA T6A11A,JT6A11AX-AS GENERAL SPECIFICATION FOR CALCULATOR LSI BARE CHIP 1. Purpose This is to specify the quality standard for the integrated circuit produced by TOSHIBA CORPORATION (hereinafter referred as to VENDOR) to be delivered to PURCHASER. 2. Definition This specification applies only to the calculator LS! bare chip produced by VENDOR and purchased by PURCHASER and defined the general specification items. 3. Priority of specifications When the discrepancies or questions happen to the specifications and instructions provided by VENDOR, the priority shall be ranked as follows. 1) Individual specification for the calculator LSI bare chip. (Both PURCHASER and VENDOR are confirmed by the special sheets.) 2) General specifications for the calculator LSI bare chip. 3) Other related specifications and standards. 4. Characteristics To be shown in the individual specification sheets. The individual specification shall consist of the following 4 items in principle. 1) Rated specifications. 2) Electrical characteristics. 3) Pin configuration & mechanical dimensions. 4) Others. 5. Inspection of product for delivery

5.1 Inspection lot

a) Inspection lot shall consist of products produced by same material under same design, through same production process, and same facilities and assured same quality by same quality assurance method, and lot number shall be put on all trays to be able to trace the lot history. b) The quantity of products per Inspection lot shall consist of all the same VENDOR’s lot number. 1998-12-01 19/26

TOSHIBA T6A11A,JT6A11AX-AS

5.2 Sampling plan

Statistical sampling and inspection shall be in accordance with MIL-STD-105D single sampling plans for normal inspections, general inspection level II. The acceptable quality level (AQL) shall be specified in following table : TEST ITEM AQL (%) [visual [40

5.3 Electrical criteria

Criteria of Electrical Characteristics are prescribed in Attachment-1.

5.4 Visual criteria

Visual Criteria are prescribed in Attachment-2. 6. Incoming inspection

6.1 General

a) PURCHASER’s incoming inspection should be done within 15 days after PURCHASER receives the quantity of products in principle. b) PURCHASER shall report the results of incoming inspection to VENDOR and provide VENDOR with detailed data in failure rate and items regarding VENDOR’s lot number respectively, if VENDOR demands the report from PURCHASER.

6.2 Inspection procedure

PURCHASER should do his incoming inspection according to the following procedure. a) First : Visual inspection should be done. b) Next : Electrical and other inspection should be done under condition with bare chip before going into PURCHASER’s process. 7. Treatment for defective lot and products Regarding the defective lot and defective products which are found through PURCHASER’s incoming inspection, PURCHASER can be returned to VENDOR with detailed description on failures concerned. However, if VENDOR cannot receive the defective items within 30 days after PURCHASER’s incoming inspection, VENDOR should be able to make no reference to the defective problem. 1998-12-01 20/26

TOSHIBA T6A11A,JT6A11AX-AS 8. Packing and labeling a) Dice shall be placed in die tray with the top metalization facting up in order. b) In principle, a pile consists of 5 trays and several piles are packed in a package. These piles and packages are indicated with printed labels as shown below. [dae] sd | totNo. [| [Net | TOSHIBA MADE IN JAPAN ©) PURCHASER shall return these packing materials to VENDOR on VENDOR’s demand. 9. Storage criteria Solid state chips, unlike packaged devices, are non-hermetic devices normally fragile and small in physical size, and therefore, require special handling considerations as follows :

9.1 Chips must be stored under proper conditions to insure that they are not subjected to a

moist and/or contaminated atmosphere that alter their electrical, physical, or mechanical characteristics. After the shipping container is opened, the chips must be stored under the following conditions : A. Storage temperature, 40°C max. B. Relative humidity, 50% max. C. Clean, dust-free environment.

9.2 The user must exercise proper care when handling chips or wafers to prevent even the

slightest physical damage to the chip.

9.3 During mounting and lead bounding of chips the user must use proper assembly techniques

to obtain proper electrical, thermal, and mechanical performance.

9.4 After the chip has been mounted and bounded, any necessary procedure must be followed

by the user to insure that these non-hermetic chips are not subjected to moist or contaminated atmosphere which might cause the development of electrical conductive paths across the relatively small insulating surfaces. In addition, proper consideration must be given to the protection of these devices from other harmful environments which could conceivably adversely affect their proper performance. 1998-12-01 21/26

TOSHIBA TGA 1A, JTGA11AX-AS 10.Handling criteria The user should find the following suggested precautions helpful in handling chips. In any event, because of the extremely small size and fragile nature of chips, care should be taken in handling these devices.

10.1 Grounding

a) Bonders, pellet pickup tools, table tops, trim and form tools, sealing equipment, and other equipment used in chip handling should be properly grounded. b) Operator should be properly grounded.

10.2 In-process handling

a) Assemblies or subassemblies of chips should be transported and stored in conductive carriers. b) All external leads of the assemblies or subassemblies should be shorted together. VISUAL INSPECTION CRITERIA 1. Visual inspection magnification shall be 40 x in principle. 2. Defects defined :

2.1 Thickness

See the technical data sheet.

2.2 Chip and crack

A die shall be rejected if : a) Any crack of chip extends greater than 35m in length into the inside of the scribble line. (see Fig.1) 2.3. Metallization A die shall be rejected if : a) More than 25% of the designed area of the metallization is missing at any bonding pad. b) There is a short or break which affects electrical characteristics in any lead pattern. (see Fig.2)

2.4 Glass protection coat

A die shall be rejected if : a) It exhibits glass protection coat which covers more than 25% of any active bonding pad. TT 992-01 22726

TOSHIBA TGA 1A, JTGA11AX-AS

2.5 Attached foreign material

A die shall be rejected if : a) A die is covered by stains or attached foreign material which size is more than 5 times as large as a bonding pad area. b) It exhibits residual ink, stains or attached foreign material which covers more than 20% of any active bonding pad. (see Fig.3)

2.6 Others

A die shall be rejected if : a) There have no evident probed impression on the bonding pads. b) A inked die, defective die, is intermized. 3. Limit samples should be fized, if necessary. + Scribe line Short Break _ Die edge a 35pm Fig.1 Fig.2 Lead pattern Stain or foreign materials 20%” 4 Fig.3 8998-12-01 23/26

TOSHIBA T6A11A,JT6A11AX-AS OUTSIDE DIMENSIONS OF CHIP TRAY a xafx2 LAT ao nf] 45.8 51.0 z E | H ae re Tid —ho Unit : mm No. OF [resmcae[ ene [om [oe [oe] ag [|e Tray material : Carbon-containing polypropylene 1998-12-01 24/26

TOSHIBA T6A11A,JT6A11AX-AS PACKING METHOD-1 [vee [| Joara [| TOSHIBA, MADE IN JAPAN nuysi0ce ‘® Label @ Tray cover © Anti-static plastic bag — © Chip tray SSS Zo ZA| 2 —— SSH 2 Packed trays a SSE ———— =) en Chip © Packing Heat seal the mouth of the bag, @® Carton ay, $e ‘® Packing U—wWw © Packing , _ = FH po Ka s5mm SS (0D) 123mm i. (0D) 107mm ~ (OD) Place eight bags of chip trays in each carton box @. Lay one sheet of packing © (7UF44F) before closing the lid of the cart box. (See the diagram above.) Prepare packing ® by cutting 7UF44F into halves and folding each in half as partitions 1998-12-01 25/26

TOSHIBA T6A11A, JT6A11AX-AS PACKING METHOD-2 Shipping box Jascm ‘a5cm 45cm © Inner box: Containing 20 boxes © Weight — : Approx. 15kg (including packing material) © Material: Corrugated cardboard © IC contents : 36x5x8x20=28.8kpcs. 1998-12-01 26/26