T6A04A TOSHIBA | Alldatasheet

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Features

/Gb7/G20On-chip display RAM capacity : 120 × 64 = 7.5 kbits /Gb7/G20Display RAM data /Gb7/G201/64 duty cycle /Gb7/G20Word length of display data can be switched between eight bits and six bits according to the character font. /Gb7/G20LCD driver outputs : 120 column driver outputs and 64 row driver outputs /Gb7/G20Interface with 80-series MPU /Gb7/G20On-chip oscillator with one external resistor /Gb7/G20Low power consumption /Gb7/G20On-chip resistors to divide bias voltage, on-chip operational amplifier for LCD supply, on-chip DC-DC converter, on-chip contrast control circuit /Gb7/G20CMOS process /Gb7/G20Operating voltage : 4.5 to 5.5 V /Gb7/G20Operating voltage for LCD drive signal : V DD − VEE = 16.0 V (max) /Gb7/G20Package : TCP (tape carrier package) Unit: mm Lead Pitch IN T6A04A (UAW, 6NS) OUT (UEM, 7NS) 1.0 0.4 0.28 0.4 Please contact Toshiba or an authorized Toshiba dealer for information on package dimensions. TCP (Tape Carrier Package)

(32) 32-bit SHIFT REGISTER LCD DRIVE CIRCUIT (32) 32-bit SHIFT REGISTER LCD DRIVE CIRCUIT (120) LATCH INPUT/OUTPUT GATE Y-ADDRESS COUNTER/DECODER MPX X-COUNTER Z-COUNTER TIMING GENERATION CIRCUIT OSCILLATOR OP-AMP (/Gb45) RESISTOR LADDERS CONTRAST CONTROL CIRCUIT DC-DC CONVERTER INPUT/OUTPUT BUFFER OUTPUT BUFFER INPUT/OUTPUT BUFFER I/F CONTROL CIRCUIT INPUT/OUTPUT BUFFER OUTPUT REGISTER INPUT REGISTER WORD LENGTH CONVERTER REGISTER Z-ADDRESS REGISTER COUNTER UP/DOWN REGISTER X･Y COUNTER SELECT REGISTER DISPLAY ON/OFF REGISTER CONTRAST CONTROL REGISTER OP-AMP CONTROL REGISTER BIT TRANSFER CIRCUIT COM32 COM33 COM64 SEG1 SEG120 MPX M/S FS1 FS2 VLC1 C1 C 2 COMD SCLK OSC1 OSC2 / /G66PM C L FRM M /STB EXP /RST D/I /WR /CE DB0 to DB7 844 5 3 VLC2 VLC3 VLC4 VLC5 VEE VIN VOUT DECODER 120 DISPLAY RAM 120 /Gb4 64 /G3d 7.5 kbits

Note 1: The above diagram shows the pin configuration of the LSI chip; it does not show the configuration of the tape carrier package. T6A04A (top view) DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 /RST /CE /WR D/I EXP M/S OSC2 OSC1 FS2 FS1 V DD //G66 PM /G66B /G66A P/G66 FRM M C L COMB VSS /STB VOUT VIN VEE VLC1 VLC2 VLC3 VLC4 VLC5 COM32 COM1 SEG1 SEG120 COM33 COM64

SEG1 to SEG120 Output Column driver output COM1 to COM64 Output Row driver output

  • Disable expansion mode (EXP /G3d L, M/S /G3d H) /Gae COM1 to COM64 are enabled.
  • Enable expansion mode/master mode (EXP /G3d H, M/S /G3d H) /Gae COM1 to COM32 are enabled and COM33 to COM64 are disabled.
  • Enable expansion mode/slave mode (EXP /G3d H, M/S /G3d L) /Gae COM1 to COM32 are disabled and COM33 to COM64 are enabled. CL I/O Input/output for shift clock pulse
  • Master mode (M/S /G3d H) /Gae Output
  • Slave mode (M/S /G3d L) /Gae Input M I/O Input/output for frame signal
  • Master mode (M/S /G3d H) /Gae Output
  • Slave mode (M/S /G3d L) /Gae Input FRM I/O Input/output for display synchronous signal
  • Master mode (M/S /G3d H) /Gae Output
  • Slave mode (M/S /G3d L) /Gae Input P/G66, /G66A, /G66B I/O Input/output system clock signal
  • Master mode (M/S /G3d H) /Gae Output
  • Slave mode (M/S /G3d L) /Gae Input COMD I/O Input/output row signal data
  • Master mode (M/S /G3d H) /Gae Output
  • Slave mode (M/S /G3d L) /Gae Input DB0 to DB7 I/O Data bus D/I Input Input for data/instruction select signal
  • D/I /G3d H /Gae indicates that the data on DB0 to DB7 is display data.
  • D/I /G3d L /Gae indicates that the data on DB0 to DB7 is control data. /WR Input Input for write select signal
  • /WR /G3d H /Gae Read selected
  • /WR /G3d L /Gae Write selected /CE Input Input for chip enable signal
  • /WR /G3d L /Gae Data on DB0 to DB7 is latched on the rising edge of /CE.
  • /WR /G3d H /Gae Data appears at DB0 to DB7 while /CE is Low. /RST Input Input for reset signal
  • /RST /G3d L /Gae Reset state /STB Input Input for standby signal
  • Usually connected to V DD
  • /STB /G3d L /Gae T6A04A is in standby state and cannot accept any commands or data. Column driver signal and row driver signal are at the VDD level FS1, FS2 Input Input for frequency selection EXP Input Input for expansion mode selection
  • M/S /G3d H /Gae enables expansion mode. Two chips can be used together.
  • M/S /G3d L /Gae disables expansion mode.

Input for master/slave selection

  • M/S /G3d H /Gae T6A04A is master chip.
  • M/S /G3d L /Gae T6A04A is slave chip. OSC1, OSC2 /Gbe When using the internal clock oscillator, connect a resistor between OSC1 and OSC2. When using an external clock, connect the clock as input to OSC1 and leave OSC2 open. R1, R2 /Gbe Input for LCD drive bias selection
  • LCD drive bias selection is shown in the following table R

2 R1 Bias

C1, C2 /Gbe Connected by a capacitor for DC-DC converter VIN /Gbe Input for DC-DC converter. Connect to V DD. VOUT /Gbe DC-DC converter output VEE /Gbe Power supply for LCD driver circuit

  • When using on-chip DC-DC converter, connect V EE to VOUT VLC1 to VLC5 /Gbe Power supply for LCD driver circuit
  • M/S /G3d H /Gae bias voltage output
  • M/S /G3d L /Gae bias voltage input VDD /Gbe Power supply for logic circuit VSS /Gbe Ground: Reference PM /Gbe Pre-frame signal for Toshiba T9841B //G66 /Gbe Output system clock for Toshiba T9841B

/Gb7/G20DC-DC converter The T6A04A has an on-chip DC-DC converter. When /G2b5 V is applied to VIN, the DC-DC converter generates /G2d5 V at VOUT. The voltage from VOUT will drop due to the load current for VEE. This characteristic is defined in “Electrical Characteristics”. Normally the value of external capacitors is 1.0 /G6dF; this value may need some adjustment according to the application. When the T6A04A is in standby state, V OUT /G3d 0 V. See Figure 6. When using an external power supply, input the voltage to VEE and leave the C1, C2 VOUT pins open. External capacitor C /G3d 1.0 /G6dF External capacitor C /G3d 1.0 /G6dF Usually connected to VDD Usually connected to VEE VOUTVIN DC-DC Figure 6

/Gb7/G20Voltage divider resistors, contrast control circuit The T6A04A has on-chip resistors which include op-amps, that divide the bias voltage, and a contrast control circuit. The voltage bias is modified by the values of R1 and R2. One of four biases can be selected. These resistors and the contrast control circuit are shown in Figure 7 below. /Gb7/G20Op-amp, op-amp control register The T6A04A has five operational amplifiers which determine the LCD driving level. The power supplied by these op-amps is modified by the contents of the op-amp control register to match the LCD panel. The op-amp can also be controlled in such a way that it supplies full current on the rising edge of C L and a reduced current otherwise. To maintain good LCD contrast, connect a capacitor between the op-amp output and VDD. The value of the capacitor should normally be in the range 0.1 to 1.0 /G6dF. Figure 7 /STB 5RB 4RB 3RB 2RB RB RB VDD VLC1 RB RB VLC3 VLC4 VLC5 DB0 RC DB1 2RC DB2 4RC DB3 8RC DB4 16RC DB5 32RC VEE DB6 DB7 Contrast Control Register /G3d Voltage Follower Circuit RB /G3d 134 k/G57 (typ.) RC /G3d 10.1 k/G57 (typ.) Decoder VLC2 Decoder

/Gb7/G20Display RAM The display RAM consists of 64 rows /Gb4 120 columns for a total of 7680 cells. It is directly bit-mapped to the LCD. The relation between the display RAM and LCD is shown in Figure 8. When the word length is set to eight bits, the display RAM is arranged in 15 pages and each page contains 64 words. When the word length is set to six bits, the display RAM is arranged in 20 pages and each page contains 64 words. See Figure 8. (1) 8-bits-per-word mode (2) 6-bits-per-word mode Figure 8 D1 D3 D 2 D 0 D7 D6 D5 D4 D3 D2 D1 D0D6 D 5 D 4

1 SEG1

0 SEG2

1 SEG3

0 SEG4

1 SEG5

0 SEG6

1 SEG7

0 SEG8

1 SEG9

0 SEG10

1 SEG11

0 SEG12

1 SEG13

0 SEG14

1 SEG15

0 SEG16

120 /Gb4 64 bit DISPLAY RAM MSB LSB X-Address D7 D0 PAGE13 PAGE14 PAGE1 PAGE2PAGE0 Y- (page) Address X-Address XAD0 XAD1 XAD62 XAD63 D5 D0 PAGE18 PAGE19 PAGE1 PAGE2PAGE0 Y- (page) Address X-Address XAD0 XAD1 XAD62 XAD63 Figure 9

Name D/I /WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function DPE 0 0 0 0 0 0 0 0 1 1/0 Display ON (1)/OFF (0) 86E 0 0 0 0 0 0 0 0 0 1/0 Word Length: 8 bits (1)/6 bits (0) UDE 0 0 0 0 0 0 0 1 1/0 1/0 Counter Select : DB1 Y (1)/X (0) Mode Select : DB0 UP (1)/DOWN (0) CHE 0 0 0 0 0 1 1 * * * Test Mode Select OPA1 0 0 0 0 0 1 0 * 1/0 1/0 Op-amp Power Control 1 OPA2 0 0 0 0 0 0 1 * 1/0 1/0 Op-amp Power Control 2 SYE 0 0 0 0 1 Y-(page) Address (0 to 19) Y-(page) Address Set SZE 0 0 0 1 Z-Address (0 to 63) Z-Address Set SXE 0 0 1 0 X-Address (0 to 63) X-Address Set SCE 0 0 1 1 CONTRAST CONTROL (0 to 63) Contrast Set STRD 0 1 B 8/6 D R 0 0 Y/X U/D Status Read DAWR 1 0 Write Data Display Data Write DARD 1 1 Read Data Display Data Read *: INVALID /Gb7/G20Display ON/OFF select (DPE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 1 Display ON (03H) 0 0 0 0 0 0 0 0 1 0 Display OFF (02H) This command turns display ON/OFF. It does not affect the data in the display RAM. Note 2: An L input on /RST turns display OFF. /Gb7/G20Word length 8 bits/6 bits select (86E) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 8 Bits/Word Mode (01H) 0 0 0 0 0 0 0 0 0 0 6 Bits/Word Mode (00H) This command sets the word length for display RAM data to eithers six bits or eight bits. Note 3: An L input on /RST sets the word length to eight bits per word.

/Gb7/G20X/Y (page) counter, up/down mode select (UDE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 0 0 X-Counter/Down Mode (04H) 0 0 0 0 0 0 0 1 0 1 X-Counter/Up Mode (05H) 0 0 0 0 0 0 0 1 1 0 Y-Counter/Down Mode (06H) 0 0 0 0 0 0 0 1 1 1 Y-Counter/Up Mode (07H) This command selects the counter and the up/down mode. For instance, when X-counter/up mode is selected, the X-address is incremented in response to every data read and write. However, when X-counter/up mode is selected, the address in the Y-(page) counter will not change. Hence the Y-address must be set (with the SYE command) before it can be changed. Note 4: An L input to /RST sets the Y-counter to up mode. /Gb7/G20Test mode select (CHE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 1 * * * *: INVALID This command selects the test mode. Do not use this command. /Gb7/G20Set Y-(page) address (SYE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 A A A A A Range: 8-bit/Word: 20H to 2EH (page 0 to page 14) 6-bit/Word: 20H to 33H (page 0 to page 19) When operating in 8-bits-per-word mode, this command selects one of the 15 pages from the display RAM. (Do not try to select a page outside this range.) When operating in 6-bits-per-word mode, this command selects one of the 20 pages from the display RAM. Note 5: An L input to /RST sets the Y-address to page 0. /Gb7/G20Set Z-address (SZE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 A A A A A A Range: 40H to 7FH (ZAD0 to ZAD63) This command sets the top row of the LCD screen, irrespective of the current X-address. For instance, when the Z-address is 32, the top row of the LCD screen is address 32 of the display RAM, and the bottom row of the LCD screen is address 31 of the display RAM. Note 6: An L input to /RST sets the Z-address to 0.

/Gb7/G20Set X-address (SXE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 A A A A A A Range: 80H to BFH (XAD0 to XAD63) This command sets the X-address (in the range 0 to 63). An L input to /RST sets the X-address to 0. /Gb7/G20Set contrast (SCE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 A A A A A A Range: C0H to FFH This command sets the contrast for the LCD. The LCD contrast can be set in 64 steps. The command C0H selects the brightest level; the command FFH selects the darkest. /Gb7/G20Op-amp control 1 (OPA1) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 * A A *: INVALID Range: 10H to 13H (when DB2 /G3d 0) This command sets the power supply strength for the operational amplifier. This command selects one of four levels. The command 10H selects the lowest power supply strength and the command 13H selects the maximum strength. Note 7: An L input to /RST sets the op-amp power supply strength to the lowest level. /Gb7/G20Op-amp control 2 (OPA2) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 * A A *: INVALID Range: 08H to 0BH (when DB2 /G3d 0) This command enhances the power supply strength of the operational amplifier over a short period from the rising edge of CL. This command selects one of four levels of strength. Note 8: An L input to /RST sets t to 0 for op-amp. See Figure 10. T The amplifier’s strength is enhanced over the period denoted by /Gab, starting on the rising edge of CL. CL (1) When this command is 08H (2) When this command is 09H (3) When this command is 0AH (4) When this command is 0BH t /G3d 0 t/T /G3d 1/12 t/T /G3d 1/6 t/T /G3d 1/3 t t t Figure 10

/Gb7/G20Status read (STRD) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 B 8/6 D R 0 0 Y/X U/D B (busy) : When B is 1, the T6A04A is executing an internal operation and no instruction can be accepted except STRD. When B is 0, the T6A04A can accept an instruction. 8/6 (word length) : When 8/6 is 1, the word length of the display data is eight bits per word. When 8/6 is 0, the word length of the display data is six bits per word. D (display) : When D is 1, display is ON. When D is 0, display is OFF. R (reset) : When R is 1, the T6A04A is in reset state. When R is 0, the T6A04A is in operating state. Y/X (counter) : When Y/X is 1, the Y counter is selected. When Y/X is 0, the X counter is selected. U/D (up/down) : When U/D is 1, the X and Y counters are in up mode. When U/D is 0, the X and Y counters are in down mode. /Gb7/G20Write/read display data (DAWR/DARD) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 D D D D D D D D DAWR: Display Data Write 1 1 D D D D D D D D DARD: Display Data Read The command DAWR writes the display data to the display RAM. The command DARD outputs the display data from the display RAM. However, when a data read is executed, the correct data does not appear on the first data reading. Therefore, ensure that the T6A04A performs a dummy data read before reading the actual data.

/Gb7/G20Data read When reading data, there are some cases when dummy data must be read. This is because when the data read command invoked, the data pointed to by the address counter is transferred to the output register; the contents of the output register are then transferred by the next data read command. Therefore when reading data straight after power-on or straight after an address-setting command, such as SYE or SXE, a dummy data read must be performed. See Figure 12. /Gb7/G20Reset function When /RST /G3d L, the reset function is executed and the following settings are mode. /Gb7/G20Standby function When /STB /G3d L, the T6A04A is in standby state. The internal oscillator is stopped, power consumption is reduced, and the power supply level for the LCD (V LC1 to VLC5) becomes VDD. /Gb7/G20Busy flag When the T6A04A is executing an internal operation (other than the STRD command), the busy flag is set to logical H. The state of the busy flag is output in response to the STRD command. While the busy flag is H, no instruction can be accepted (except the STRD command). The busy state period (T) is as follows. 2/fosc /G3c/G20 /G3dT /G3c/G20/G3d4/fosc [seconds] fosc: Frequency of OSC1 Figure 12 Dummy Read Power on SYE /G3d 20H SXE /G3d 80H UDE /G3d 05H DARD 0 DARD 1 DARD 1 SYE /G3d 21H DARD 0 Dummy Read DARD 2 DARD 1 DARD 0

/Gb7/G20Oscillation frequency The frequency select pins (FS1 and FS2), are used to set the relation between the oscillation frequency (f OSC) and frame frequency (fM), as shown in the table below. Rf (k/G57) f OSC (kHz) f/ /G66 (kHz) f FRM (Hz) f M (Hz) FS1 FS2 1000 26.88 13.44 70 35 0 0 480 53.76 26.88 70 35 1 0 105 215.00 107.50 70 35 0 1 50 430.10 215.00 70 35 1 1 Note 9: The resistance values are typical values. The oscillation frequency depends on how the device is mounted. It is necessary to adjust the oscillation frequency to a target value. /Gb7/G20Expansion function The T6A04A’s expansion function, allows two, T6A04As to drive an LCD panel of up to 240 by 64 dots. The table below shows the functions which can be selected with the M/S and EXP pins. M/S H L H

  • Two-chip mode (enable expansion mode)
  • Master chip COM1 to COM32 are available.
  • Two-chip mode (enable expansion mode)
  • Slave chip
  • COM33 to COM64 are available.
  • Timing signals and power voltage are supplied from master chip. EXP L
  • Single-chip mode (disable expansion mode)
  • COM1 to COM32 are available.
  • Do not select. Figures 13-1 and -2 illustrate application examples of disable expansion mode and enable expansion mode. Enable Expansion Mode (two-chip mode) As shown in Figure 13-2, and Figure 14 the master chip supplies the LCD drive signals and power voltage to the slave chip (the oscillator, the timing circuits, op-amp and contrast control circuit are disabled). COM1 to COM32 of the master chip and COM33 to COM64 of the slave chip are available (COM33 to COM64 of the master chip and COM1 to COM32 of the slave chip are disabled). The T9841B is available as an expansion driver for the T6A04A (a T6A04A and T9841B can drive a 200 /Gb4 64-dot LCD panel). (1) Disable expansion mode 32-bit SR COM32 Out COM32 Out 32-bit SR SEG 120 Out RAM 120 /Gb4 64 Cell 120 dots 32 dots COM1 to 32 SEG1 to 120COM33 to 64 32 120 32 32 dots Figure 13-1

Absolute Maximum Ratings (Ta /G3d/G3d/G3d/G3d 25°C) Characteristics Symbol Rating Unit Supply voltage (1) VDD (Note 10) /G2d0.3 to 7.0 V Supply voltage (2) VLC1, 2, 3, 4, 5 VEE (Note 12) VDD /G2d 18.0 to VDD /G2b 0.3 V Input voltage VIN (Note 10, 11) /G2d0.3 to VDD /G2b 0.3 V Operating temperature T opr /G2d20 to 75 °C Storage temperature T stg /G2d55 to 25 °C Note 10: Referenced to VSS /G3d 0 V Note 11: Applies to all data bus pins and input pins except VEE, VLC1, VLC2, VLC3, VLC4 and VLC5. Note 12: Ensure that the following condition is always maintained. VDD /G3e/G20/G3dVLC1 /G3e/G20/G3dVLC2 /G3e/G20/G3dVLC3 /G3e/G20/G3dVLC4 /G3e/G3dVLC5 /G3e/G3dVEE to VDD VDD /G66A //G66 CL FRM PM M COM1 SEG120 SEG1 COM2 COM64 64 1 2 3 64 1 2 3 64 1 VDD VDD VDD VDD V DD VDD ON ON OFF OFF LCD driver timing chart (1/64 duty) to

Electrical Characteristics

Test Conditions (Unless Otherwise Noted, VSS /G3d/G3d/G3d/G3d 0 V, VDD /G3d/G3d/G3d/G3d 5.0 V /Gb1/Gb1/Gb1/Gb1 10%, VLC5 /G3d/G3d/G3d/G3d 0 V, Ta /G3d/G3d/G3d/G3d /G2d/G2d/G2d/G2d20 to 75°C) Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit PIN Name Operating supply (1) V DD /Gbe /Gbe 4.5 /Gbe 5.5 V V DD, VIN Operating supply (2) VLC5 VEE /Gbe /Gbe VDD /G2d 16.0 /Gbe VDD /G2d 4.0 V V EE, VLC5 H level V IH1 /Gbe /Gbe 0.7 VDD /Gbe V DD Input voltage (1) L level V IL1 /Gbe /Gbe 0 /Gbe 0.3 VDD V M/S, EXP, R1, R2, CL, M, FRM, /G66A, /G66B, COMD, FS1, FS2, P/G66 H level V IH2 /Gbe /Gbe 2.2 /Gbe V DD Input voltage (2) L level V IL2 /Gbe /Gbe 0 /Gbe 0.8 V DB0 to DB7, D/I, /WR, /CE, /RST, /STB H level V OH1 /Gbe I OH /G3d /G2d400 /G6dA VDD /G2d 0.4 /Gbe V DD Output voltage (1) L level V OL1 /Gbe I OL /G3d 400 /G6dA 0 /Gbe 0.4 V CL, M, FRM, P/G66, COMD, /G66A, /G66B H level V OH2 /Gbe I OH /G3d /G2d205 /G6dA 2.4 /Gbe V DD Output voltage (2) L level V OL2 /Gbe I OL /G3d 1.6 mA 0 /Gbe 0.4 V D/I, /WR, /CE, DB0 to DB7, /RST, /STB Column output resistance Rcol /Gbe VDD /G2d VLC5 /G3d 11.0 V Load current /G3d /Gb1100 /G6dA /Gbe /Gbe 7.5 k /G57 SEG1 to SEG120 Row output resistance Rrow /Gbe VDD /G2d VLC5 /G3d 11.0 V Load current /G3d /Gb1100 /G6dA /Gbe /Gbe 1.5 k /G57 COM1 to COM64 Input leakage I IL /Gbe V IN /G3d VDD to GND /G2d1 /Gbe 1 /G6dA M/S, EXP, R1, R2, CL, M, FRM, D/I, /WR, COMD, /CE, DB0 to DB7, /STB, /RST, FS1, FS2, P/G66, /G66A, /G66B Operating freq. f φ /Gbe /Gbe 10 /Gbe 250 kHz / /G66 External clock freq. f ex /Gbe /Gbe 20 /Gbe 500 kHz OSC1 External clock duty f duty /Gbe /Gbe 45 50 55 % OSC1 External clock rise/fall time t r/tf /Gbe /Gbe /Gbe /Gbe 50 ns V DD Current consumption (1) I DD1 /Gbe (Note 13) /Gbe 850 1400 /G6dA V DD Current consumption (2) I DD2 /Gbe (Note 14) /Gbe 950 1600 /G6dA V DD Current consumption (3) I DDSTB /Gbe (Note 15) /G2d1 /Gbe 1 /G6dA V DD Output voltage Vo 1 (Note 16) /G2d4.0 /G2d4.2 /Gbe V V OUT Note 13: VDD /G3d 5.0 V /Gb1 10%, VEE /G3d VOUT (from DC-DC converter) Master mode, no data access R f /G3d 47 k/G57, no load 1/9 bias, FS1, 2 /G3d H, op-amp strength at minimum level Note 14: VDD /G3d 5.0 V /Gb1 10%, VEE /G3d VOUT (from DC-DC Converter) Master mode, data access cycle f/CE /G3d 1 MHz Rf /G3d 47 k/G57, No load 1/9 bias, FS1, 2 /G3d H, op-amp strength at minimum level Note 15: VDD /G3d 5.0 V /Gb1 10%, VDD /G2d VEE /G3d 16 V Master mode, /STB /G3d L Note 16: VIN /G3d 5.0 V, ILoad /G3d 500 /G6dA, VEE /G3d /G2d5.0 V (external power supply) C1 /G2d C2 /G3d 1.0 /G6dF, VIN /G2d VOUT /G3d 1.0 /G6dF, R /G3d 47 k/G57, Ta /G3d 25°C

Test Conditions (Unless Otherwise Noted, VSS /G3d/G3d/G3d/G3d 0 V, VDD /G3d/G3d/G3d/G3d 5.0 V /Gb1/Gb1/Gb1/Gb1 10%, Ta /G3d/G3d/G3d/G3d /G2d/G2d/G2d/G2d20 to 75°C) Characteristics Symbol Min Max Unit Enable cycle time t cycE 500 /Gbe ns Enable pulse width PWEL 220 /Gbe ns Enable rise/fall time t Er, tEf /Gbe 20 ns Address set-up time t AS 40 /Gbe ns Address hold time t AH 0 /Gbe ns Data set-up time t DS 60 /Gbe ns Data hold time t DHW 10 /Gbe ns Data delay time t DD (Note 17) /Gbe 200 ns Data hold time t DHR (Note 17) 10 /Gbe ns Note 17: With load circuit connected VSS CC VOUT VEE VIN VDD OSC1 R OSC2 EXTERNAL POWER SUPPLY ILoad R /G3d 47 k/G57 C /G3d 1.0 /G6dF ILoad /G3d 500 /G6dA Load Circuit D D VDD D D R C DB0 to 7 RL RL /G3d 2.4 k/G57 R /G3d 11 k/G57 C /G3d 130 pF (including wiring capacitance) D /G3d 1S1588 tDD tAH VIL2 VIH2VIH2 VIL2 VIL2 tAS VIH2 VIL2 PWEL VIH2 VIL2 D/I /WR /CE Data Read tAH tEr tDHR VIH2 VIL2 Valid Data VOH2 VOL2 Valid Data VIH2 VIL2 VOH2 VOL2 tcycE tDStEf Data Write tDHW

(1) T6A04A single-chip mode /Gb7/G20Oscillation frequency is at a minimum. /Gb7/G20LCD drive bias is 1/9. /Gb7/G20DC-DC converter is used. D0 to D7 MPU T6A04A /IORQ An /WR /RESET RESET CIRCUIT DECODER 120 /Gb4 64-dot LCD COM1 to COM32 SEG1 to SEG120 COM33 to COM64 DB0 to DB7 /CE D/I /WR /RST V LC1 VLC2 VLC3 VLC4 VLC5 /STB FS1 FS2 M/S EXP R 1 R2 VSS V DD VIN VOUT VEE C1 GND OSC1 1.0 /G6dF C2 OSC2 1.0 /G6dF 0.1 /G6dF VCC 0.1 /G6dF VCC

(2) T6A04A two-chip mode /Gb7/G20Oscillation frequency is at a minimum. /Gb7/G20LCD drive bias is 1/9. /Gb7/G20DC-DC converter is used. T6A04A (master) DB0 to DB7 /CE D/I /WR /RST VLC1 VLC2 VLC3 VLC4 VLC5/STB FS1 FS2 M/S EXP R1 R 2 VSS VDD VIN VOUT VEE C1OSC1 OSC2 CL M FRM COMD D0 to D7 MPU /IORQ An /WR /RESET /CE1 /CE2 DECODER RESET CIRCUIT 240 /Gb4 64-dot LCD P/G66 /G66A /G66B 0.1 /G6dF GND V CC 0.47 /G6dF SEG1 to SEG120 SEG1 to SEG120 COM1 to COM32 COM33 to COM64 T6A04A (slave) DB0 to DB7 /CE D/I /WR /RST VLC1 VLC2 VLC3 VLC4 VLC5 /STB FS1 FS2 M/S EXP R1 R2 VSS VDD VIN VOUT VEE OSC1 OSC2 CL M FRM COMD P/G66 /G66A /G66B VCC VCC 1.0 /G6dF 1.0 /G6dF

/Gb7/G20TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. /Gb7/G20The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. /Gb7/G20Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. /Gb7/G20Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. /Gb7/G20The products described in this document are subject to the foreign exchange and foreign trade laws. /Gb7/G20The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. /Gb7/G20The information contained herein is subject to change without notice. 000707EBERESTRICTIONS ON PRODUCT USE