T54LS574 STMICROELECTRONICS | Alldatasheet
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. em 1 PRELIMINARY DATA . : LS673 - OCTAL D-TYPE LATCH ; WITH 3-STATE OUTPUTS - LS574 - OCTAL D-TYPE FLIP-FLOP . WITH 3-STATE OUTPUTS a DESCRIPTION » aa eT tpts designee for bus organised 8 ‘mina en! soplcations. When Latch coatte 03 fe Plastic Package Ceramic Package transparent to 7 Y . tatu it fa Lon tne data is latched. When the out- vw tm? But Ente gos tthe bus ouput len te high “ PS when is in Mnpedanee state, The LS579 is functionally Kéer- Micro Package Plastic Chip Cartier tical to the L373, but has diferent pinouts. ORDERING NUMBERS: ‘The T54LS/T74L8574 Is an octal D-Type flip-flop TSMLSKXK De Tr4LSxxx C1 Wah 2 Stale Outputs deeloned i hered clock and Mabe +44 TAAL BXX Mt plications. It is of a buffered clock and an oulput Enable common to all flip-flops. The --eeS 8574 is functionally Identical to the L8374 except ——_— for the pinouts. PIN CONNECTION (top view) DUAL IN LINE u«* «i ony Cy DEY sf 3]% oy Ga) ¢ INPUT AND OUTPUT ON OPPOSITE SIDES OF PACKAGE ALLOWING EASY INTERFACE Gly Lss73 4 WITH MICROPROCESSORS on « i}, a ar % af qe veh ory of) Oo Oy 0) Ghd o C a 5) — on a * Ee sf cl, “8874 , i PIN NAMES Ae a DoD Data Inputs ® «a .e Lacich Enable (Active HIGH) Input Glo ow or Clock {Active HIGH going edge) Input he ria () ce Output Enable (Active LOW} Input a8 Oy07 _ | Outputs a 7185-3333 G-10 S00
/ eat ae seak? 67c 19524 GO -46-07-11 AG TALSSENSTA, ; i 1 y; TIALS579/574 CHIP CARRIER sade crutea : &p qe ap gs 4p q« 3 os «ap qs aH Gs. 3p qs 4p ats ap Qa a Gs nonnn nonnan etaee” «elese™ LOGIC SYMBOL 234SeTrH9 TI4SEeTED fel el 1 1 WET SEHD nen esKhoRr ABSOLUTE MAXIMUM RATINGS Symbol Parameter Tae Unit Veo [Supply Votage oso TV M v 0 | Output Vote, Apia to Oui v ib [noe Caert io Inputs | = S08 | ma bo Output Current, into Outputs [| so fm Strsesee in excess of those listed under “Absolute Maximum Ratings” may cause permaneat damage to the device, ‘This Is @ stress rating only and functional operation of the device al these or any conditions in excess of those foowted ne operator eect outs epee le nat haplied. Rapoeure i shechse mastemura rang condone for extanded Is may affect device reliability. 561
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KG Besar 574 = o7C 16525 OT H46-07-11 * - * NY rtussrac i 4 GUARANTEED OPERATING RANGES . Supply Voltage — a Teaseranrave [as v_| ov [a8 v_ [ero stare TAL 857a057 0K [av [tov | sasv | 0 700 X= packages type. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE [__ imine Test Conditions ‘“ esc vote 1 om vi HIGH Voltage Guaranteed HIGH Voltage v [remeron Te | feria Me Input LOW Voltage [84 | |_| 07 _| Guaranteed input LOW Voliage v [| [ot ts Yoo | Input Clamp Oiode Voltage [|= 0.88]-1.8 | Voc=MINIn=-16ma Von | Output HIGH Voltage [64 | 24 | 34 [| Voce MINlon=-400AVm=Vin or | y : [re [ee | as | | Viper rh Yabo Vou | Output Low vortage [54,74 |" [0.25 | 04 | tou=tamA | Voo=MIN, Vey=Vi. oF [re | foas [0s [ hec=zsma | Varner Trum Tang” |v loz ee [20 [VoomMAX,Vourm24v | a \\ Voo = MAX, Viy =2.7V m__[reanercown Tt fa emissincray | ak in [input Cow Current [| [04 [Voo=MAxvin=oev | mA los ‘Output Short Circuit Current ma sca ore [oe] [elo | . co [Power Supaiy Curent |] 40 | VoceMax mA Notes: 1) Conditions for testing, not shown in the Table, are chosen to guarantee operalion under “worst case” conditions. 2) Not more than one output should be shorted at a time. 9) Typical values are at Voc =5.0V, Ta= 25°C 5355 6-12 om x
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J6LEADCERAMIC DIP =S=~—“—SSSSSSSSOSTTTTTTTTTCOCSSSNNTT ; 20LEADPLASTICOIP == ~~ ~~~SCS*“‘;<SCSTS!STSSTSTSTTT 20LEADCERAMICOIP === ~~~SCS<T«;7; 3EFTSC*é<S;7<; ESRF it A aN PARAS :
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, 67C 16546 OD T-90-20 Packages 24-LEAD PLASTIC DIP / . . a= : o . \\ . — 24-LEAD CERAMIC DIP “ “i Pej CHIP CARRIER 20 LEAD PLASTIC eee Ty Hest UMM, ey 1 : - i c+ T =e a sedis jl doy Crna j | wear | 3 al , 9608 8-01 baad
Packages 67C 16547 D0. 1-90-20 SEEN tee Ne i\\s . ‘ i ‘ILM NMINGE MOEA soe NOTE: FOR BOLEAD PLAGTIO DIP MICROPAOKAGE CONTACT SGS 00
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—- = Surface Mounted a 67C 16548 OD T-90-20 ones possible solution to ot uakeg suri ant problem of ~ The mounting system is fully automatic minimization, is that Surface mounted ==. PWB number and the interconnections between components. Integrated circuits In SO (Small them are reduced when the same number of mould in very small plastic packages, = deMloes aro used. ; m in very sm . The advantages given by using these devices are: makes t thormelyy no ee on the PWB Reduction Noise Reduction and improved Frequency the red aor ‘Of PW size aries from 40 10 00% onse the reduction of Ze Vi rom The reduction of the length of the connectin; In comparison with Standard board types. (See wires between the leads and the silicon page package dimensions.) gueranteos @ more homogeneous propogation Assembly Cost Reduction the dhandlend ne, meray ins, with reapect to SO Devices require no preliminary operation prior to mounting and can therefore be easily utilized in Assembly Without Board Holes fully autometio equipment. The devices oe placed on the bosrd and lered. This technology permits a level Increasing Reliability of tolerance in the positioning (autorradley of the The following characteristics lead to a higher level device. For the standard DIP types this must be of reliability with respect to their standard packag- done with great accuracy due to the insertion of ed counter parts: the leads into their holes. ci CONNECTION , . A CES owl ~ ST (ie , ENCAPSULATION