Power Management

T541X337M010AH6720

Texas Instruments

TPS7H1101A-SP 1.5-V to 7-V Input, 3-A, Radiation-Hardened LDO Regulator APRIL 2021

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TPS7H1101A-SP 1.5-V to 7-V Input, 3-A, Radiation-Hardened LDO Regulator

1 Features

5962R13202 (1): – Radiation hardness assurance (RHA) qualified up to total ionizing dose (TID) 100 krad(Si) – ELDRS-free: 100 krad(Si) – Dose rate: 10 mrad(Si)/s – Single event latch-up (SEL) immune to LET = 85 MeV-cm2/mg – SEB and SEGR immune to LET = 85 MeV-cm2/mg – SET/SEFI onset threshold > 40 MeV-cm 2/mg(2)
Specifically designed to always upset low to avoid damage to critical downstream component – SET/SEFI cross-section plot (2)
Ultra-low V IN range: 1.5 V to 7 V
3-A maximum output current
Current share/parallel operation to provide up to 6-A output current
Stable with ceramic output capacitor
±2% accuracy over line, load, and temperature
Programmable soft start through external capacitor
Input enable across all input voltages and power- good output for power sequencing
Ultra-low dropout LDO voltage: 62 mV at 1 A (25°C), VOUT = 1.8 V
Low noise: 20.33 µVRMS, VIN = 2 V, VOUT = 1.8 V at 3 A
PSRR: over 45 dB at 1 kHz
Excellent load/line transient response
Foldback current limit
See the Design and development tab
Thermally-enhanced CFP package, 0.4° C/W R θJC

2 Applications

Space satellite point of load supply for FPGAs, microcontrollers, ASICs, and data converters
Radiation-hardened low-noise linear regulator power supply for RF, VCOs, receivers, and amplifiers
Clean analog supply requirements
Command and data handling (C&DH)
Optical imaging payload
Radar imaging payload
Satellite electrical power system (EPS)

3 Description

The TPS7H1101A-SP is an improved version of the TPS7H1101-SP allowing the use of the enable feature across the entire input voltage range. It is a radiation-hardened LDO linear regulator that uses a PMOS pass element configuration. It operates over a wide range of input voltage, from 1.5 V to 7 V while offering excellent PSRR. The TPS7H1101A-SP features a precise and programmable foldback current limit implementation with a very-wide adjustment range. To support the complex power requirements of FPGAs, DSPs, or microcontrollers, the TPS7H1101A- SP provides enable on and off functionality, programmable soft start, current sharing capability, and a Power Good open-drain output. Device Information PART NUMBER(1) GRADE PACKAGE 5962R1320202V9A KGD Flight Grade RHA 100 krad(Si) 16-Pin CFP 9.60 mm × 11.00 mm Weight: 1.55 g(4) 5962R1320202VXC Flight Grade RHA 100 krad(Si) TPS7H1101HKR/EM Engineering Modules(3) (5) TPS7H1101AHKR/EM Engineering Modules(3) TPS7H1101SPEVM Ceramic Evaluation Board EVM (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) See Radiation Report (SNAA257) for details. (3) These units are intended for engineering evaluation only. They are processed to a noncompliant flow (that is, no burn-in, and so forth) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life. (4) Weight is accurate to ±10%. (5) TPS7H1101HKR/EM with device Date Code newer than 1705 is equivalent to TPS7H1101AHKR/EM using rev A silicon. EN Soft Start Power Good Feed Back GND CIN CSS COUT 3.3 V 5 V TPS7H1101A-SP PCL COMP CS RCS RT RPCL RB VOUT VIN Copyright © 2017, Texas Instruments Incorporated Typical Application Circuit www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: TPS7H1101A-SP TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11.3 Receiving Notification of Documentation Updates..27

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2020) to Revision C (April 2021) Page Changes from Revision A (August 2017) to Revision B (June 2020) Page Changes from Revision * (April 2017) to Revision A (August 2017) Page TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. HKR Package 16-Pin CFP Bottom View Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME NO. SS 1 I/O Soft-start terminal. Connecting an external capacitor slows down the output voltage ramp rate after enable event. EN 2 I Enable terminal. Driving this terminal to logic high enables the device; driving the terminal to logic low disables the device. VIN I Unregulated supply voltage. TI recommends to connect an input capacitor as a good analog circuit practice. PCL 7 I/O Programmable current limit. A resistor to GND sets the overcurrent limit activation point. The range of resistor that can be used on the PCL terminal to GND is 8.2 kΩ to 160 kΩ. GND 8 — Ground/thermal pad.(1) (2) PG/OC 9 O Power Good terminal. PG is an open-drain output to indicate the output voltage reaches 90% of target. PG terminal is also used as indicator when an overcurrent condition is activated. PG pin should have a pull-up resistor to the VOUT pin. CS 10 I/O Current sense terminal. Resistor connected from CS to VIN. CS terminal indicates voltage proportional to output current. CS terminal low: Foldback current limit disabled. CS terminal high: Foldback current limit enabled. VOUT O Regulated output. COMP 15 I/O Internal compensation point for error amplifier. (1) Thermal pad must be connected to GND. (2) Thermal pad and package lid are internally connected to GND. www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS7H1101A-SP

Table 5-2. Bare Die Information DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION BOND PAD THICKNESS 15 mils Silicon with backgrind Ground AlCu 30 kA All dimensions are in microns. TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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Table 5-3. Bond Pad Coordinates in Microns DESCRIPTION PAD NUMBER X MIN Y MIN X MAX Y MAX SS 1 109.89 4046.805 287.19 4224.105 EN 2 109.89 3493.35 287.19 3670.65 VIN 3 1359.99 3021.345 1537.29 3198.645 VIN 4 1359.99 2749.005 1537.29 2926.305 VIN 5 1359.99 2553.705 1537.29 2731.005 VIN 6 1359.99 2281.365 1537.29 2458.665 VIN 7 1359.99 2086.065 1537.29 2263.365 VIN 8 1359.99 1813.725 1537.29 1991.025 VIN 9 1359.99 1618.425 1537.29 1795.725 PCL 10 109.89 660.285 287.19 837.585 GND 11 109.89 319.455 287.19 496.755 GND 12 392.58 109.935 569.88 287.235 VIN 13 1359.99 1346.085 1537.29 1523.385 PG/OC 14 2898.945 379.62 3076.245 556.92 CS 15 2898.945 724.32 3076.245 901.62 VOUT 16 2829.105 1384.695 3006.405 1561.995 VOUT 17 2829.105 1579.815 3006.405 1757.115 VOUT 18 2829.105 1852.335 3006.405 2029.635 VOUT 19 2829.105 2047.455 3006.405 2224.755 VOUT 20 2829.105 2319.975 3006.405 2497.275 VOUT 21 2829.105 2515.095 3006.405 2692.395 VOUT 22 2829.105 2787.615 3006.405 2964.915 VOUT 23 2829.105 2982.735 3006.405 3160.035 COMP 24 2898.945 3519.72 3076.245 3697.02 FB 25 2898.945 3956.535 3076.245 4133.835 www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS7H1101A-SP

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage VIN, PG –0.3 7.5 V FB, COMP, PCL, CS, EN –0.3 VIN + 0.3 Output voltage VOUT, SS –0.3 7.5 V PG terminal sink current 0.001 5 mA Maximum operating junction temperature, TJ –55 150 °C Storage temperature, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TJ Operating junction temperature –55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) (2) (3) TPS7H1101A-SP UNITHKR (CFP)

16 PINS

Rθ JA Junction-to-ambient thermal resistance 24.3 °C/W Rθ JC(top) Junction-to-case (top) thermal resistance 5.5 °C/W Rθ JB Junction-to-board thermal resistance 8.1 °C/W ψJT Junction-to-top characterization parameter 1.3 °C/W ψJB Junction-to-board characterization parameter 8.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Do not allow package body temperature to exceed 265°C at any time or permanent damage may result. (3) Maximum power dissipation may be limited by overcurrent protection. TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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6.5 Electrical Characteristics

6.5 Electrical Characteristics (continued)

1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.35 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG terminal pulled up to VIN with 50 kΩ, over operating temperature range (TJ = –55°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ΔVO DC output load regulation(3) VOUT = 0.8 V, 0 ≤ ILoad ≤ 1 A, TJ = –55°C(2) 0.4 1 mV VOUT = 0.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C(2) 0.6 1.1 VOUT = 0.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C(2) 0.8 1.3 VOUT = 0.8 V, 0 ≤ ILoad ≤ 2 A, TJ = –55°C(2) 0.8 1.8 VOUT = 0.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C(2) 1.3 1.8 VOUT = 0.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C(2) 1.6 2.4 VOUT = 0.8 V, 0 ≤ ILoad ≤ 3 A, TJ = –55°C(2) 1.1 1.9 VOUT = 0.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C(2) 1.9 2.6 VOUT = 0.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C(2) 2.5 3.4 VOUT = 1.2 V, 0 ≤ ILoad ≤ 1 A, TJ = –55°C(2) 0.3 1.2 VOUT = 1.2 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C(2) 0.5 1.3 VOUT = 1.2 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C(2) 0.6 1.3 VOUT = 1.2 V, 0 ≤ ILoad ≤ 2 A, TJ = –55°C(2) 0.8 1.6 VOUT = 1.2 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C(2) 1.1 2.1 VOUT = 1.2 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C(2) 1.5 2.1 VOUT = 1.2 V, 0 ≤ ILoad ≤ 3 A, TJ = –55°C(2) 1 1.7 VOUT = 1.2 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C(2) 1.1 2.4 VOUT = 1.2 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C(2) 2.2 3.5 VOUT = 1.8 V, 0 ≤ ILoad ≤ 1 A, TJ = –55°C(2) 0.1 0.9 VOUT = 1.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C(2) 0.3 0.9 VOUT = 1.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C(2) 0.4 1.2 VOUT = 1.8 V, 0 ≤ ILoad ≤ 2 A, TJ = –55°C(2) 1.4 2.4 VOUT = 1.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C(2) 0.7 1.4 VOUT = 1.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C(2) 0.6 1.9 VOUT = 1.8 V, 0 ≤ ILoad ≤ 3 A, TJ = –55°C(2) 2.5 3.9 VOUT = 1.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C(2) 1.2 2.1 VOUT = 1.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C(2) 1.2 2.5 VOUT = 6.65 V, 0 ≤ ILoad ≤ 1 A, TJ = –55°C(2) 1.5 2.9 VOUT = 6.65 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C(2) 0.4 2.6 VOUT = 6.65 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C(2) 2.8 3.5 VOUT = 6.65 V, 0 ≤ ILoad ≤ 2 A, TJ = –55°C(2) 3.5 5.9 VOUT = 6.65 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C(2) 1.1 4.7 VOUT = 6.65 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C(2) 5.8 8 VOUT = 6.65 V, 0 ≤ ILoad ≤ 3 A, TJ = –55°C(2) 5.6 9.3 VOUT = 6.65 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C(2) 3.7 8 VOUT = 6.65 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C(2) 13 25 VDO Dropout voltage(3) IOUT = 3 A, VOUT = 1.3 V, VIN = VOUT + VDO 210 335 mV ICL Programmable output current limit range VIN = 1.5 V, VOUT = 1.2 V, PCL resistance = 47 kΩ 500 750 mA VIN = 1.5 V, VOUT = 1.2 V, PCL resistance varies 200 3500(4) VCS Operating voltage range at CS (see Section 7)(5) 0 VIN V TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.35 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG terminal pulled up to VIN with 50 kΩ, over operating temperature range (TJ = –55°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CSR Current sense ratio ILOAD / ICS, VIN = 2.3 V, VOUT = 1.9 V, TJ = –55°C, ILOAD ≥ 500 mA 45000 55500 65000 A/ALOAD / ICS, VIN = 2.3 V, VOUT = 1.9 V, TJ = 25°C, ILOAD ≥ 500 mA 45000 52000 59000 LOAD / ICS, VIN = 2.3 V, VOUT = 1.9 V, TJ = 125°C, ILOAD≥ 500 mA 45000 51000 56000 IGND GND terminal current VIN = 1.5 V, VOUT = 1.2 V, IOUT = 2 A 10 16 mA IQ Quiescent current (no load) VIN = VOUT + 0.5 V, IOUT = 0 A 7 10 mA ISHDN Shutdown current 1.5 V ≤ VIN ≤ 7 V, pre and post 100 krad(Si), TJ = 25°C(6) 26 230 µA ISNS, IFB FB/SNS terminal current VIN = 7 V, VOUT = 6.65 V 1 5 nA IEN EN terminal input current VIN = 7 V, VEN = 7 V, VOUT = 6.65 V 20 150 nA VILEN EN terminal input low (disable) 1.5 V < VIN < 7 V 0.55 V VIHEN EN terminal input high (enable) 1.5 V < VIN < 7 V VIN – 0.7 V Eprop Dly Enable terminal propagation delay VIN = 2.2 V, EN rise to IOUTrise 650 1000 µs TEN Enable terminal turn-on delay (delay to PG assertion) VIN = 2.2 V, VOUT = 1.8 V, ILOAD = 1 A, COUT = 220 µF, CSS = 2 nF 1.4 1.6 ms VTHPG PG threshold No load, 0.8 V ≤ VOUT ≤ 6.65 V 86% 90% VTHPGHYS PG hysteresis 1.5 V ≤ VIN ≤ 7 V 2% VOL PG PG terminal output low IPG = 0 mA to –1 mA 120 300 mV ILKGPG PG terminal leakage current VOUT > VTHPG, VPG = 1.2 V 0.2 1.5 µA VOUT > VTHPG, VPG = 7 V 0.5 2.5 ISS SS terminal charge current VIN = 1.5 V to 7 V 2.5 3.5 µA ISSdisb SS terminal disable current VIN = 1.5 V to 7 V 5 10 µA VSS SS terminal voltage (device enabled)(7) VIN = 1.5 V to 7 V 1.232 V VSSdisb SS terminal low-level input voltage to disable device VIN = 1.5 V to 7 V 0.4 V PSRR Power-supply rejection ratio VIN = 2.5 V, VOUT = 1.8 V, COUT = 220 µF 1 kHz 48 dB 100 kHz 25 VN Output noise voltage BW = 10 Hz to 100 kHz, IOUT = 3 A, VIN = 2 V, VOUT = 1.8 V 20.33 µVRMS TSD Thermal shutdown temperature 185 °C (1) The output voltage accuracy of condition at I OUT = 2 A and IOUT = 3 A is specified by characterization, but not production tested. (2) Line and load regulations done under pulse condition for t < 10 ms. (3) The parameter is specified to the limit in characterization, but not production tested. (4) The maximum limit of the I CLparameter is specified to the limit in characterization, but not production tested. (5) To insure foldback is enabled, V CS must be > 0.9 · VFB. (6) This maximum limit applies to SMD 5962R13202 post 100-krad(Si) test at 25°C. (7) Any external pullup voltage should not exceed 1.188 V. www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS7H1101A-SP

6.6 Typical Characteristics

0.602 0.603 0.604 0.605 0.606 0.607 0.608 -55 -35 -15 5 25 45 65 85 105 125 VIN = 1.5 V VIN = 7 V Junction Temperature ( °C) Feedback Voltage (V) Figure 6-1. Feedback Voltage vs Temperature ±55 ±35 ±15 5 25 45 65 85 105 125 Quiescent Current (mA) Junction Temperature (C) C014 VIN = 1.5 V VIN = 7 V Figure 6-2. Quiescent Current vs Temperature ±55 ±35 ±15 5 25 45 65 85 105 125 Ground Current (mA) Junction Temperature (C) C015 No Load Load = 2 A Figure 6-3. Ground Current vs Temperature 120 160 200 240 280 320 -55 -35 -15 5 25 45 65 85 105 125 Dropout Voltage (mV) Junction Temperature (°C) VOUT = 1.8 V Load = 3 A Figure 6-4. Dropout Voltage vs Temperature 100 -55 -35 -15 5 25 45 65 85 105 125 Shutdown Current (uA) Junction Temperature ( C) ° C017 VIN = 1.5 V VIN = 7 V Figure 6-5. Shutdown Current vs Temperature 100 -55 -35 -15 5 25 45 65 85 105 125 PG Threshold (%) Junction Temperature ( C) ° C018 Figure 6-6. PG Threshold vs Temperature TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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6.6 Typical Characteristics (continued)

Frequency (Hz) Ripple Rejection (dB) 10 100 1000 10000 100000 100 No load VIN = 2.5 V VOUT = 1.8 V Figure 6-7. Power Supply Ripple Rejection vs Frequency www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS7H1101A-SP

7 Detailed Description

7.1 Overview

The TPS7H1101A-SP is 3-A, 1.5-V to 7-V LDO linear regulator that uses PMOS pass element configuration. It uses TI’s proprietary process to achieve low noise, high PSRR combined with high-thermal performance in a 16-pin ceramic flatpack package (HKR). A number of features are incorporated in the design to provide high reliability and system flexibility. Current foldback, current limit, and thermal protection are incorporated in the design to make it viable for space environments. The device also has a current sense monitoring feature. A resistor connected from the current sense (CS) terminal to VIN indicates voltage proportional to the output current. Section 8.2.1.3 provides a detailed description of this feature. When CS is pulled high to voltage greater than 90% Vref (0.544 V), foldback current limit is enabled. Pulling CS below 0.544 V disables the foldback current limit. A resistor connected from the programmable current limit (PCL) terminal to ground sets the overcurrent limit activation point. When overcurrent limit activation point is reached, it results in the LDO going into current provides a detailed description of this feature. TPS7H1101A-SP incorporates thermal protection, which disables the output when the junction temperature rises to approximately 185°C, allowing the device to cool. Cycling limits the dissipation of the regulator, protecting it from catastrophic damage as a result of overheating. To provide system flexibility for demanding current needs, the LDO can be configured in parallel operation as An enable feature is incorporated in the design allowing the user to enable or disable the LDO. Power Good (PG), is an open-drain connection, indicating status of the output voltage regulation. These provide the customers system flexibility in monitoring and controlling the LDO operation.

7.2 Functional Block Diagram

1.2 V PG 1.1*VREF 0.9*VREF 2 mA RBOT RTOP TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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7.3 Feature Description

7.3.1 Soft Start

Connecting a capacitor (C SS) from the SS terminal to GND slows down the output voltage ramp rate. The soft-start capacitor charges up to 1.2 V, with a threshold of VFB. C =SS /c190t ISS SS/c183 VFB (1) where

t ss = soft-start time
I ss = 2.5 µA
V FB = VREF = 0.605 V

7.3.2 Power Good (PG)

Power Good terminal (9) is an open-drain connection and can be used to sequence multiple LDOs. Figure 7-1 shows typical connection. The PG terminal will be pulled low until the output voltage reaches 90% of its maximum level. At that point, the PG pin will be pulled up. Since the PG pin is open drain, it can be pulled up to any voltage as long as it does not exceed the absolute max of 7.5 V listed in Section 6.5. PGEN SS TPS7H1101A-SP VIN PGEN SS TPS7H1101A-SP VIN Copyright © 2017, Texas Instruments Incorporated Figure 7-1. Sequencing LDOs With Power Good Note For PSpice models, WEBENCH, and reference design, see the Design & development tab of the product folder. 1. PSpice transient model (switching, transient, and stability simulations) 2. PSpice Worst Case Analysis (WCA) model (radiation and aging stability – Bode plot)

7.4 Device Functional Modes

7.4.1 Enable/Disable

For V IN from 1.5 V to 7 V, TPS7H1101A-SP can be disabled by pulling the enable terminal to logic low at a minimum of 0.7 V. Enable cannot exceed V IN by more than 0.3 V, and in most cases, the enable terminal is connected to VIN. www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS7H1101A-SP

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TPS7H1101A-SP LDO linear regulator is targeted space environment applications. This regulator has various features such as low dropout, soft start, output current foldback, high-side current sensing (where sensing voltage at CS pin provides voltage proportional to output current), and current sharing.

8.1.1 Stability

Bode plots are a standard approach in assessing stability. This approach requires a single feedback path where an AC signal is injected across a resistor (typically 50 Ω) and measurements are taken on either side of the resistor as shown in Figure 8-1. From this measurement, loop gain and phase plots can be generated. Crossover frequency, ƒC, is defined as the frequency where the magnitude of the loop gain is unity and phase margin is evaluated at the crossover frequency ƒC. TPS7H1101A-SP 0.6V VREF FB RT RB COUT RLOAD RESR CIN RESR VIN OUTIN CCOMP 50 gm COMP Signal injection Figure 8-1. Conventional Bode Plot With Simplified Feedback Loops However, it is important the AC signal is injected as shown in Figure 8-1. This injection point ensures that the feedback signal goes through both the outer loop (consisting of the top feedback resistor, R T) and the inner loop (consisting of the compensation capacitor, CCOMP). If the only the outer loop is measured, the resulting crossover frequency will be lower which would indicate a poorer transient response than reality. Therefore, it is best to inject the measurement signal at a point where it goes through both loops. If this is not possible, the two loops may be measured independently and added using the superposition principle. Furthermore, the stability of the device can be qualitatively validated by applying a step load to the output and observing the response. The SPICE models for the device can be found on the TPS7H1101A-SP product page. To simulate impedance measurements, the transient model should be used. TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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8.2 Typical Application

3.3 V 5 V TPS7H1101A-SP PCL COMP CS RCS RT RPCL RB VOUT VIN Copyright © 2017, Texas Instruments Incorporated Figure 8-2. Typical Application Circuit www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS7H1101A-SP

8.2.1 Detailed Design Procedure

8.2.1.1 Adjustable Output Voltage (Feedback Circuit)

The output voltage of the TPS7H1101A-SP can be set to a user-programmable level between 0.8 V and 6.65 V. Achieve this by using a resistor divider connected between V OUT, FB, and GND terminals. R TOP connected between VOUT and VFB, and RBOTTOM connected between VFB and GND. Use Equation 2 to determine VOUT. V =OUT ( )R + R VTOP BOTTOM FB /c183/c190RBOTTOM (2) where

V FB = 0.605 V Table 8-1. Example Resistor Values for Typical Voltages VOUT Standard 1% Resistors Standard 0.1% Resistors RTOP RBOTTOM RTOP RBOTTOM 1 V 13.7 kΩ 21 kΩ 12.6 kΩ 19.3 kΩ 1.2 V 11.3 kΩ 11.5 kΩ 11.8 kΩ 12 kΩ 1.8 V 23.2 kΩ 11.8 kΩ 32 kΩ 16.2 kΩ 4 V 13.3 kΩ 2.37 kΩ 31.2 kΩ 5.56 kΩ 5 V 11.5 kΩ 1.58 kΩ 16.2 kΩ 2.23 kΩ 6 V 90.9 kΩ 10.2 kΩ 10.7 kΩ 1.2 kΩ

8.2.1.2 PCL

PCL resistor, RPCL, sets the overcurrent limit activation point and can be calculated per Equation 3. RPCL = (CSR × VREF) / (ICL – 0.0403) (3) where

V REF = 0.605 V
I CL = Programmable current limit (A)
Current sense ratio (CSR) is the ratio of output load current to I CS; typical value of the CSR is 52000
Offset value 0.0403 is a fixed offset derived from internal keep-alive biasing Figure 8-3 shows the output load current (I LOAD) versus PCL terminal current (I PCL) varied with minimum and maximum range of CSR values by temperature. The R PCL resistor should be chosen to set the worst case I LOAD across system normal operating load and temperature range without reaching overcurrent activation point of IPCL
RPCL ≥ VREF. Additionally, a suitable resistor RCS must be chosen to ensure the CS terminal is within its operating range of 0.3 V to VIN and VCS needs to be greater than 0.9 · VREF (0.544 V) to insure foldback remains enabled when current activation point is triggered. TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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The maximum PCL is 3.5 A. The range of resistor that can be used on the PCL terminal to GND is 8.2 k Ω to 160 kΩ. It is not recommended to use overcurrent limit activation thresholds of less than 500 mA due to internal bias offset currents representing a larger percentage of total IPCLcurrent and therefore additional error. IPCL (A) ILOAD (A) ILOAD Vs IPCL across CSR range 0x100 10x10-6 20x10-6 30x10-6 40x10-6 50x10-6 60x10-6 70x10-6 80x10-6 CSR_ Min CSR: ILOAD = 45000 * IPCL +0.0403 25c Nom CSR: ILOAD = 52000 * IPCL +0.0403 125c Max CSR: ILOAD = 56000 * IPCL +0.0403 -55c Max CSR: ILOAD = 65000 * IPCL +0.0403 Figure 8-3. ILOAD (A) vs IPCL (A)

8.2.1.3 High-Side Current Sense

Figure 8-4 shows the cascode NMOS current mirror. V CS must be ≥ 0.3 V for proper biasing. Additionally V CS must be greater than 0.9 · V REF (0.544 V) if foldback current limiting is intended to be enabled. The following example shows the typical calculation of RCS. LOAD offset CS I + II = CSR (4) R =CS V VIN CS-/c190/c190ICS (5) where

I LOAD is the output load current
CSR is the current sense ratio
I offset is internal keep-alive bias current times CSR
I offset = 5 µA · CSR When VIN = 2.3 V, select VCS = 2.05 V, ILOAD = 3 A, CSR = 52000, and I offset = 0.26 A, then I CS = 62.69 µA and RCS = 3.99 kΩ. www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS7H1101A-SP

Figure 8-4. Cascode NMOS Current Mirror For TPS7H1101A-SP, Figure 8-5 shows a typical curve V CS vs I OUT for V IN = 2.28 V and R CS = 3.65 k Ω. A resistor connected from the CS terminal to VIN indicates voltage proportional to the output current. Monitoring current in the CS terminal (I CS vs I LOAD) indicates the current sense ratio between the main PMOSFET and the current sense MOSFET as shown in Figure 8-6. Additionally Figure 8-6 shows the linearity of the CSR ratio across V CS pin voltage range of 0.3 V to V IN. VCS must be ≥ 0.3-V minimum to keep circuit properly biased. Figure 8-7 shows ILOAD vs ICS across the full range of CSR values. 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 CS Pin Voltage (V) Load Current (A) C003 VIN = 2.3 V VOUT = 1.8 V y = –0.078x + 2.2853 Figure 8-5. VCS (V) vs I LOAD (A) ICS (uA) ILOAD (A) 0 10 20 30 40 50 60 70 80 0.5 1.5 2.5 3.5 VCS_ ICS (uA) vs ILOAD at VCS = 0.3V ICS (uA) vs ILOAD at VCS = 2.3V ICS (uA) vs ILOAD at VCS = 5V VIN = 2.3 V VOUT = 1.8 V Figure 8-6. IOUT (A) vs ICS (A) TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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ICS (A) ILOAD (A) ILOAD Vs ICS across CSR range 0x100 10x10-6 20x10-6 30x10-6 40x10-6 50x10-6 60x10-6 70x10-6 80x10-6 CSR_ Min CSR: ILOAD = 45000(ICS - 5uA) 25c Nom CSR: ILOAD = 52000(ICS - 5uA) -55c Max CSR: ILOAD = 65000(ICS - 5uA) 125c Max CSR: ILOAD = 56000(ICS - 5uA) Figure 8-7. IOUT (A) vs ICS (A)

8.2.1.4 Current Foldback

The TPS7H1101A-SP has a current foldback feature which can be enabled when the CS terminal is greater than 0.9 · VREF (0.544 V). Pulling CS below this threshold disables the foldback current limit. If the foldback current limit is disabled, then the LDO will begin regulating again as soon as the current falls below the clamp threshold. 2. With foldback current limit enabled, when current limit trip point is activated, a. Output voltage drops low, and b. Output current folds back to approximately 50% of the current limit trip point. This results in minimizing the power loss under fault conditions. Monitoring the voltage at the CS terminal indicates voltage proportional to the output current. It is important to note that the current sense voltage range on CS pin must be designed to stay above the 0.9 · VREF threshold to insure foldback is not inadvertently disabled at high currents. www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS7H1101A-SP

8.2.1.5 Transient Response

Figure 8-8, Figure 8-9, and Figure 8-10 indicate the transient response behavior of the LDO for 50% step load change. Channel 1: Input voltage Channel 3: Step load in current Channel 4: Output voltage overshoot/undershoot Figure 8-8. Load Transient Response: Step Load 0.1 to 1.6 A, VIN = 2.3 V, VOUT = 1.8 V Figure 8-9. Expanded View Overshoot Figure 8-10. Expanded View Undershoot TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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8.2.1.6 Current Sharing

For demanding load requirements, multiple LDOs can be paralleled as indicated in Figure 8-12. In parallel mode, the CS terminal of LDO1 must be connected to the PCL terminal of LDO2 via a series resistor, R CL, and CS terminal of LDO2 must be connected to PCL terminal of LDO1 via series resistor, R CL. The typical value of R CL in parallel operation is 3.75 k Ω for current limit > 6 A. In parallel configuration, R CL (resistor from PCL to GND) and RCS (resistor from CS terminal to V IN) must be left open (unpopulated). The R CL value must be selected so that the operating condition of the CS terminal is maintained, as specified in Section 6.5. VCS must be greater than 0.3 V to insure proper current sense operation. The current from PCL through RCL of LDO1 is determined by the output load current of LDO2 divided by the CSR. Hence, the voltage at CS terminal of the LDO1 is 0.605 V – ((output load current of LDO2 + 0.2458) / CSR × RCL). Alternately, it can also provide twice the output current to meet system needs. When using two LDOs in parallel operation for higher output load current, use POL TPS50601-SP as an input source. 35.00 40.00 45.00 50.00 55.00 60.00 65.00 0 1 2 3 4 5 6 % of total Load Output Current LDO1 LDO2 Figure 8-11. LDO Current Share www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS7H1101A-SP

Figure 8-12. Block Diagram (Parallel Operation) TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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8.2.1.7 Compensation

Figure 8-13 shows a generic block diagram for TPS7H1101A-SP LDO with external compensation components. LDO incorporates nested loops, thus providing the high gain necessary to meet design performance. VOUT CO RESR VIN RINESR CIN VREF = 0.605 V E/A RL Buffer CCOMP CFF RTOP RBOT CX Figure 8-13. TPS7H1101A-SP Compensation Resistor divider composed of R top and Rbottom determine the output voltage set points as indicated by Equation Output capacitor COUT introduces a pole and a zero as shown in the following. F =p_co /c1901

2 C/c183 /c183/c112 o L/c183R

(6) F =z_co /c1901

2 C/c183 /c183/c112 o esr/c183C

(7) The TPS7H1101A-SP was designed so that the ESR of the output capacitor will not have a strong influence on the response of the LDO. However, an optional capacitor, C x, can be added in parallel with the bottom feedback resistor to introduce a pole to cancel Fz_co. Equation 8 shows how to calculate the location of the pole introduced by Cx. To cancel the zero directly, Fp should be equal to Fz_co. F =p /c1901

2 C/c183 /c183/c112 x bottom/c183R

(8) Cx is calculated to be 1000 pF for Co = 220 µF, Cesr = 45 mΩ, and Rbottom = 10 kΩ. Figure 8-13 also includes a place holder for a feed forward capacitance C ff. Use of feed forward compensation can be more advantageous than use of C x. Please reference application note Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator for additional information on usage of CFF. Internal compensation in the LDO cancels the output capacitor pole introduced by COUT and RL. Ccomp introduces a dominant pole at low frequency. TI recommends that a Ccomp value of 10 nF.

8.2.1.8 Output Noise

Output noise is measured using an HP3495A. Figure 8-14 and Figure 8-15 show noise of the TPS7H1101A-SP in µV/√ Hz vs frequency. www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS7H1101A-SP

0.01 0.1 10 100 1,000 10,000 100,000 Noise (µV/ Hz) Frequency (Hz) VIN = 2 V VOUT = 1.8 V at 3 A CIN = 220 µF CLOAD = 220 µF Figure 8-14. RMS Noise (10 Hz to 100 kHz) = 20.33 µVrms 0.01 0.1 10 100 1000 10000 100000 Noise ( μV/ Hz) Frequency (Hz) VIN = 7 V VOUT = 6.7 V at ILOAD = 3 A CIN = 220 µF CLOAD = 220 µF Figure 8-15. RMS Noise (10 Hz to 100 kHz) = 31.68 µVrms

8.2.1.9 Capacitors

TPS7H1101A-SP requires the use of a combination of tantalum and ceramic capacitors to achieve good volume to capacitance ratio. Table 8-2 highlights some of the capacitors used in the device. TI recommends to follow proper derating guidelines as recommended by the capacitor manufacturer based upon output voltage and operating temperature. Note that polymer-based tantalum capacitors must be derated to at least 60% of rated voltage, whereas manganese oxide (MnO 2) based tantalum capacitors should be derated to 33% of rated voltage depending upon the operating temperature. TI recommends to use a tantalum capacitor along with a 0.1-µF ceramic capacitor. The device is stable for input and output tantalum capacitor values of 10 µF to 220 µF with the ESR range of 10 m Ω to 2 Ω. However, the dynamic performance of the device varies based on load conditions and the capacitor values used. TI recommends a minimum output capacitor of 22 µF with ESR of 1 Ω or less to prevent oscillations. X7R dielectrics are preferred. See Table 8-2 for various capacitor recommendations. TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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Table 8-2. TPS7H1101A-SP Capacitors CAPACITOR PART NUMBER CAPACITOR DETAILS (CAPACITOR, VOLTAGE, ESR) TYPE VENDOR T493X107K016CH612A(1) 100 µF, 16 V, 100 mΩ Tantalum - MnO2 Kemet T493X226M025AH6x20(1) 22 µF, 25 V, 35 mΩ Tantalum - MnO2 Kemet T525D476M016ATE035(1) 47 µF, 10 V, 35 mΩ Tantalum - Polymer Kemet T540D476M016AH6520(1) 47 µF, 16 V, 20 mΩ Tantalum - Polymer Kemet T525D107M010ATE025(1) 100 µF, 10 V, 25 mΩ Tantalum - Polymer Kemet T541X337M010AH6720(1) 330 µF, 10 V, 6 mΩ Tantalum - Polymer Kemet T525D227M010ATE025(1) 220 µF, 10 V, 25 mΩ Tantalum - Polymer Kemet T495X107K016ATE100(1) 100 µF, 16 V, 100 mΩ Tantalum - MnO2 Kemet CWR29FK227JTHC(1) 220 µF, 10 V, 180 mΩ Tantalum - MnO2 AVX THJE107K016AJH 100 µF, 16 V, 58 mΩ Tantalum AVX THJE227K010AJH 220 µF, 10 V, 40 mΩ Tantalum AVX SMX33C336KAN360 33 µF, 25 V Stacked ceramic AVX SR2225X7R335K1P5#M123 3.3 µF, 25 V, 10 mΩ Ceramic Presidio Components Inc (1) Operating temperature is –55°C to 125°C.

8.2.2 Application Curves

0 0.5 1 1.5 2 2.5 3 Dropout Voltage (mV) I (A)OUT -55 ° C 25 ° C 125 ° C Figure 8-16. VDO vs IOUT www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS7H1101A-SP

9 Power Supply Recommendations

This device is designed to operate with an input voltage supply up to 7 V. The minimum input voltage should provide adequate headroom greater than the dropout voltage for the device to have a regulated output. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance.

10 Layout

10.1 Layout Guidelines

For best performance, all traces should be as short as possible, and no longer than 5 cm.
Use wide traces for IN, OUT and GND to minimize the parasitic electrical effects.
Place the output capacitors (COUT) as close as possible to the OUT pin of the device.

10.2 Layout Example

Main GND layer(s) plane Vias from top layer thermal pad GND to main GND plane(s) CapCap CapCap R R C C CapCap R To CS sense R To PG/OC sense CapCap CapCap R R Via to GND TPS7H1101A-SP1 SS 2 EN

3 VIN

4 VIN

5 VIN

6 VIN

7 PCL

8 GND

Figure 10-1. PCB Layout Example TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 www.ti.com

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Device Nomenclature

RHA Radiation hardness assurance for space systems 5962R13202 Same device as TPS50601-SP, shown with standard microcircuit drawing (SMD) TPS7H1101A-SP Same device as 5962R10221, shown with TI package drawing

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note (SBVA042)
Texas Instruments, TPS7H1101‐SP TID and SEE radiation report (SNAA257)

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPS7H1101A-SP SLVSDW6C – APRIL 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS7H1101A-SP

www.ti.com 10-Jun-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962R1320202V9A ACTIVE XCEPT KGD 0 70 RoHS & Green Call TI N / A for Pkg Type -55 to 125 Samples 5962R1320202VXC ACTIVE CFP HKR 16 1 RoHS-Exempt & Green NIAU N / A for Pkg Type -55 to 125 5962R1320202VXC TPS7H1101-RHA Samples TPS7H1101AHKR/EM ACTIVE CFP HKR 16 1 RoHS-Exempt & Green NIAU N / A for Pkg Type 25 to 25 TPS7H1101AHKR/EM EVAL ONLY Samples TPS7H1101AY/EM ACTIVE XCEPT KGD 0 5 RoHS & Green Call TI N / A for Pkg Type 25 to 25 Samples TPS7H1101HKR/EM ACTIVE CFP HKR 16 1 RoHS-Exempt & Green NIAU N / A for Pkg Type 25 to 25 TPS7H1101HKREM Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 10-Jun-2022 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

*All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) 5962R1320202VXC HKR CFP 16 1 506.98 26.16 6220 NA TPS7H1101AHKR/EM HKR CFP 16 1 506.98 26.16 6220 NA TPS7H1101HKR/EM HKR CFP 16 1 506.98 26.16 6220 NA PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2022 Pack Materials-Page 1

www.ti.com PACKAGE OUTLINE C (6.59) 2.416 1.850 14X 1.27 8.95 8.656.74 6.44 16X 0.482 0.382 2X 8.89 1.19 0.69 0.177 0.097 25.142 24.642 B 9.88 9.38 A 11.26 10.76 (9.14) (10.41) CFP - 2.416 mm max heightHKR0016A CERAMIC DUAL FLATPACK 4226020/B 12/2020 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermetically sealed with a metal lid. Lid is connected to Heatsink and pin 8 (GND). 4. The terminals are gold plated. 5. Falls within MIL-STD-1835 CDFP-F11A. 1 16 PIN 1 ID

0.2 C A B

SCALE 0.700 METAL LID 1 16 8 9 HEATSINK PIN 1 ID

www.ti.com EXAMPLE BOARD LAYOUT (8.8) (6.59) ( 0.2) TYP (1.2) TYP (0.6) (1.2) TYP (0.6) CFP - 2.416 mm max heightHKR0016A CERAMIC DUAL FLATPACK 4226020/B 12/2020 HEATSINK LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:10X PKG PKG

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