Memory

T436416D-5SG

Taiwan Memory Technolog...

4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM

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TM Technology Inc. reserves the right P. 1 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A SDRAM 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM

FEATURES

••• Fast access time from clock: 4.5/5/5.4 ns
••• Fast clock rate: 200/166/143 MHz
••• Fully synchronous operation
••• Internal pipelined architecture
••• 1M word x 16-bit x 4-bank
••• Programmable Mode registers - CAS# Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function
••• Auto Refresh and Self Refresh
••• 4096 refresh cycles/64ms
••• CKE power down mode
••• Single +3.3V ± 0.3V power supply
••• Interface: LVTTL
••• 54-pin 400 mil plastic TSOP II package
60-Ball, 6.4 mm x 10.1 mm TFBGA package Key Specifications T436416D - 5/6/7 tCK3 Clock Cycle time(min.) 5/6/7 ns tAC3 Access time from CLK(max.) 4.5/5/5.4/ ns tRAS Row Active time(min.) 35/42/45 ns tRC Row Cycle time(min.) 50/60/63 ns

ORDERING INFORMATION

Part Number Frequency Package T436416D-5S/-5C 200MHz TSOP II / TFBGA T436416D-5SG/-5CG 200MHz TSOP II / TFBGA T436416D-6S/-6C 166MHz TSOP II / TFBGA T436416D-6SG/-6CG 166MHz TSOP II / TFBGA T436416D-7S/-7C 143MHz TSOP II / TFBGA T436416D-7SG/-7CG 143MHz TSOP II / TFBGA S : indicates TSOPII Package, C : indicates TFBGA Package, G : indicates Pb Free Package GRNERAL DESCRIPTION The T436416D SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The T436416D provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.

TM Technology Inc. reserves the right P. 2 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A PIN ARRANGEMENT (Top View) TFBGA Top View TOSPII Top View DQ1 V DD V DDQ DQ11 DQ10 V SSQ DQ2 DQ15 DQ14 Vss 2827 DQ3 DQ0 V DDQ DQ4 DQ5 V SSQ DQ6 RAS CS BA1 A10/AP V DD V SSQ DQ13 DQ12 DQ9 UDQM N. C CLK CKE Vss DQ7 V DD LDQM DQ8 Vss N. C/RFU W E CAS 54PINTSOP(II) (400mil x 875mil) (0.8 mm PIN PITCH) V DDQ BA0 V DDQ V SSQ A11 A B C D E F G H V D D N C A 5 A 7 V S S A 8 D Q 6 D Q 7 C L K D Q 8 D Q 9 D Q 3 D Q 1 N C D Q 1 5 D Q 1 4 D Q 1 2 V D D Q D Q 4 V D D Q D Q 1 1 V D D Q D Q 5 V S S Q U D Q M V S S Q D Q 1 0 V S S Q A 6 V D D C K E A 9 A 0 A 1 0 B A1 B A0 V S S Q D Q 1 3 N C N C N C A 1 1 V S S A 4 N C N C V D D Q D Q 0 D Q 2 N C N C N C L D Q M W E # C A S # R A S # C S # A 3 A 2 A 1 J K L M N P R 1 2 3 4 5 6 7

TM Technology Inc. reserves the right P. 3 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A BLOCK DIAGRAM Data Input Register I/O ControlOutput Buffer1M x 16 1M x 16 Sense AMP Column Decoder Latency & Burst Length Programming Register Bank Select Row Buffeer Refresh Counter Row Decoder Address Register Col. Buffer Timing Register DQi LDQM LWE LDQM LWCBRLCAS LWELCBRLRAS L(U)DQMRASCSCKECLK LCBR LRAS ADD CLK LCKE CAS WE 1M x 16 1M x 16

TM Technology Inc. reserves the right P. 4 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Pin Descriptions (Table 1. Pin Details of T436416D) Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. Bank Select: BA0,BA1 input select the bank for operation. BA1 BA0 Select Bank 0 0 BANK #A 0 1 BANK #B 1 0 BANK #C BA0,BA1 Input 1 1 BANK #D A0-A11 Input Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 1M available in the respective bank. During a Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op- code during a Mode Register Set command. CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. RAS# Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. CAS# Input Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH." WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. LDQM, UDQM Input Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode. DQ0-DQ15 Input / Output Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are maskable during Reads and Writes. NC/RFU - No Connect: These pins should be left unconnected. VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V ) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.( 0 V ) VDD Supply Power Supply: +3.3V ± 0.3V VSS Supply Ground

the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) )

CKEn signal is input level when commands are provided.

CKEn-1 signal is input level one clock cycle before the commands are provided.

These are states of bank designated by BS signal.
Device state is 1, 2, 4, 8, and full page burst operation.
Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle, device state is clock suspend mode.

TM Technology Inc. reserves the right P. 6 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Commands

1 BankActivate

(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address) The BankActivate command activates the idle bank designated by the BA0,1 signals. By latching the row address on A0 to A11 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of t RCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). The minimum time interval between successive BankActivate commands to the same bank is defined by t RC(min.). The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks. t RRD(min.) specifies the minimum time required between activating different banks. After this command is used, the Write command and the Block Write command perform the no mask write operation. CLK ADDRESS T0 T 1 T2 T3 Tn+3 Tn+4 Tn+5 Tn+6 COMMAND RAS# - CAS# delay ( tRCD) RAS# - RAS# delay time ( tRRD) RAS# Cycle time (tRC) Bank A Row Addr. Bank A Col Addr. Bank B Row Addr. Bank A Row Addr. Bank A Activate R/W A with AutoPrecharge Bank B Activate Bank A Activate AutoPrecharge Begin : "H" or "L" BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)

2 BankPrecharge command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care) The BankPrecharge command precharges the bank designated by BA signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after t RAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by t RAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated again.

3 PrechargeAll command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0-A9 and A11 = Don't care) The PrechargeAll command precharges all banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state.

4 Read command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A7 = Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least t RCD(min.) before the Read command is issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS# latency after the issue of the Read command. Each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).

TM Technology Inc. reserves the right P. 7 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A CLK COMMAND CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's T 0T 1 T 2T 3 T 4T 5 T 6T 7 T 8 READ A NOP NOP NOP NOP NOP NOP NOP NOP DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure). CLK COMMAND CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's T 0T 1 T 2T 3 T 4T 5 T 6T 7 T 8 READ A READ B NOP NOP NOP NOP NOP NOP NOP DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus contention. READ A NOP NOP NOP NOP WRITE B NOP NOP CLK DQM COMMAND DQ's T 0T 1 T 2T 3 T 4T 5 T 6T 7 T 8 NOP DOUT A0 DINB 0 DINB1 DINB 2Must be Hi-Z before the Write Com mand : "H" or "L" Read to Write Interval (Burst Length ≥≥≥≥ 4, CAS# Latency = 3)

TM Technology Inc. reserves the right P. 8 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A CLK DQM COMMAND T 0T 1 T 2T 3 T 4T 5 T 6T 7 T 8 NOP NOP NOP NOP NOP NOPBANKA ACTIVATE DIN A0 DIN A1 DIN A2 DIN A3

1 Clk Interval

CAS# latency=2 tCK2, DQ's READ A WRITE A : "H" or "L" Read to Write Interval (Burst Length ≥≥≥≥ 4, CAS# Latency = 2) CLK DQM COMMAND T 0T 1 T 2T 3 T 4T 5 T 6T 7 T 8 NOP READ A NOP WRITE B NOP NOP NOP DIN B0 DIN B1 DIN B2 DIN B3 CAS# latency=2 tCK2, DQ's NOP NOP : "H" or "L" Read to Write Interval (Burst Length ≥≥≥≥ 4, CAS# Latency = 2) A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll command is issued in different CAS# latency. CLK COMMAND CAS# latency=2 tCK2, DQ's T 0 T 1 T 2 T 3T 4 T 5T 6 T 7T 8 READ A NOP NOP NOP NOP Activate NOPNOP Precharge CAS# latency=3 tCK3, DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 ADDRESS tRP Bank, Col A Bank(s) Bank, Row Read to Precharge (CAS# Latency = 2, 3)

TM Technology Inc. reserves the right P. 9 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A

5 Read and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A7 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored.

6 Write command

(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A7 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least t RCD(min.) before the Write command is issued. During write bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless another command is initiated. The burst length and burst sequence are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). CLK COMMAND T 0T 1T 2T 3T 4T 5 T 6T 7 T 8 DIN A 3 NOP WRITE A NOP NOP NOP NOP NOPNOP NOP DIN A 0 DIN A1 DIN A 2DQ0 - DQ3 The first data element and the write are registered on the same clock edge. Extra data is masked. don't care Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3) A write burst without the auto precharge function may be interrupted by a subsequent Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure). CLK COMMAND T 0T 1 T 2T 3 T 4T 5 T 6T 7 T 8 DIN B 2 NOP WRITE A NOP NOP NOP NOP NOPWRITE B NOP DIN A 0 DIN B 0 DIN B1DQ's DIN B 3 Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not be executed.

TM Technology Inc. reserves the right P. 10 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A CLK COMMAND T 0T 1 T 2T 3 T 4T 5 T 6T 7 T 8 NOP WRITE A NOP NOP NOP NOP NOPREAD B NOP DIN A0 don't care DOUT B2DOUT B0 DOUT B1 DOUT B3 DIN A0 don't care don't care DOUT B2DOUT B0 DOUT B1 DOUT B3 Input data for the write is masked. Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention. CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). CLK T 0T 1T 2T 3T 4T 5 T 6 WRITECOMMAND BANK (S) ROW NOP NOPPrecharge NOP NOP Activate BANK COL n DIN n DIN n + 1 DQM ADDRESS DQ tWR tRP : don't care Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2. Write to Precharge

7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A7

= Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored.

TM Technology Inc. reserves the right P. 11 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A CLK COMMAND T 0T 1 T 2T 3 T 4T 5 T 6T 7 T 8 NOP NOP NOP NOP NOPNOP NOP CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DIN A0 DIN A1 DIN A0 DIN A1 tDAL= tWR + tRP Beg in AutoPre charge Bank can be reactivated at completion of tDAL Bank A Activa te Write A AutoPrec harge tDAL tDAL Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)

8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)

The mode register stores the data for controlling the various operating modes of SDRAM. The Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the mode register. One clock cycle is required to complete the write in the mode register (refer to the following figure). The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state.

TM Technology Inc. reserves the right P. 12 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A RAS# T 0 T 1 T 2 T 3 T 4T 5 T 6T 7 T 8T 9 T 1 0 CL K CKE CS# CAS# WE # A11 A10 A0-A9 DQ M DQ tCK2 Clock min. Address Key tRP Hi -Z PrechargeAll Mode Register Set Command Any Command Mode Register Set Cycle (CAS# Latency = 2, 3) The mode register is divided into various fields depending on functionality. Address BS0,1 A11,10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function RFU* RFU* WBL Test Mode CAS Latency BT Burst Length *Note: RFU (Reserved for future use) should stay “0” during MRS cycle.

Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page. A2 A1 A0 Burst Length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Full Page

TM Technology Inc. reserves the right P. 13 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A

Burst Type Field (A3) The Burst Type can be one of two modes, Interleave Mode or Sequential Mode. A3 Burst Type

0 Sequential

1 Interleave

--- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. When the value of column address, (n + m), in the table is larger than 255, only the least significant 8 bits are effective. Data n 0 1 2 3 4 5 6 7 - 255 256 257 - Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 - 2 words: Burst Length 4 words: 8 words: Full Page: Column address is repeated until terminated. --- Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Column Address Burst Length Data 0 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A7 A6 A5 A4 A3 A2 A1 A0# 4 words Data 2 A7 A6 A5 A4 A3 A2 A1# A0 Data 3 A7 A6 A5 A4 A3 A2 A1# A0# 8 words Data 4 A7 A6 A5 A4 A3 A2# A1 A0 Data 5 A7 A6 A5 A4 A3 A2# A1 A0# Data 6 A7 A6 A5 A4 A3 A2# A1# A0 Data 7 A7 A6 A5 A4 A3 A2# A1# A0#

CAS# Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following formula must be programmed into this field. t CAC(min) ≤ CAS# Latency X tCK A6 A5 A4 CAS# Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks

1 X X Reserved

TM Technology Inc. reserves the right P. 14 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A

Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. A8 A7 Test Mode 0 0 normal mode 0 1 Vendor Use Only

1 X Vendor Use Only

Write Burst Length (A9) This bit is used to select the burst write length. A9 Write Burst Length

0 Burst

1 Single Bit

9 No-Operation command

The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low). This prevents unwanted commands from being registered during idle or wait states.

10 Burst Stop command

The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the auto precharge function. The terminated read burst ends after a delay equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the following figure. CLK COMMAND T 0T 1T 2T 3 T 4T 5 T 6T 7 T 8 READ A NOP NOP NOP NOP NOP NOPNOP Burst Stop CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 The burst ends after a delay equal to the CAS# latency. Termination of a Burst Read Operation (Burst Length 4, CAS# Latency = 2, 3) CLK COMMAND T 0T 1T 2T 3 T 4T 5 T 6T 7 T 8 NOP WRITE A NOP NOP NOP NOP NOPNOP Burst Stop CAS# latency= 2, 3 DQ's DIN A0 DIN A1 DIN A2 don't care Input data for the Write is masked. Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3)

TM Technology Inc. reserves the right P. 15 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A

11 Device Deselect command (CS# = "H")

The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command.

12 AutoRefresh command

(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A11 = “Don‘t care, A0-A9 = Don't care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#- before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 2048 times within 32ms. The time required to complete the auto refresh operation is specified by t RC(min.). To provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed. The precharge time requirement, t RP(min), must be met before successive auto refresh operations are performed.

13 SelfRefresh Entry command

(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care) The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).

14 SelfRefresh Exit command

This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device Deselect commands must be issued for t RC(min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode.

15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")

When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms) since the command does not perform any refresh operations.

16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")

When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. t PDE(min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command.

17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")

During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system.

TM Technology Inc. reserves the right P. 16 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Absolute Maximum Rating Symbol Item - 5/6/7 - 5G/6G/7G Unit Note VIN, VOUT Input, Output Voltage - 1.0 ~ 4.6 V 1 VDD, VDDQ Power Supply Voltage -1.0 ~ 4.6 V 1 TA Ambient Temperature 0 ~ 70 °C 1 TSTG Storage Temperature - 55 ~ 125 °C 1 TSOLDER Soldering Temperature (10 second) 245 260 °C 1 PD Power Dissipation 1 W 1 IOUT Short Circuit Output Current 50 mA 1 Recommended D.C. Operating Conditions (TA = 0~70°C) Symbol Parameter Min. Typ. Max. Unit Note VDD Power Supply Voltage 3.0 3.3 3.6 V 2 VDDQ Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2 VIH LVTTL Input High Voltage 2.0 - 4.6 V 2 VIL LVTTL Input Low Voltage - 0.3 - 0.8 V 2 Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C) Symbol Parameter Min. Max. Unit CI Input Capacitance 2 5 pF CI/O Input/Output Capacitance 4 6.5 pF Note: These parameters are periodically sampled and are not 100% tested.

TM Technology Inc. reserves the right P. 17 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Recommended D.C. Operating Conditions (VDD = 3.3V ±±±± 0.3V, TA = 0~70°C) -5 -6 -7 Description/Test condition Symbol Max. Unit Note Operating Current tRC ≥ tRC(min), Outputs Open One bank active IDD1 100 85 75 3 Precharge Standby Current in non-power down mode tCK = tck(min), CS# ≥ VIH(min), CKE ≥ VIH Input signals are changed very 2clks IDD2N 25 Precharge Standby Current in non-power down mode TCK = ∞ , CLK ≤ VIL(max), CKE ≥ VIH IDD2NS 15 Precharge Standby Current in power down mode tCK = tck(min), CKE ≤ VIL(max) IDD2P 2 3 Precharge Standby Current in power down mode TCK = ∞ , CKE ≤ VIL(max) IDD2PS 2 Active Standby Current in non-power down mode tCK = tck(min), CKE ≥ VIH(min), CS# ≥ VIH(min) Input signals are changed very 2clks IDD3N 30 Active Standby Current in non-power down mode CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞ IDD3NS 25 Operating Current (Burst mode) tCK =tCK(min), Outputs Open, Multi-bank interleave IDD4 120 100 90 3, 4 Refresh Current tRC ≥ tRC(min) IDD5 150 130 120 3 Self Refresh Current VIH ≥ VDD - 0.2, 0V ≤ VIL ≤ 0.2V IDD6 2 mA Parameter Description Min. Max. Unit Note IIL Input Leakage Current ( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V ) - 1 1 uA IOL Output Leakage Current Output disable, 0V ≤ VOUT ≤ VDDQ) - 1 1 uA VOH LVTTL Output "H" Level Voltage ( IOUT = -2mA ) 2.4 - V VOL LVTTL Output "L" Level Voltage ( IOUT = 2mA ) - 0.4 V

TM Technology Inc. reserves the right P. 18 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Electrical Characteristics and Recommended A.C. Operating Conditions - 5/6/7 Symbol A.C. Parameter Min. Max. Unit Note tRC Row cycle time (same bank) 50/60/63 tRCD RAS# to CAS# delay (same bank) 15/18/20 tRP Precharge to refresh/row activate command (same bank) 15/18/20 ns tRRD Row activate to row activate delay (different banks) 10/12/14 tRAS Row activate to precharge time (same bank) 35/42/45 tWR Write recovery time 2 tCCD CAS# to CAS# Delay time 1 CLK tCK2 CL* = 2 10/10/10 9 tCK3 Clock cycle time CL* = 3 5/6/7 tCH Clock high time 2/2.5/2.5 10 tCL Clock low time 2/2.5/2.5 10 tAC2 CL* = 2 6/6/6 10 tAC3 Access time from CLK (positive edge) CL* = 3 4.5/5/5.4 ns tOH Data output hold time 2/2.5/2.7 9 tLZ Data output low impedance 1 tHZ Data output high impedance 4.5/5/5.4 8 tIS Data/Address/Control Input set-up time 1.5/1.5/1.5 10 tIH Data/Address/Control Input hold time 1 10 tPDE Power Down Exit set-up time 1.5/1.5/1.5 * CL is CAS# Latency. Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to V SS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power-up sequence is described in Note 11.

TM Technology Inc. reserves the right P. 19 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A 6. A.C. Test Conditions LVTTL Interface Reference Level of Output Signals 1.4V / 1.4V Output Load Reference to the Under Output Load (B) Input Signal Levels 2.4V / 0.4V Transition Time (Rise and Fall) of Input Signals 1ns Reference Level of Input Signals 1.4V 3.3V 1.2kΩ 870 Ω30pF Output 1.4V 50 Ω Output 30pF 50 ΩZ0= LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B) 7. Transition times are measured between V IH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1 ns). 8. t HZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. If clock rising time is longer than 1 ns, ( t R / 2 -0.5) ns should be added to the parameter. 10. Assumed input rise and fall time t T ( tR & tF ) = 1 ns If t R or t F is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to V DD and VDDQ(simultaneously) when all input signals are held "NOP" state and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time. 2) After power-up, a pause of 200us minimum is required. Then, it is recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance. 3) All banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.

Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)

Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)

Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2)

Figure 4. Power on Sequence and Auto Refresh (CBR)

Figure 5. Self Refresh Entry & Exit Cycle

CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
The device remains in SelfRefresh mode as long as CKE stays "low".

RAS is required before exit from SelfRefresh.

System clock restart and be stable before returning CKE high.
Enable CKE and CKE should be set high for minimum time of t SRX.

RC is required after CKE going high to complete SelfRefresh exit.

2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses

TM Technology Inc. reserves the right P. 25 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=1) T 0T 1 T 2T 3T 4T 5T 6T T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 DQM DQ tCK1 RAx RAx CAx Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend

1 Cycle Clock Suspend

2 Cycles

3 Cycles

Note: CKE to CLK disable/enable = 1 clock

TM Technology Inc. reserves the right P. 26 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 DQM DQ tCK2 RAx RAx CAx Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend

1 Cycle

2 Cycles Clock Suspend

Note: CKE to CLK disable/enable = 1 clock

TM Technology Inc. reserves the right P. 27 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T 1 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 DQM DQ tCK3 RAx RAx CAx Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend Note: CKE to CLK disable/enable = 1 clock

TM Technology Inc. reserves the right P. 28 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = 1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 DQM DQ tCK1 RAx RAx CAx Hi-Z DAx0 Activate Command Bank A Write Command Bank A Clock Suspend Note: CKE to CLK disable/enable = 1 clock

TM Technology Inc. reserves the right P. 29 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 DQM DQ tCK2 RAx RAx CAx Hi-Z DAx0 Activate Command Bank A Write Command Bank A Clock Suspend Note: CKE to CLK disable/enable = 1 clock

TM Technology Inc. reserves the right P. 30 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 DQM DQ DAx0 DAx1 DAx2 DAx3 tCK3 RAx RAx CAx Hi-Z Activate Command Bank A Write Command Bank A Clock Suspend Note: CKE to CLK disable/enable = 1 clock

Figure 8. Power Down Mode and Clock Mask (Burst Length=4, CAS# Latency=2)

TM Technology Inc. reserves the right P. 32 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 Activate Command Bank A Read Command Bank A Read Command Bank A Precharge Command Bank A Aw0 Aw1 Aw2 Aw3Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 RAw RAw CAw CAx CAy Read Command Bank A Hi-Z CAz Az0 Az1 Az2 Az3 Read Command Bank A Activate Command Bank A RAz RAz

TM Technology Inc. reserves the right P. 33 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 Activate Command Bank A Read Command Bank A Read Command Bank A Precharge Command Bank A Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 RAw RAw CAw CAx CAy Read Command Bank A Hi-Z CAz Az0 Az1 Az2 Az3 Read Command Bank A Activate Command Bank A RAz RAz

TM Technology Inc. reserves the right P. 34 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK3 Activate Command Bank A Read Command Bank A Read Command Bank A Precharge Command Bank A Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 RAw RAw CAw CAx CAy Read Command Bank A Hi-Z CAz Read Command Bank A Activate Command Bank A RAz RAz Az0

TM Technology Inc. reserves the right P. 35 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 Activate Command Bank A Write Command Bank A Write Command Bank B Precharge Command Bank B DBw0DBw1DBw2 DBw3 DBx0 DBx1 DBy0DBy1 DBy2 DBy3 RBw RBw CBw CBx CBy Write Command Bank B Hi-Z CBz DBz0DBz1 DBz2 DBz3 Write Command Bank B Activate Command Bank B RBz RBz

TM Technology Inc. reserves the right P. 36 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 Activate Command Bank A Write Command Bank B Write Command Bank B Precharge Command Bank B DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 RBw RBw CBw CBx CBy Write Command Bank B Hi-Z CBz DBz0 DBz1DBz2 DBz3 Write Command Bank B Activate Command Bank B RBz RBz

TM Technology Inc. reserves the right P. 37 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK3 Activate Command Bank A Write Command Bank B Write Command Bank B Precharge Command Bank B DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 RBw RBw CBw CBx CBy Write Command Bank B Hi-Z CBz DBz0 DBz1 Write Command Bank B Activate Command Bank B RBz RBz DBz2

TM Technology Inc. reserves the right P. 38 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 Activate Command Bank B Activate Command Bank A Precharge Command Bank B Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 RBx RBx RBy Read Command Bank B Hi-Z CBy Read Command Bank B Precharge Command Bank A High RAx Read Command Bank A Activate Command Bank B By0 By1 By2Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 CBx CAxRAx RBy tRCD tAC1 tRP

TM Technology Inc. reserves the right P. 39 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 Activate Command Bank B Activate Command Bank A Precharge Command Bank B Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 RBx RBx RBy Read Command Bank B Hi-Z CBy Read Command Bank B High RAx Read Command Bank A Activate Command Bank B By0 By1Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 CBx CAxRAx RBy tRCD tAC2 tRP

TM Technology Inc. reserves the right P. 40 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK3 Activate Command Bank B Activate Command Bank A Precharge Command Bank B Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 RBx RBx RBy Read Command Bank B Hi-Z CBy Read Command Bank B High RAx Read Command Bank A Activate Command Bank B Ax7 By0 Ax2 Ax3 Ax4 Ax5 Ax6 CBx CAxRAx RBy tRCD tAC3 tRP Precharge Command Bank A

TM Technology Inc. reserves the right P. 41 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 Activate Command Bank A Activate Command Bank B Precharge Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 RAx RAx RAy Write Command Bank A Hi-Z CAy High RBx Precharge Command Bank B DBx7 DAy3DBx2 DBx3DBx4 DBx5 DBx6 CAx CBxRBx RAy tRCD DAy0 DAy1 DAy2 Write Command Bank A Write Command Bank B Activate Command Bank A tRP tWR

TM Technology Inc. reserves the right P. 42 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 Activate Command Bank A Activate Command Bank B Precharge Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 RAx RAx RAy Write Command Bank A Hi-Z CAy High RBx Precharge Command Bank B DBx7DBx2 DBx3 DBx4 DBx5 DBx6 CAx CBx RBx RAy tRCD Write Command Bank A Write Command Bank B Activate Command Bank A DAy3DAy0 DAy1 DAy2 DAy4 tWR* tRP tWR* * tWR > tWR(min.)

TM Technology Inc. reserves the right P. 43 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK3 Activate Command Bank A Activate Command Bank B Precharge Command Bank A DAx0 DAx1 DAx2 DAx3DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 RAx RAx RAy Write Command Bank A Hi-Z CAy High RBx Precharge Command Bank B DBx7DBx2 DBx3 DBx4 DBx5 DBx6 CAx CBx RBx RAy tRCD Write Command Bank A Write Command Bank B Activate Command Bank A DAy3DAy0 DAy1 DAy2 tWR* tRP tWR* * tWR > tWR(min.)

TM Technology Inc. reserves the right P. 44 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 Activate Command Bank A The Write Data is M asked with a Zero Clock Latency Read Command Bank A Ax0 Ax1 Ax2 Ax3 DAy0DAy1 Hi-Z Precharge Command Bank B Az3DAy3 Az0 Az1 Read Command Bank A Write Command Bank A The Read Data is M asked with a Two Clock Latency RAx RAx CAx CAy CAz

TM Technology Inc. reserves the right P. 45 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 Activate Command Bank A The Write Data is Masked with a Zero Clock Latency Read Command Bank A Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 Hi-Z Az3DAy3 Az0 Az1 Read Command Bank A Write Command Bank A The Read Data is Masked with a Two Clock Latency RAx RAx CAx CAy CAz

TM Technology Inc. reserves the right P. 46 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK3 Activate Command Bank A The Write Data is M asked with a Zero Clock Latency Read Command Bank A Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 Hi-Z Az3DAy3 Az0 Az1 Read Command Bank A Write Command Bank A The Read Data is M asked with a Two Clock Latency RAx RAx CAx CAy CAz

TM Technology Inc. reserves the right P. 47 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 Activate Command Bank A Read Command Bank B Precharge Command Bank A Bw0 Bw1 Bx0 Bx1 By1 Ay0 Hi-Z Bz0 Read Command Bank A Read Command Bank A RAx RAx Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1 Bz2 Bz3 Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Precharge Command Bank B tRCD tAC1 RAx RBw RBw CBw CBx CBy CAy CBz

TM Technology Inc. reserves the right P. 48 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 Activate Command Bank A Read Command Bank B Precharge Command Bank A Bw0 Bw1 Bx0 Bx1 By1 Ay0 Hi-Z Bz0 Read Command Bank A Read Command Bank A RAx RAx Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1 Bz2 Bz3 Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Precharge Command Bank B tRCD tAC2 CAy RAx RAx CBw CBx CBy CAy CBz

TM Technology Inc. reserves the right P. 49 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK3 Activate Command Bank A Prechaerge Command Bank B Bx0 Bx1 By0 By1 Bz1 Ay0 Hi-Z Ay2 Read Command Bank A Read Command Bank A RAx RAx Ax0 Ax1 Ax2 Ax3 Bz0 Ay1 Ay3 Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Precharge Command Bank A tRCD tAC3 CAx RBx RBx CBx CBy CBz CAy

TM Technology Inc. reserves the right P. 50 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 Activate Command Bank A Write Command Bank B DBw0 DBw1 DBx0 DBx1 DBy1 DAy0 Hi-Z Write Command Bank A Precharge Command Bank A RAx RAx DAx0 DAx1 DAx2 DAx3 DBy0 DAy1 DBz0 Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Precharge Command Bank B tRCD CAx RBw RBw CBw CBx CBy CAy DBz1 DBz2 DBz3 Write Command Bank B tRRD tRP tWR tRP CBz

TM Technology Inc. reserves the right P. 51 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 Activate Command Bank A Write Command Bank B DBw0 DBw1 DBx0 DBx1 DBy1DAy0Hi-Z Write Command Bank A Precharge Command Bank A RAx RAx DAx0DAx1 DAx2 DAx3 DBy0 DAy1 DBz0 Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Precharge Command Bank B tRCD CAx RBw RBw CBw CBx CBy CAy DBz1 DBz2 DBz3 Write Command Bank B tRRD tRP tWR tRP CBz WE#

TM Technology Inc. reserves the right P. 52 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# A10 A0~A9,A11 DQM DQ BA0,1 tCK3 Activate Command Bank A Write Command Bank B DBw0 DBw1DBx0 DBx1 DBy1 DAy0 Hi-Z Write Command Bank A Precharge Command Bank A RAx RAx DAx0 DAx1 DAx2 DAx3 DBy0 DAy1 DBz0 Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Precharge Command Bank B tRCD CAx RBw RBw CBw CBx CBy CAy DBz1 DBz2 DBz3 Write Command Bank B tRRD > tRRD(min) tRPtWR tWR(min) CBz WE#

TM Technology Inc. reserves the right P. 53 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 Activate Command Bank A Activate Command Bank B Bx0 Bx1 Bx2 Bx3 Ay1 Ay2 Hi-Z Read Command Bank A RAx RAx RBx Ax0 Ax1 Ax2 Ax3 Ay0 Ay3 By0 Activate Command Bank B Activate Command Bank B RBx CBx CAy RBy CBy By1 By2 By3 RBz High Bz0 Bz1 Bz2 Bz3 Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank A Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank B CAx RBy RBz CBz

TM Technology Inc. reserves the right P. 54 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 Activate Command Bank A Activate Command Bank A Bx0 Bx1 Bx2 Bx3 Ay1 Ay2Hi-Z Read Command Bank A RAx RAx RBx Ax0 Ax1 Ax2 Ax3 Ay0 Ay3 By0 Activate Command Bank B Activate Command Bank B RBx CBx RByRAy CBy By1 By2 By3 High Az0 Az1 Az2 Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank A Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank A CAx RBy RAz CAzRAz

TM Technology Inc. reserves the right P. 55 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# A10 A0~A9,A11 DQM DQ BA0,1 tCK3 Activate Command Bank A Bx0 Bx1 Bx2 Bx3 Ay1 Ay2Hi-Z Read Command Bank A RAx RAx RBx Ax0 Ax1 Ax2 Ax3 Ay0 Ay3 By0 Activate Command Bank B Activate Command Bank B RBx CBx By1 By2 By3 High Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank A Read with Auto Precharge Command Bank B CAx RBy CByRByCAy WE#

TM Technology Inc. reserves the right P. 56 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 Activate Command Bank A DBx0 DBx1 DBx2 DBx3 DAy1DAy2 Hi-Z Write Command Bank A RAx RAx RBx DAx0 DAx1 DAx2 DAx3 DAy0 DAy3 DBy0 Activate Command Bank B Activate Command Bank B CBx CAy DBy1 DBy2 DBy3 High Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A Write with Auto Precharge Command Bank B RBy CAzCByRBy DAz0 DAz0 Activate Command Bank A Write with Auto Precharge Command Bank A DAz0DAz0 CAx RBx RAz RAz T 11

TM Technology Inc. reserves the right P. 57 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 Activate Command Bank A DBx0 DBx1 DBx2 DBx3 DAy1 DAy2 Hi-Z Write Command Bank A RAx RAx RBx DAx0 DAx1 DAx2 DAx3 DAy0 DAy3 DBy0 Activate Command Bank B Activate Command Bank B CBx CAy DBy1 DBy2 DBy3 High Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A Write with Auto Precharge Command Bank B RBy CByRBy DAz0 DAz1 Activate Command Bank A Write with Auto Precharge Command Bank A DAz2 DAz3 CAx RBx CAz RAz RAz WE#

TM Technology Inc. reserves the right P. 58 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A0~A9,A11 DQM DQ BA0,1 tCK3 Activate Command Bank A DBx0 DBx1 DBx2 DBx3 DAy1 DAy2Hi-Z Write Command Bank A RAx RAx RBx DAx0 DAx1 DAx2 DAx3 DAy0 DAy3 DBy0 Activate Command Bank B Activate Command Bank B CBx DBy1 DBy2DBy3 High Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A Write with Auto Precharge Command Bank B CAyCAx RBx CBy RBy RBy

TM Technology Inc. reserves the right P. 59 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 Activate Command Bank A Ax Ax+1 Bx Bx+1 Bx+3 Bx+4 Hi-Z Read Command Bank A RAx RAx RBx Ax+1 Ax+2 Ax-2 Ax-1 Bx+2 Bx+5 Activate Command Bank B Burst Stop Command CBx High Read Command Bank B Precharge Command Bank B CAx RBx RBy RBy Ax Bx+6 Bx+7 The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues burstin g beginning with the starting address. Activate Command Bank B tCK1 tRRD tRP

TM Technology Inc. reserves the right P. 60 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 Activate Command Bank A Ax Ax+1 Bx Bx+1 Bx+3 Bx+4Hi-Z Read Command Bank A RAx RAx Ax+1 Ax+2Ax-2 Ax-1 Bx+2 Bx+5 Activate Command Bank B Burst Stop Command CBx High Read Command Bank B Precharge Command Bank B RBxCAx RBy RBy Ax Bx+6 The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Activate Command Bank B tCK2 tRP RBx

TM Technology Inc. reserves the right P. 61 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 Activate Command Bank A Ax Ax+1 Bx Bx+1 Bx+3 Bx+4 Hi-Z Read Command Bank A RAx RAx Ax+1 Ax+2 Ax-2 Ax-1 Bx+2 Bx+5 Activate Command Bank B Burst Stop Command CBx High Read Command Bank B Precharge Command Bank B RBxCAx RBy RBy Ax The burst counter wraps from the highest order page address back to zero durin g this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Activate Command Bank B tCK3 tRP RBx

TM Technology Inc. reserves the right P. 62 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 DAx+1DAx Activate Command Bank A Hi-Z Activate Command Bank B RAx RAx Burst Stop Command CBx High Write Command Bank B Precharge Command Bank B RBxCAx RBy RBy The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting be ginning with the starting address. Activate Command Bank B tCK1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 DBx+7 Write Command Bank A Data is ignored RBx

TM Technology Inc. reserves the right P. 63 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 DAx+1DAx Activate Command Bank A Hi-Z Activate Command Bank B RAx RAx Burst Stop Command CBx High Write Command Bank B Precharge Command Bank B RBxCAx RBy RBy The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting be ginning with the starting address. Activate Command Bank B tCK2 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 Write Command Bank A Data is ignored RBx

TM Technology Inc. reserves the right P. 64 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 DAx+1DAx Activate Command Bank A Hi-Z Activate Command Bank B RAx RAx Burst Stop Command CBx High RBxCAx Write Command Bank B Precharge Command Bank B RBy RBy The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting be ginning with the starting address. Activate Command Bank B tCK3 RBx DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1DBx+2 DBx+3 DBx+4 DBx+5 Write Command Bank A Data is ignored

Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2)

Figure 21. Random Row Read (Interleaving Banks)

Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)

Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)

TM Technology Inc. reserves the right P. 69 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK1 DAx0 DAx1DAx2 DAx3 DAx4 Ay0 Ay1 Ay2 DAz3DAz2DAz0 Activate Command Bank A Write Command Bank A Precharge Command Bank A Read Command Bank A Precharge Command Bank A Write Command Bank A RAx RAx RAy CAx RAy CAy RAz DAz1 DAz4 DAz5 DAz6 DAz7 Precharge Termination of a Write Burst. Write data is masked. Activate Command Bank A Activate Command Bank A tWR tRP tRP Precharge Ter mination of a Read Burst. RAz CAz

TM Technology Inc. reserves the right P. 70 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 24.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK2 DAx0 DAx1DAx2 DAx3 Ay2Ay0 Ay1 Activate Command Bank A Write Command Bank A Precharge Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A RAx RAx RAy CAx RAy CAy Az0 Az1 Az2 Precharge Termination of a Write Burst. Write data is masked. Activate Command Bank A tWR tRP tRP RAz CAz High Read Command Bank A Precharge Command Bank A Precharge Terminati on of a Read Burst tRP RAz

TM Technology Inc. reserves the right P. 71 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A Figure 24.3. Precharge Termination of a Burst (Burst Length=4, 8 or Full Page, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# A10 A0~A9,A11 DQM DQ BA0,1 tCK3 DAx0 Ay0 Ay1 Ay2 Activate Command Bank A Write Command Bank A Precharge Termination of a Write Burst Read Command Bank A Precharge Command Bank A RAx RAx RAy CAx RAy CAy Write Data is masked Activate Command Bank A tWR tRP tRP RAz RAz High Activate Command Bank A Precharge Command Bank A Precharge Termination of a Read Burst DAx1

TM Technology Inc. reserves the right P. 72 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A

54 Pin TSOP II Package Outline Drawing Information

A A 1 A 2 L L1 C D E HE 0.254 L Symbol Dimension in inch Dimension in mm Min Normal Max Min Normal Max Notes: 1. Dimension D&E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension : mm

TM Technology Inc. reserves the right P. 73 Publication Date: FEB. 2007 to change products or specifications without notice. Revision: A 60-Ball (6.4mm x 10.1mm)VFBGA Units in mm RPNM LKJ HG FEDCBA ABC DEF G H J K L M NPR TOP VIEW BOTTOM VIEW AB C D E E1 SEATING PLANE A1 CORNERA1 CORNER Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom Max

Product Information

T436416D-5SG specifications and overview.

Summary

4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM

Description

4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM

Source title T436416D-5SG Datasheet(PDF) - Taiwan Memory Technology

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