T2316160A

T2316160A TMT | Alldatasheet

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Technical content

Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A DRAM 1024K x 16 DYNAMIC RAM FAST PAGE MODE

FEATURES

• Industry-standard x 16 pinouts and timing functions.
• Single 5V ( ±10%) power supply.
• All device pins are TTL- compatible.
• 1K-cycle refresh in 16ms.
• Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN.
• BYTE WRITE and BYTE READ access cycles. OPTION TIMING MARKING 45ns -45 60ns -60 PACKAGE 42-pin SOJ J 44/50-pin TSOPII S GENERAL DESCRIPTION The T2316160A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x16 configuration. The T2316160A has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode with Extended Data Output. The T2316160A CAS function and timing are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL to transition low in a WRITE cycle will write data into the lower byte (DQ0~DQ7), and CASH transiting low will write data into the upper byte (DQ8~DQ15). PIN ASSIGNMENT ( Top View ) DQ1 VDD DQ11 DQ10 DQ9 DQ2 DQ3 DQ15 DQ14 DQ8 Vss VDD DQ0 DQ4 DQ5 DQ6 DQ7 NC NC NC WE RAS NC NC V DD DQ13 DQ12 Vss NC NC OE CASL CASH Vss DQ1 VDD DQ2 DQ3 VDD DQ0 DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC NC VDD DQ11 DQ10 DQ9 DQ15 DQ14 DQ8 Vss DQ13 DQ12 Vss NC OE CASL CASH Vss

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTIONS SYM. TYPE DESCRIPTION A0-A9 Input Address Input RAS Input Row Address Strobe CASH Input Column Address Strobe /Upper Byte Control CASL Input Column Address Strobe /Lower Byte Control WE Input Write Enable OE Input Output Enable DQ0 – DQ15 Input/ Output Data Input/ Output Vcc Supply Power, 5V Vss Ground Ground NC - No Connect NO.2 CLOCK GENERATOR COLUMN. ADDRESS BUFFER REFRESH CONTROLLER REFRESH COUNTER ROW. ADDRESS BUFFERS(10) NO.1 CLOCK GENERATOR CONTROL LOGIC DATA-IN BUFFER DATA-OUT BUFFER COLUMN DECODER ROW DECODER 1024x 1024 x 16 MEMORY ARRAY SENSE AMPLIFIERS I/O GATING 1024x 16 1024 1024 RAS CAS DQ0 DQ15 OE 1010 CASH CASL WE Vcc Vss

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A ABSOLUTE MAXIMUM RATINGS* Voltage on Any pin Relative to VSS…... -1V to +7V Operating Temperature, Ta (ambient).. 0°C to +70°C *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted) DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES Supply Voltage Vcc 4.5 5.5 V 1 Supply Voltage Vss 0 0 V Input High (Logic) voltage V IH 2.4 Vcc+1 V 1 Input Low (Logic) voltage V IL -1.0 0.8 V 1 Input Leakage Current 0V ≤ VIN ≤ 7V ILI -10 10 uA Output Leakage Current 0V ≤ VOUT≤ 7V Output(s) disabled ILO -10 10 uA Output High Voltage I OH = -5 mA V OH 2.4 Vcc V Output Low Voltage I OL = 4.2 mA V OL 0 0.4 V Note: 1.All Voltages referenced to Vss MAX DESCRIPTION CONDITIONS SYM. -45 -60 UNITS NOTES Operating Current RAS ,CAS cycling , tRC = min Icc1 190 170 mA 1,2 TTL Standby Current TTL interface, RAS , CAS =VIH, DOUT=High-Z Icc2 2.0 2.0 mA RAS -only refresh Current tRC = min I cc3 190 170 mA 2 Fast Page Mode Current tPC = min I cc4 150 130 mA 1,3 CAS Before RAS Refresh Current tRC = min Icc5 190 170 mA CMOS Standby Current CMOS interface, RAS ,CAS >Vcc- 0.2V Icc6 1.0 1.0 mA 1 Note: 1. Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.

Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A CAPACITANCE (Ta =25°C, Vcc =5V, f = 1M HZ) Parameter Symbol Typ Max Unit Input Capacitance (address) C I1 - 5 pF Input Capacitance ( RAS , CAS , WE , OE ) C I2 - 7 pF Output Capacitance (data-in/out) C I/O - 10 pF AC CHARACTERISTICS (note 1,2,3) (Ta = 0 to 70°C) TEST CONDITIONS: Vcc=5V ±10%, VIH/VIL=2.4/0.8V,VOH/VOL=2.0/0.8V Input rise and fall times: 2ns Output Load: 2TTL gate + CL (100pF) AC CHARACTERISTICS -45 -60 PARAMETER SYM MIN MAX MIN MAX UNIT Notes Read or Write Cycle Time t RC 85 110 ns Read Write Cycle Time t RWC 105 140 ns Fast-Page-Mode Read or Write Cycle Time t PC 26 35 ns Fast-Page-Mode Read-Write Cycle Time t PCM 70 85 ns Access Time From RAS tRAC 45 60 ns 4 Access Time From CAS tCAC 11 15 ns 5 Access Time From OE tOAC 11 15 ns 13 Access Time From Column Address t AA 19 30 ns 8 Access Time From CAS Precharge tACP 22 35 ns RAS Pulse Width tRAS 45 10K 60 10K ns RAS Pulse Width (Fast Page Mode) tRASC 45 100K 60 100K ns RAS Hold Time tRSH 11 15 ns RAS Precharge Time tRP 28 40 ns CAS Pulse Width tCAS 10 10K 15 10K ns CAS Hold Time tCSH 40 60 ns CAS Precharge Time tCP 6 10 ns RAS to CAS Delay Time tRCD 10 34 20 45 ns 7 CAS to RAS Precharge Time tCRP 5 5 ns Row Address Setup Time t ASR 0 0 ns Row Address Hold Time t RAH 5 10 ns RAS to Column Address Delay Time tRAD 8 26 12 30 ns 8 Column Address Setup Time t ASC 0 0

Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A AC CHARACTERISTICS (continued) AC CHARACTERISTICS -45 -60 PARAMETER SYM MIN MAX MIN MAX UNIT Notes Column Address Hold Time t CAH 6 10 ns Column Address Hold Time (Reference to RAS ) tAR 35 45 ns Column Address to RAS Lead Time tRAL 19 30 ns Read Command Setup Time t RCS 0 0 ns 14 Read Command Hold Time Reference to CAS tRCH 0 0 ns 9,14 Read Command Hold Time Reference to RAS tRRH 0 0 ns 9 CAS to Output in Low-Z tCLZ 3 3 ns Output Buffer Turn-off Delay From CAS or RAS tOFF1 3 15 3 15 ns 10,16 Output Buffer Turn-off OE to tOFF2 8 15 ns 16 Write Command Setup Time tWCS 0 0 ns 11,14 Write Command Hold Time tWCH 6 10 ns Write Command Hold Time (Reference to RAS ) tWCR 35 45 ns 14 Write Command Pulse Width t WP 7 15 ns 14 Write Command to RAS Lead Time tRWL 9 10 ns 14 Write Command to CAS Lead Time tCWL 8 10 ns 14 Data-in Setup Time t DS 0 0 ns 12 Data-in Hold Time t DH 6 10 ns 12 Data-in Hold Time (Reference to RAS ) tDHR 35 45 ns RAS to WE Delay Time tRWD 61 85 ns 11 Column Address to WE Delay Time tAWD 35 55 ns 11 CAS to WE Delay Time tCWD 27 40 ns 11 Transition Time (rise or fall) t T 2.5 50 2.5 50 ns 2,3 Refresh Period (1024 cycles) t REF 16 16 ms RAS to CAS Precharge Time tRPC 10 10 ns CAS Setup Time (CBR REFRESH) tCSR 10 10 ns 6 CAS Hold Time (CBR REFRESH) tCHR 10 10 ns 6 OE Hold Time From WE During Read-Modify-Write Cycle tOEH 6 15 ns 15 OE Setup Prior to RAS During Hidden Refresh Cycle tORD 0 0 ns

Taiwan Memory Technology, Inc. reserves the right P. 6 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A Notes: 1. An initial pause of 200us is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 2. V IH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between VIH(2.4V) and VIL(0.8V). 3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. 4. Assume that t RCD < t RCD(max). If t RCD is greater than the maximum recommended value shown in this table, t RAC will increase by the amount that tRCD exceeds the value shown. 5. Assume that t RCD ≥ tRCD(max) . 6. Enables on-chip refresh and address counters. 7. Operation within the t RCD(max) limit ensures that t RAC(max) can be met. t RCD(max) is specified as a reference point only; if t RCD is greater than the specified t RCD(max) limit, access time is controlled by tCAC. 8. Operation within the t RAD limit ensures that tRAC(max) can be met. t RAD(max) is specified as a reference point only; if t RAD is greater than the specified t RAD(max) limit, access time is controlled by tAA. 9. Either t RCH or t RRH must be satisfied for a READ cycle. 10. tOFF1(max) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 11. tWCS, t RWD, t AWD and t CWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycles only. If t WCS ≥ tWCS(min), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If t RWD ≥ tRWD(min), t AWD ≥ tAWD(min) and t CWD ≥ tCWD(min), the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE - controlled) cycle. 12. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ- MODIFY-WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. 14. WRITE command is defined as WE going low. 15. LATE WRITE and READ-MODIFY-WRITE cycles must have both t OFF2 and t OEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 16. The I/Os open during READ cycles once tOFF1 or tOFF2 occur.

Taiwan Memory Technology, Inc. reserves the right P.7 Publication Date:APR. 2002 to change products or specifications without notice. Revision:A READ CYCLE RAS CAS VIHVIL VOHVOL VIHVIL VIHVIL VIHVIL VIHVIL ADDR WE OE I/O tRAS tRC tRP VALI D DATA COLUMN ROWROW tASR tRAH tRAD tCRP tCSH tRAL tASC tCAH tOFF1 NOTE1 tRRH tAR tAA tCAC tCLZ tRAC OPENOPEN tOFF2tOAC tRSH tCAS tRCD tRCS tRCH EARLY WRITE CYCLE RAS CAS VIHVIL VIO HVIO L VIHVIL VIHVIL VIHVIL VIHVIL ADDR WE OE I/O tRAS tRC tRP VALI D DATA COLUMN ROWROW tASR tRAH tRAD tCRP tCSH tCWL tRW L tWCR tAR tDHR tWP tDS tDH tRSH tCAS tRCD tWCH tASC tCAH tRAL tWCS DON'T CARE UNDEFINED Note: tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.

Taiwan Memory Technology, Inc. reserves the right P.8 Publication Date:APR. 2002 to change products or specifications without notice. Revision:A READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) RAS CAS VIHVIL VIO H VIO L VIHVIL VIHVIL VIHVIL VIH VIL ADDR WE OE I/O tRAS tRW C tRP VALI D DOUT COLUMN ROWROW tASR tRAH tRAD tCRP tCSH tRAL tASC tCAH tAR tAA tCAC tCLZ tRAC OPENOPEN tOFF2tOAC tRSH tCAStRCD tRCS tOEH VALI D DIN tDHtDS tRW D tCWD tAW D tCWL tRW L tWP FAST-PAGE-MODE READ CYCLE Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of CAS . Both measurements must meet the tPC specification. RAS CAS VIHVIL VOH VOL VIHVIL VIHVIL VIHVIL VIHVIL ADDR WE OE I/O tRP VALID DATA COLUMN ROWROW tASR tRAH tRAD tCRP tRAL tASC tCAH tAR tAA tCAC tCLZ tRAC OPEN OPEN tOF F2tOAC tCSH tRCD tRCS DON'T CARE UNDEFINED t RASC tCPN tRSH tCP tPC tCP tCAS COLUMN tASC tCAH tASC tCAH COLUMN VALID DATA tCLZ tCLZ tAA tCAC tAA tCAC tOFF2tOAC tOFF1 tACPtACP tRRHtRCH tCAS tCAS VALID DATA tOFF2 tOAC tOFF1 tOFF1

Taiwan Memory Technology, Inc. reserves the right P. 9 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A FAST-PAGE-MODE EARLY-WRITE CYCLE RAS CAS VIHVIL VIO HVIO L VIHVIL VIHVIL VIHVIL VIHVIL ADDR WE OE I/O VALI D DATA tCAStRCDtCRP tCSH tPC tCP tCP tRSH tCPN t RASC VALI D DATA VALI D DATA COL UMN COL UMN COL UMN ROWROW tASR tRAH tRAD tAR tASC tCAH tASC tCAH tASC tCAH tRAL tWCS tWCH tCWL tWP tWCS tCWL tWCH tWP tWCS tCWL tWCH tWP tDS tWCR tDHR tDH tDS tDH tDS tDH tRW L tCAS tCAS FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) VIO HVIO L VIHVILOE I/O tDH tCAC tCLZ OPENOPEN tOFF2 tOAC DON'T CARE UNDEFINED tAA tOEH tOFF2 tOAC tACP RAS CAS VIHVIL VIHVIL VIHVIL VIHVIL ADDR WE tRP COLUMN ROWROW tASR tRAH tRAD tCRP tRAL tASC tCAH tAR tAA tDS tRAC tCSH tCAS tRCD tRCS t RASC tCPN tRSH tCPtCP tCAS tCAS COLUMN tASC tCAH tASC tCAH COLUMN tAA tACP tRW L tCWL tWP tCWL tWP tRW D tAW D tCWD tCWD tAW D tCWD tAWD tCWL tWP tOFF2 tOAC tDH tDS tDH tDS tCAC tCLZ tCAC tCLZ tPCM VALID D IN VALID DOUT VALID D IN VALID DOU T VALID D IN VALID DOUT Note: tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification.

Taiwan Memory Technology, Inc. reserves the right P. 10 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) RAS ONLY REFRESH CYCLE (ADDR=A0-A9;OE, WE =DON‘T CARE) RAS CAS VIHVIL VOHVOL VIHVIL VIHVILADDR I/O tRAS tRC tRP OPEN ROWROW tASR tRAH tCRP tRPC DON'T CARE UNDEFINED Note1:Do not drive data prior to tristate. RAS CAS VIHVIL VIOHVIOL VIHVIL VIHVIL VIHVIL VIHVIL ADDR WE OE I/O tRP VALID DATA (B) ROWROW tASR tRAH tRAD tCRP tCSH tRAL tASC tCAH tRASC tRSH tAR tAA tCAC tRAC OPEN tOAC tPC tCAStRCD tRCS COLUMN(A) COLUMN(B) COLUMN(N) NOTE1 VALID DATA (A) tCP tPC tCPtCAS tCAS tCP tASC tCAH tASC tCAH tWCHtWCS tRCH tOFF1 tAA tCAC tCLZ tACP tDS tDHtOFF1 VALID DATA IN

Taiwan Memory Technology, Inc. reserves the right P. 11 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A CBR REFRESH CYCLE (A0-A9; OE =DON‘T CARE) RAS CASH, CASL VIHVIL VIHVIL VIH VIL I/O tRAS tRAStRP OPEN tRPC tCPN WE tRP tCSR tCHR tRPC tCSR tCHR HIDDEN REFRESH CYCLE ( WE =HIGH;OE =LOW) RAS CAS VIHVIL VOHVOL VIHVIL VIHVIL I/O ( REFRESH) tRAStRP OPEN VALI D DATA tCRP OE OPEN VIHVILADDR ROW tASR tRAH tRAD tRAL tASC tCAH tAR tAA tCAC tCLZ tRAC tOAC tRSH tRCD tCHR COLUMN tOFF2 tORD tOFF1 NOTE1 (R E A D ) tRAS Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.

Taiwan Memory Technology, Inc. reserves the right P. 12 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A PACKAGE DIMENSIONS 42-LEAD SOJ DRAM (400 mil) SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 0.128~0.148 3.251~3.759 A1 0.025(MIN) 0.635(MIN) A2 0.105~0.115 2.657~2.920 B 0.026~0.032 0.660~0.813 b 0.015~0.020 0.381~0.508 c 0.007~0.013 0.178~0.330 D 1.070~1.080 27.178~27.432 E 0.395~0.405 10.033~10.287 e 0.050 1.270 E1 0.435~0.445 11.049~11.303 L 0.082(MIN) 2.083(MIN) y 0.004(MAX) 0.102(MAX)

Taiwan Memory Technology, Inc. reserves the right P. 13 Publication Date: APR. 2002 to change products or specifications without notice. Revision:A PACKAGE DIMENSIONS 44/50L LEAD TSOPII DRAM (400 mil) SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 0.047 1.200(MAX) A1 0.002~0.006 0.050~0.150 A2 0.037~0.041 0.950~1.050 b 0.012~0.018 0.300~0.450 c 0.005~0.008 0.120~0.210 D 0.820~0.830 20.820~21.080 E 0.455~0.471 11.560~11.960 e 0.031 0.800 E1 0.395~0.405 10.030~10.290 L 0.016~0.024 0.400~0.600 L1 0.031 0.800 θ 0°~5° 0 °~5° "A"