T221160A-35J

T221160A TMT | Alldatasheet

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Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A DRAM 64K x 16 DYNAMIC RAM FAST PAGE MODE

FEATURES

• High speed access time : 25/30/35/40 ns
• Industry-standard x 16 pinouts and timing functions.
• Single 5V ( ±10%) power supply.
• All device pins are TTL- compatible.
• 256-cycle refresh in 4ms.
• Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN.
• Conventional FAST PAGE MODE access cycle.
• BYTE WRITE and BYTE READ access cycles. PART NUMBER EXAMPLES PART NUMBER ACCESS TIME PACKAGE T221160A-30J 30ns SOJ T221160A-30S 30ns TSOP -II T221160A-35J 35ns SOJ T221160A-35S 35ns TSOP -II GENERAL DESCRIPTION The T221160A is a randomly accessed solid state memory containing 1,048,551 bits organized in a x16 configuration. The T221160A has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode operation The T221160A CAS function and timing are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL transiting low in a WRITE cycle will write data into the lower byte (IO1~IO8), and CASH transiting low will write data into the upper byte (IO9~16). PIN ASSIGNMENT ( Top View ) I/01 Vcc I/02 I/03 I/04 I/05 Vcc I/06 I/07 I/08 NC NC NC Vcc WE RAS I/016 Vss I/015 I/014 I/013 I/012 Vss I/011 I/010 I/09 NC NC VSS CASL CASH OE SOJ I/01 Vcc I/02 I/03 I/04 I/05 Vcc I/06 I/07 I/08 NC NC NC Vcc W E RAS I/016 Vss I/015 I/014 I/013 I/012 Vss I/011 I/010 I/09 NC NC VSS CASL CASH OE TSOP(II)

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A FUNCTIONAL BLOCK DIAGRAM NO.2 CLOCK GENERATOR COLUMN. ADDRESS BUFFER REFRESH CONTROLLER REFRESH COUNTER ROW. ADDRESS BUFFERS(8) NO.1 CLOCK GENERATOR CONTROL LOGIC DATA-IN BUFFER DATA- OUTBUFFER COLUMN DECODER ROW DECODER 256 x 256 x 16 MEMORYARRA Y SENSE AMPLIFIERS VO GATING 256 x 16 256 256 RAS CAS DQ01 DQ16 OE CASH CASL WE Vcc Vss PIN DESCRIPTIONS PIN NO. SYM. TYPE DESCRIPTION 16~19,22~25 A0-A7 Input Address Input

14 RAS Input Row Address Strobe

28 CASH Input Column Address Strobe /Upper Byte Control

29 CASL Input Column Address Strobe /Lower Byte Control

13 WE Input Write Enable

27 OE Input Output Enable

2~5,6~10,31~34,36~39 I/O1 - I/O16 Input/ Output Data Input/ Output 1,6,20 Vcc Supply Power, 5V 21,35,40 Vss Ground Ground 11,12,15,30 NC - No Connect

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A ABSOLUTE MAXIMUM RATINGS* Voltage on Any pin Relative to VSS… … -1V to 7V Operating Temperature, Ta (ambient)..0°C to +70°C Storage Temperature (plastic)….... -55 °C to +150°C *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted) DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES Supply Voltage Vcc 4.5 5.5 V 1 Supply Voltage Vss 0 0 V Input High (Logic) voltage V IH 2.4 Vcc+1 V 1 Input Low (Logic) voltage V IL -1.0 0.8 V 1 Input Leakage Current 0V ≤ VIN ≤ 7V ILI -10 10 uA Output Leakage Current 0V ≤ VOUT≤ 7V Output(s) disabled ILO -10 10 uA Output High Voltage I OH = -5 mA V OH 2.4 - V Output Low Voltage I OL = 4.2 mA V OL - 0.4 V Note: 1.All Voltages referenced to Vss

Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A DC CHARACTERISTICS (Ta = 0 to 70°C, Vcc = 5V ±10%, Vss = 0V) -25 -30 -35 -40 Parameter Symbol Min Max Min Max Min Max Min Max Unit Test Condition Operating Current Icc1 - 170 - 150 - 130 - 120 mA RAS , CAS cycling tRC=min Standby Current Icc2 - 4 - 4 - 4 - 4 mA TTL interface, RAS , CAS =VIH, DOUT=High-Z Standby Current Icc3 - 2 - 2 - 2 - 2 mA CMOS interface, RAS , CAS > Vcc-0.2V Fast Page Mode Current Icc4 - 170 - 150 - 130 - 120 mA RAS =VIL, CAS cycling, tPC= min RAS -only refresh Current Icc5 - 170 - 150 - 130 - 120 mA CAS =VIH, RAS cycling, tRC= min CAS Before RAS Refresh Current Icc6 - 170 - 150 - 130 - 120 mA RAS , CAS cycling, tRC= min Note: Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition, Icc is specified as an average current. CAPACITANCE (Ta =25°C, Vcc =5V, f = 1M HZ) Parameter Symbol Typ Max Unit Input Capacitance (address) CI1 - 5 pF Input Capacitance ( RAS , CAS , WE , OE ) CI2 - 7 pF Output Capacitance (data-in/out) CI/O - 10 pF

Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A AC CHARACTERISTICS (note 1,2,3) (Ta = 0 to 70°C) AC TEST CONDITIONS: Vcc=5V ±10%, input pulse level = 0 to 3V Input rise and fall times: 2ns Output Load: 2TTL gate + CL (50pF) -25 -30 -35 -40 AC CHARACTERISTICS PARAMETER SYM MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes Read or Write Cycle Time t RC 43 55 65 75 ns Read-Modify-Write Cycle Time t RWC 65 85 95 105 ns Fast-Page-Mode Read or Write Cycle Time t PC 15 20 23 25 ns Fast-Page-Mode Read-Write Cycle Time t PCM 37 42 49 52 ns Access Time From RAS tRAC 25 30 35 40 ns 4 Access Time From CAS tCAC 7 8 9 10 ns 5 Access Time From OE tOAC 7 8 9 10 ns 13 Access Time From Column Address t AA 12 16 18 20 ns 8 Access Time From CAS Precharge tACP 14 18 20 22 ns RAS Pulse Width tRAS 25 10K 30 10K 35 10K 40 10K ns RAS Pulse Width tRASC 25 100K 30 100K 35 100K 40 100K ns RAS Hold Time tRSH 7 8 9 10 ns RAS Precharge Time tRP 15 20 23 25 ns CAS Pulse Width tCAS 4 10K 6 10K 8 10K 10 10K ns CAS Hold Time tCSH 21 26 30 35 ns CAS Precharge Time tCP 3 3 4 5 ns RAS to CAS Delay Time tRCD 10 17 10 21 10 25 10 29 ns 7 CAS to RAS Precharge Time tCRP 3 3 3 5 ns Row Address Setup Time t ASR 0 0 0 0 ns Row Address Hold Time t RAH 5 5 5 5 ns RAS to Column Address Delay Time tRAD 8 13 8 14 8 16 8 18 ns 8 Column Address Setup Time t ASC 0 0 0 0 ns Column Address Hold Time t CAH 4 4 4 5 ns Column Address Hold Time (Reference to RAS ) tAR 22 26 30 34 ns Column Address to RAS Lead Time tRAL 12 14 16 18 ns Read Command Setup Time t RCS 0 0 0 0 ns 14 Read Command Hold Time Reference to CAS tRCH 0 0 0 0 ns 9,14 Read Command Hold Time Reference to RAS tRRH 0 0 0 0 ns 9 CAS to Output in Low-Z tCLZ 3 3 3 3 ns Output Buffer Turn-off Delay From CAS or RAS tOFF1 3 15 3 15 3 15 3 15 ns 10,16

Taiwan Memory Technology, Inc. reserves the right P. 6 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A AC CHARACTERISTICS (continued) -25 -30 -35 -40 AC CHARACTERISTICS PARAMETER SYM MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes Output Buffer Turn-off OE to tOFF2 - 6 - 8 - 8 - 8 ns 16 Write Command Setup Time tWCS 0 0 0 0 ns 11,14 Write Command Hold Time tWCH 4 4 4 6 ns Write Command Hold Time (Reference to RAS ) tWCR 22 26 30 34 ns 14 Write Command Pulse Width t WP 4 4 4 6 ns 14 Write Command to RAS Lead Time tRWL 5 6 7 9 ns 14 Write Command to CAS Lead Time tCWL 5 6 7 8 ns 14 Data-in Setup Time t DS 0 0 0 0 ns 12 Data-in Hold Time t DH 4 4 4 5 ns 12 Data-in Hold Time (Reference to RAS ) tDHR 22 26 30 34 ns RAS to WE Delay Time tRWD 34 46 51 56 ns 11 Column Address to WE Delay Time tAWD 21 29 31 35 ns 11 CAS to WE Delay Time tCWD 17 24 25 27 ns 11 Transition Time (rise or fall) t T 1.5 50 1.5 50 2.5 50 2.5 50 ns 2,3 Refresh Period (256 cycles) t REF 4 4 4 4 ms RAS to CAS Precharge Time tRPC 10 10 10 10 ns CAS Setup Time (CBR REFRESH) tCSR 5 10 10 10 ns 6 CAS Hold Time (CBR REFRESH) tCHR 7 10 10 10 ns 6 OE Hold Time From WE During Read- Modify-Write Cycle tOEH 4 4 4 5 ns 15 OE Setup Prior to RAS During Hidden Refresh Cycle tORD 0 0 0 0 ns

Taiwan Memory Technology, Inc. reserves the right P. 7 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A Notes: 1. An initial pause of 200us is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 2. V IH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between VIH(2.4V) and VIL(0.8V). 3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. 4. Assume that t RCD < t RCD(max). If t RCD is greater than the maximum recommended value shown in this table, t RAC will increase by the amount that tRCD exceeds the value shown. 5. Assume that t RCD ≥ tRCD(max) . 6. Enables on-chip refresh and address counters. 7. Operation within the t RCD(max) limit ensures that t RAC(max) can be met. t RCD(max) is specified as a reference point only; if t RCD is greater than the specified t RCD(max) limit, access time is controlled by tCAC. 8. Operation within the t RAD limit ensures that tRAC(max) can be met. t RAD(max) is specified as a reference point only; if t RAD is greater than the specified t RAD(max) limit, access time is controlled by tAA. 9. Either t RCH or t RRH must be satisfied for a READ cycle. 10. tOFF1(max) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 11. tWCS, t RWD, t AWD and t CWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycles only. If t WCS ≥ tWCS(min), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If t RWD ≥ tRWD(min), t AWD ≥ tAWD(min) and t CWD ≥ tCWD(min), the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE - controlled) cycle. 12. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ- MODIFY-WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. 14. WRITE command is defined as WE going low. 15. LATE WRITE and READ-MODIFY-WRITE cycles must have both t OFF2 and t OEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 16. The I/Os open during READ cycles once tOFF1 or tOFF2 occur.

Taiwan Memory Technology, Inc. reserves the right P. 8 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A READ CYCLE VIH VILRAS VIH VIL VIH VILADDR VIH VILWE VIOH VIOL I/O VIH VIL OE CAS VAILD DATA COLUMNROW ROW tRC tRAS tRP tRRH tCSH tRSH tCAS tRCD tCRP tASR tRAH tRAD tASC tCAH tRAL tAR tRCH tRCS tAA tRAC tCAC tCLZ tOFF1 NOTE1 tOFF2tOAC OPENOPEN tCRP EARLY WRITE CYCLE VIH VILRAS VIH VIL VIH VILADDR VIH VILWE VIOH VIOL I/O VIH VIL OE VAILD DATA COLUMNROW ROW tRC tRAS tRP tRSH tCSH tCAStRCDtCRP tASR tRAH tRAD tASC tAR tRAL tCSH tWP tWCHtWCS tWCR tRWL tDHR tDHtDS DON'T CARE UNDEFINED tCWL tCRP RAS Note: tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.

Taiwan Memory Technology, Inc. reserves the right P. 9 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) ROWCOLUMNROW VAILD D INVAILD DOUT VIH VILRAS VIH VILCAS VIH VILADDR VIH VILWE VIOH VIOLI/O VIH VILOE tRWC tRAS tRP tCSH tRSH tCAStRCDtCRP tASR tRAH tRAD tAR tASC tCAH tRAL tCWL tRWL tWP tRWD tCWD tAWD tRCS tAA tRAC tCAC tCLZ tOAC tOFF2 tOEH tDH tDS tCRP FAST-PAGE-MODE READ CYCLE t RASC t CRP t CSH t RCD t CAS t PC t CP t CAS t CP t CAS t RSH t RP t CPN t ASR t RAH t ASC t RAD t AR t CAH t ASC t CAH t CAHt ASC t RAL ROW COLUM N COLUM N COLUM N ROW V IH V IL RAS V IH V IL CAS V IH V IL ADDR V IH V IL WE V IO H V IO L I/O V IH V IL OE t RCS t RRH t RCH t OFF1t CLZ t CAC t ACP t AAt AA t ACP t CAC t CLZ t CAC t RAC t AA t OAC t OAC t OFF2 VAI LD DATA VAI LD DATA VAI LD DATAOPEN OPEN DON' T CARE UNDEFI NED t CRP t OFF1t OFF1 t CLZ t OAC t OFF2t OFF2 Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of CAS . Both measurements must meet the tPC specification.

Taiwan Memory Technology, Inc. reserves the right P. 10 Publication Date:FEB. 2002 to change products or specifications without notice. Revision:A FAST-PAGE-MODE EARLY-WRITE CYCLE tRASC tCRP tCSH tRCD tCAS,tCLCH tPC tCP tCAS,tCLCH tCP tCAS,tCLCH tRSH tRP tCPN tASR tRAH tASC tRAD tAR tCAH tASC tCAH tCAHtASC tRAL tWCS tCWL tWCH tWP tWCS tCWL tWCH tWP tWCS tCWL tWCH tWP tRWL tDHtDStDS tDHtDHtDS tWCR tDHR ROW COLUMN COLUMN COLUMN ROW VALID DATA VALID DATA VALID DATA VIH VILRAS VIH VILCAS VIH VILADDR VIH VILWE VIOH VIOLI/O VIH VILOE tCRP FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) tRASC tCRP tCSH tRCD tCAS,tCLCH tPCM tCP tCAS,tCLCH tCP tCAS,tCLCH tRSH tRP tCPN tASR tRAH tASC tRAD tAR tCAH tASC tCAH tCAHtASC tRAL ROW COLUMN COLUMN COLUMN ROW VIH VIL RAS VIH VIL CAS VIH VILADDR VIH VILWE VIOH VIOL I/O VIH VIL OE tRWD tRCS tCWL tWPtAWD tCWD tAWD tWP tCWL tCWD tCWD tWP tCWL tRWL tAA tRAC tCACtCLZ tDS tDH tAA tACP tCACtCLZ tCLZ tCAC tACPtDS tDH tAA tDH tDS tOAC tOFF2 tOAC tOFF2 tOAC tOFF2 tOEH DON'T CARE UNDEFINED VAILD D OUT VAILD D IN VAILD D OUT VAILD D IN VAILD D OUT VAILD D IN tCRP Note: tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification.

Taiwan Memory Technology, Inc. reserves the right P. 11 Publication Date:FEB. 2002 to change products or specifications without notice. Revision:A FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) tRASC tCRP tCSH tRCD tCAS tPC tCP tCAS tCP tCAS tRSH tRP tCP tASR tRAH tASC tRAD tAR tCAH tASC tCAH tCAHtASC tRAL ROW COLUMN COLUMN COLUMN ROW V IH V IL RAS V IH V IL CAS V IH V IL ADDR V IH V IL WE V IO H V IO L I/O V IH V IL OE tPC tRCS tRCH tWCS tWCH tAA tRAC tCAC tACP tCAC tAA tDHtDS tOAC OPE N tCRP tOFF1 tCLZ tOFF1 VAI LD DATA( A) VAI LD DATA( B) VAI LD D A TA IN RAS ONLY REFRESH CYCLE (ADDR=A0-A7 ; OE, WE =DON‘T CARE) VIH VILRAS VIH VILCAS VIH VILADDR VOH VOLI/O OPEN ROW ROW tASR tRAH tCRP tRPC tRPtRAS tRC DON'T CARE UNDEFINED tOFF Note1:Do not drive data prior to tristate.

Taiwan Memory Technology, Inc. reserves the right P. 12 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A CBR REFRESH CYCLE (A0-A7 ; OE =DON‘T CARE) VIH VIL RAS VIH VIL I/O VIH VIL WE CAS tRP tRAS tRP tRAS tCHRtCSRtRPCtCHRtCSRtCPN tRPC OPEN tOFF tRC HIDDEN REFRESH CYCLE ( WE =HIGH ; OE =LOW) V IH V IL RAS V IH V IL V IH V IL ADDR V IO H V IO L I/O V IH V IL OE CAS VAI LD DATA ROW COLUM N t RAS t RP t RAS t CHRt RSHt RCDt CRP t ASR t RAH t RAD t AR t RAL t ASC t CAH t AA t RAC t CAC t CLZ t OAC t ORD t OFF 2 t OFF 1 NOTE1 OP ENOP EN DON' T CARE UNDEFI NED t RP (R E F R E S H ) t RC (R E A D ) t RC Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.

Taiwan Memory Technology, Inc. reserves the right P. 13 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A PACKAGE DIMENSIONS 40-LEAD SOJ DRAM (400 mil) 1 20 2140 C y J B A D Seating Plane F E 10¢X(MAX I H L K G SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 1.025 ±0.010 26.035 ±0.254 B 0.400 ±0.005 10.160 ±0.127 C 0.045(MAX) 1.143(MAX) D 0.050 ±0.006 1.27 ±0.152 E 0.019 ±0.003 0.483 ±0.08 F 0.026 ±0.003 0.661 ±0.080 G 0.440 ±0.010 11.176 ±0.254 H 0.011 ±0.003 0.280 ±0.080 I 0.025(MIN) 0.635(MIN) J 0.364 ±0.020 9.246 ±0.508 K 0.047 ±0.006 1.194 ±0.152 L 0.150(MAX) 3.810(MAX) y 0.004(MAX) 0.102(MAX)

Taiwan Memory Technology, Inc. reserves the right P. 14 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A PACKAGE DIMENSIONS 40-LEAD TSOP II DRAM (400 mil) SEATING PLANE EE 1 D be A A2 A1 L y θ 12 0 2140 SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 0.047(max) 1.20(max) A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 b 0.014(typ.) 0.35(typ.) e 0.0315(typ.) 0.80typ.) D 0.725±0.004 18.41±0.10 E 0.463±0.008 11.76±0.20 E1 0.400±0.004 10.16±0.10 L1 0.031 0.80 L 0.020±0.004 0.500±0.10 y 0.004(max) 0.10(max) θ 0°~5° 0 °~5°