T15V2M16B TMT | Alldatasheet

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TM Technology Inc. reserves the right P. 1 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A SRAM 128K X 16 LOW POWER CMOS STATIC RAM

FEATURES

  • Access time : 45/55/70/100 ns
  • Low-power consumption - Active: 5mA (ICC1) - Stand-by: (CMOS input/output) Max.. 15 uA for 55/70/100ns Max.. 40 uA for 45ns
  • Equal access and cycle time
  • Single +2.7V to 3.6V Power Supply
  • TTL compatible , Tri-state output
  • Common I/O capability
  • Automatic power-down when deselected
  • Available in 44-PIN TSOP-II and 48-pin CSP packages
  • Operating temperature : - -10 ~ +70 °C - -40 ~ +85 °C PART NUMBER EXAMPLES PART NUMBER PACKAGE Temperature T15V2M16B-55S TSOP-II -10 ~ +70 °C T15V2M16B-70C CSP -10 ~ +70 °C T15V2M16B-55SI TSOP-II -40 ~ +85 °C T15V2M16B-70CI CSP -40 ~ +85 °C GENERAL DESCRIPTION The T15V2M16B is a very Low Power CMOS Static RAM organized as 131,072 words by 16 bits . This device is fabricated by high performance CMOS technology. It can be operated under wide power supply voltage range from +2.7V to +3.6V. The T15V2M16B inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Data retention is guaranteed at a power supply voltage as low as 2V. BLOCK DIAGRAM DECODERA0 A16 I/O16 Vcc DATA I/O CORE ARRAY Vss I/O1WE OE CE CONTROL CIRCUIT UB LB

TM Technology Inc. reserves the right P. 2 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A PIN CONFIGURATIONS TSOP-II CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A10 A11 NC LB OE I/O9 VCC VSS I/O10 I/O15 I/O16 NC A8 A14 NC A15 A12 A13 A9 A10 WE A11 NC I/O8 I/O7 NC VCC VSS UB I/O3 I/O1 A0 A1 A2 CEA4A3 A 654321 H G F E D C B I/O11 I/O12 I/O13 I/O14 NC NC A16 I/O2 I/O4 I/O5 I/O6 48-Ball CSP TOP VIEW (Ball Down) PIN DESCRIPTIONS SYMBOL DESCRIPTIONS SYMBOL DESCRIPTIONS A0 ~ A16 Address inputs LB Lower byte (I/O 1~8) I/O1~I/O16 Data inputs/outputs UB Upper byte (I/O 9~16) CE Chip enable VCC Power supply WE Write enable input VSS Ground OE Output enable input NC No connection

TM Technology Inc. reserves the right P. 3 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A ABSOLUTE MAXIMUM RATINGS* PARAMETER SYM MIN. MAX. UNIT Voltage on Any Pin Relative to VSS V R -0.2 +4.6 V V Power Dissipation PD - 1.0 W Storage Temperature TSTG -55 +150 °C Temperature Under Bias IBIAS -10 / -40 +70 / +85 °C *Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE CE OE WE LB UB I/O 1~8 I/O 9~16 MODE Power H X* X* X* X* High-Z High-Z Deselected Standby X* X* X* H H High-Z High-Z Deselected Standby L H H L X* High-Z High-Z Output Disabled Active L H H X* L High-Z High-Z Output Disabled Active L L H L H Data Out High-Z Lower Byte Read Active L L H H L High-Z Data Out Upper Byte Read Active L L H L L Data Out Data Out Word Read Active L X* L L H Data In High-Z Lower Byte Write Active L X* L H L High-Z Data In Upper Byte Write Active L X* L L L Data In Data In Word Write Active *Note: X = Don’t Care (Must be low or high state), L = Low, H = High

TM Technology Inc. reserves the right P. 4 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A RECOMMENDED OPERATING CONDITIONS PARAMETER SYM MIN TYP MAX UNIT VIH 0.7Vcc - Vcc+0.3 V Input Voltage VIL -0.2 - 0.6 V OPERATING CHARACTERISTICS -45 -55 -70 -100 UNIT PARAMETER SYM. TEST CONDITIONS Min Max Min Max Min Max Min Max Input Leakage Current  ILI Vcc = Max, VIN = VSS to Vcc - 1 - 1 - 1 - 1 uA Output Leakage Current  ILO CE= VIH or OE = VIH or WE = VIL VIO = VSS to Vcc - 1 - 1 - 1 - 1 uA Operating Power Supply Current ICC CE = VIL, WE =VIH, OE = VIH , VIN = VIH or VIL, IOUT=0mA - 3 - 3 - 3 - 3 mA ICC1 Cycle time=1us, 100% duty, IIO=0mA, CE ≤ 0.2V, VIN ≥ VCC-0.2V or VIN ≤ 0.2V - 5 - 5 - 5 - 5 mA Average Operating Current ICC2 Cycle time=min, 100% duty, IIO=0mA, CE = VIL, VIN = VIH or VIL - 45 - 40 - 35 - 25 mA Standby Power Supply Current (TTL Level) ISB CE =VIH or LB = UB =VIH other input= VIL or VIH Standby Power Supply Current (CMOS Level) ISB1 CE ≥ Vcc-0.2V or LB = UB ≥Vcc-0.2V, VIN ≤ 0.2V or VIN ≥ Vcc-0.2V - 40 - 15 - 15 - 15 uA

TM Technology Inc. reserves the right P. 5 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A CAPACITANCE (f = 1 MHz, Ta = 25°C,) PARAMETER SYMBOL CONDITION MAX. UNIT Input Capacitance CIN VIN = 0V 8 pF Input/ Output Capacitance CI/O VIN = VOUT= 0V 10 pF Note: This parameter is guaranteed by device characterization and is not production tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels 0.6V to 0.7Vcc Input Rise and Fall Times 3.0 ns Input and Output Timing Reference Level 1.4V CL =30pF+1TTL Load(45/55/70ns) Output Load CL =100pF+1TTL Load(Load for 100ns) AC TEST LOADS AND WAVEFORM DQ Z0 = 50 ohm 50 ohm 30 pF Vt =1.4V Fig.A * Including Scope and Jig Capacitance TTL CL* Fig.B Output Load Equivalent RL CL

TM Technology Inc. reserves the right P. 6 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A AC CHARACTERISTICS(Vcc=2.7 to 3.6V, SSV = 0V, Ta = -10 ~ +70 °C / -40°C ~ 85°C) (1) READ CYCLE -45 -55 -70 -100 PARAMETER SYM. Min Max Min Max Min Max Min Max UNIT Read Cycle Time tRC 45 - 55 - 70 - 100 - ns Address Access Time tAA - 45 - 55 - 70 - 100 ns Chip Enable Access Time tACE - 45 - 55 - 70 - 100 ns Output Enable Access Time tOE - 25 - 30 - 35 - 50 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tLZ 10 - 10 - 10 - 10 - ns Chip Disable to Output in High-Z tHZ - 15 - 20 - 25 - 30 ns Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - 5 - ns Output Disable to Output in High-Z tOHZ - 15 - 20 - 25 - 30 ns LB , UB Access Time tBA - 45 - 55 - 70 - 100 ns LB , UB Enable to Output in Low-Z tBLZ 10 - 10 - 10 - 10 - ns LB , UB Disable to Output in High-Z tBHZ - 15 - 20 - 25 - 30 ns (2)WRITE CYCLE -45 -55 -70 -100 PARAMETER SYM. Min Max Min Max Min Max Min Max UNIT Write Cycle Time tWC 45 - 55 - 70 - 100 - ns Chip Enable to Write End tCW 35 - 50 - 60 - 80 - ns Address Valid to Write End tAW 35 - 50 - 60 - 80 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 30 - 45 - 50 - 70 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Data Valid to Write End tDW 20 - 25 - 30 - 40 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z tWHZ - 15 - 20 - 25 - 30 ns Output Active from Write End tOW 5 - 5 - 5 - 5 - ns

TM Technology Inc. reserves the right P. 7 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A TIMING WAVEFORMS READ CYCLE 1 (Address Controlled, CE = OE = ILV , WE =VIH , LB or/and UB = ILV ) READ CYCLE 2 (WE =VIH ) DON'T CARE UNDEFINED CE tOE UB / LB tBA tOHZ D OUT OE tRC tACE tAA tOLZtBLZ tLZ High-Z tBHZ tHZ tOH Address Notes (READ CYCLE) : 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device and from device to device interconnection. 5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE =VIL . tRC Address tOH tAA D OUT P revious D a ta V alid D a ta V a lid

TM Technology Inc. reserves the right P. 8 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A WRITE CYCLE 1 ( WE Controlled) WRITE CYCLE 2 ( CE Controlled) tWC tWHZ tDW D IN tDH tWR tAS tWP Address UB / LB CE WE D OUT tAW tCW tOW High-Z High-Z DON'T CARE UNDEFINED tWC tDW D IN tDH tWR tAS tWP tCW Address CE WE D OUT UB / LB tAW High-Z High-Z High-Z

TM Technology Inc. reserves the right P. 9 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A WRITE CYCLE 3 ( UB ,LB Controlled) NOTES ( WRITE CYCLE ) : 1. A write occurs during the overlap of a low CE , a low WE . A write begins at the lateat transition among CE goes low, WE going low. A write end at the earliest transition among CE going high, WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. DON'T CARE UNDEFINED tWC tDW D IN tDH tWR tAS tWP tCW Address CE WE D OUT UB / LB tAW High-Z High-Z High-Z

TM Technology Inc. reserves the right P. 10 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A DATA RETENTION CHARACTERISTICS PARAMETER SYM. TEST CONDITION MIN. MAX. UNIT VCC for Data Retention V DR 2.0 - V Data Retention Current I CCDR - 15/40* uA Chip Deselect to Data Retention Time tCDR 0 - ns Operation Recovery Time t R CE ≥VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V tRC - ns *note : the data retention current ‘max=40uA’ only for –45ns . DATA RETENTION WAVEFORM tCDR CE tR Vcc CE >Vcc- 0.2V VDR > 2.0V VIH VIH Vcc_typ Vcc_typ Data Retention Mode

TM Technology Inc. reserves the right P. 11 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A PACKAGE DIMENSIONS 44-LEAD TSOP-II SEATING PLANE INDEX MARK Mirror finish 2344 EE 1 D bec A A2 A1 L Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom Max A1 0.05 - 0.1 0.002 - 0.004 θ 0 - 8 0 - 8

TM Technology Inc. reserves the right P. 12 Publication Date: NOV. 2002 to change products or specifications without notice. Revision:A P A C K A G E D I M E N S I O N S Units : millimeters 48-pin CSP (8 row x 6 column) 48 BALL FINE PITCH BGA (0.75mm ball pitch) Bottom ViewTop View B 0.50 0.50C B/2 C1/2 #A1 A1 INDEX MARK D 0.36 E1E A Y Symbol min typ max A - 0.75 - B 5.95 6.00 6.05 B1 - 3.75 - C 7.95 8.00 8.05 C1 - 5.25 - D 0.25 0.30 0.35 E - 1.10 1.20 E1 - 0.95 - E2 0.20 0.25 0.30 Y - - 0.08 Notes : 1. Bump counts : 48 (8 row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75) typ. 3. All tolerance are ±0.050 unless otherwise specified. 4. ‘Y’ is coplanarity : 0.08(max) 5. Units : mm