T15N1024A TMT | Alldatasheet

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TM Technology Inc. reserves the right P. 1 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E SRAM 128K X 8 LOW POWER CMOS STATIC RAM

FEATURES

  • Low-power consumption - Active: 40mA at 55ns (Max.) - CMOS Stand-by: 10uA (Max.)
  • 55/70/100 ns access time
  • Equal access and cycle time
  • Single +2.4V to 3.6V Power Supply
  • TTL compatible , Tri-state output
  • Common I/O capability
  • Automatic power-down when deselected
  • Available in 32-pin SOP ,TSOP-I(8x20mm), TSOP-I(8x13.4mm) ,48-pin CSP packages
  • Operating temperature : Commercial : 0 ~ +70 °C Industrial : -40 ~ +85 °C PART NUMBER EXAMPLES PART NO. PACKAGE CODE Operating Temperature T15N1024A-55D T15N1024A-70H T15N1024A-100P T15N1024A-100C D=SOP H=TSOP-I(8x20) P=TSOP-I(8x13.4) C=CSP 0 ~ +70 °C T15N1024A-55DI T15N1024A-70HI T15N1024A-100PI T15N1024A-100CI D=SOP H=TSOP-I(8x20) P=TSOP-I(8x13.4) C=CSP -40 ~ +85 °C GENERAL DESCRIPTION The T15N1024A is a very Low Power CMOS Static RAM organized as 131,072 words by 8 bits. That operates on a wide voltage range from 2.4V to 3.6V power supply, Fabricated using high performance CMOS technology, Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Data retention is guaranteed at a power supply voltage as low as 1.5V. BLOCK DIAGRAM DECODERA0 A16 I/O8 Vcc ... ... DATA I/O CORE ARRAY Vss I/O1WE OE CE1 CONTROL CIRCUIT CE2

TM Technology Inc. reserves the right P. 2 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E PIN CONFIGURATIONS SOP NC A16 A14 A12 I/O1 I/O2 I/O3 VSS VDD A15 CE2 WE A13 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 TSOP-I (8x20mm) A11 A13 WE CE2 A15 VDD NC A16 A14 A12 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 TSOP-I (8x13.4mm) A11 A13 WE CE2 A15 VDD NC A16 A14 A12 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 I/O5 VDD VSS I/O6 I/O7 I/O8 A9 A10 NC OE NC CE1 A16 A11 A12 A15 A13 A14 I/O4 I/O3 VDD VSS I/O2 I/O1 CE2 A3 A6 A7A4WE NC A 654321 H G F E D C B 48-CSP TOP VIEW PIN DESCRIPTIONS SYMBOL DESCRIPTIONS SYMBOL DESCRIPTIONS A0 ~ A16 Address inputs OE Output enable input I/O0~I/O8 Data inputs/outputs V DD Power supply CE1 ,CE2 Chip enable V SS Ground WE Write enable input NC No connection

TM Technology Inc. reserves the right P. 3 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E ABSOLUTE MAXIMUM RATINGS* PARAMETER SYM MIN. MAX. UNIT Voltage on Any Pin Relative to Gnd V R -0.5 +4.6 V V Power Dissipation PD - 0.7 W Storage Temperature TSTG -55 +150 °C commercial 0 +70 Operating Temperature industrial Ta -40 +85 °C *Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE CE 1 CE2 WE OE DATA MODE H X X X High-Z Standby X L X X High-Z Standby L H H L Data Out Active, Read L H H H High-Z Active, Output Disable L H L X Data In Active, Write *Note: X = Don’t Care, L = Low, H = High

TM Technology Inc. reserves the right P. 4 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E OPERATING CHARACTERISTICS (Vcc = 2.4 to 3.6V, Gnd = 0V, Ta = 0 ~ +70 °C /-40°C to 85°C) -55 -70 -100 PARAMETER SYM. TEST CONDITIONS Min Max Min Max Min Max UNIT Input Leakage Current  ILI Vcc = Max, VIN = Gnd to Vcc - 1 - 1 - 1 uA Output Leakage Current  ILO CE1 = VIH or CE2= VIL or OE = VIH or WE = VIL VOUT= Gnd to Vcc - 1 - 1 - 1 uA Operating Power Supply Current ICC CE1 = VIL,CE2= VIH, WE =VIH, OE = VIH , VIN = VIH or VIL, IOUT=0mA - 2 - 2 - 2 mA ICC1 Cycle time=1us, 100% duty, IOUT=0mA, CE1 ≤ 0.2V, CE2 ≥ VCC-0.2V, VIN ≤ 0.2V - 3 - 3 - 3 mA Average Operating Current ICC2 Cycle time=min, 100% duty, IOUT=0mA, CE1 = VIL,CE2= VIH , VIN = VIH or VIL - 40 - 35 - 25 mA Standby Power Supply Current (TTL Level) ISB CE1 =VIH CE2= VIL - 0.5 - 0.5 - 0.5 mA Standby Power Supply Current (CMOS Level) ISB1 CE1 ≥ Vcc-0.2V, CE2 ≥ VCC-0.2V or CE2 ≤ 0.2V VIN ≤ 0.2V or VIN ≥ Vcc-0.2V - 10 - 10 - 10 uA Output Low Voltage VOL IOL = 1.0mA - 0.4 - 0.4 - 0.4 V Output High Voltage VOH IOH = -0.5 mA 2.1 - 2.1 - 2.1 - V

TM Technology Inc. reserves the right P. 5 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E RECOMMENDED OPERATING CONDITIONS PARAMETER SYM MIN MAX UNIT Vcc 2.4 3.6 V Supply Voltage Gnd 0.0 0.0 V VIH 1.6 Vcc+0.2 V Input Voltage VIL -0.3 0.4 V CAPACITANCE (f = 1 MHz, Ta = 25°C,) PARAMETER SYMBOL CONDITION MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/ Output Capacitance CI/O VIN = VOUT= 0V 8 pF Note: This parameter is guaranteed by device characterization and is not production tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels 0.2V to 2.1V Input Rise and Fall Times 3.0 ns Input and Output Timing Reference Level 1.4V CL =30pF+1TTL Load(55ns/70ns) Output Load CL =100pF+1TTL Load(Load for 100ns) AC TEST LOADS AND WAVEFORM DQ Z0 = 50 ohm 50 ohm 30 pF Vt =1.4V Fig.A * Including Scope and Jig Capacitance TTL CL* Fig.B Output Load Equivalent RL CL

TM Technology Inc. reserves the right P. 6 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E AC CHARACTERISTICS(Vcc=2.4 to 3.6V, Gnd = 0V, Ta = 0 ~ +70 °C /-40°C to 85°C) (1) READ CYCLE -55 -70 -100 PARAMETER SYM. Min Max Min Max Min Max UNIT Read Cycle Time tRC 55 - 70 - 100 - ns Address Access Time tAA - 55 - 70 - 100 ns Chip Enable Access Time tACE - 55 - 70 - 100 ns Output Enable Access Time tOE - 30 - 35 - 50 ns Output Hold from Address Change tOH 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tLZ 10 - 10 - 10 - ns Chip Disable to Output in High-Z tHZ - 20 - 25 - 30 ns Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - ns Output Disable to Output in High-Z tOHZ - 20 - 25 - 30 ns (2)WRITE CYCLE -55 -70 -100 PARAMETER SYM. Min Max Min Max Min Max UNIT Write Cycle Time tWC 55 - 70 - 100 - ns Chip Enable to Write End tCW 50 - 60 - 80 - ns Address Valid to Write End tAW 50 - 60 - 80 - ns Address Setup Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 45 - 50 - 70 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Data Valid to Write End tDW 25 - 30 - 40 - ns Data Hold Time tDH 0 - 0 - 0 - ns Write Enable to Output in High-Z tWHZ - 25 - 25 - 30 ns Output Active from Write End tOW 5 - 5 - 5 - ns

TM Technology Inc. reserves the right P. 7 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) Address Dout Previous Data Vaild Data Vaild tOH tAA tRC DON'T CARE UNDEFINED READ CYCLE 2 (Chip Enable Controlled) CE1 Dout CE2 tLZ tACE tHZ DON'T CARE UNDEFINED Notes (READ CYCLE) : 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device and from device to device interconnection. 5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with 1CE =VIL .

TM Technology Inc. reserves the right P. 8 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E WRITE CYCLE 1 ( WE Controlled) D out CE1 Addr ess CE2 WE D IN t WC t AW t WR t CW t AS t WP t WH Z t OW t DHt DW Hi g h- Z Hi g h- Z DON' T CARE UNDEFI NED WRITE CYCLE 2 ( CE Controlled) D out CE1 Addr es s CE2 WE D IN t WC t AW t WR t CW t AS t WP t DHt DW Hi gh- Z Hi gh- Z DON' T CARE UNDEFI NED NOTES ( WRITE CYCLE ) : 1. A write occurs during the overlap of a low 1CE , a high CE2 and a low WE . A write begins at the lateat transition among 1CE goes low, CE2 going high and WE going low. A write end at the earliest transition among 1CE going high, CE2 going low and WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of 1CE going low or CE2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change.

TM Technology Inc. reserves the right P. 9 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E DATA RETENTION CHARACTERISTICS PARAMETER SYM. TEST CONDITION MIN. MAX. UNIT VCC for Data Retention V DR 1CE ≥ VDD -0.2V 1.5 - V Data Retention Current I CCDR CE2 ≤ 0.2V - 5* uA Chip Deselect to Data Retention Time t CDR VIN ≥ Vcc -0.2V or 0 - ns Operation Recovery Time t R V IN ≤ 0.2V t RC - ns * VCC=1.8V DATA RETENTION WAVEFORM Data Retention Mode VDR > 1.5VVcc_typ tCDR VCC CE1 VIH CE1>VCC-0.2V VIH tR Vcc_TYP VIH CE2 < 0.2V VIHCE2

TM Technology Inc. reserves the right P. 10 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E PACKAGE DIMENSIONS 32-LEAD SOP 1 16 1732 EH E b D S AA2 Seating Plane ey See Detail F LE C L Detail F Dimension in inches Dimension in mm Symbol D - 0.805 0.817 - 20.45 20.75 Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec.

TM Technology Inc. reserves the right P. 11 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E PACKAGE DIMENSIONS 32-LEAD TSOP (8x20mm) DIMENSIONS IN INCHES DIMENSIONS IN MM SYMBOL MIN NOM MAX MIN NOM MAX A1 0.002 - 0.006 0.05 - 0.15 D 0.787 TYP 20.00 TYP Db 0.724 TYP 18.40 TYP E 0.315 TYP 8.00 TYP L1 0.032 TYP 0.813 TYP θ 0°~12° 0 °~12°

TM Technology Inc. reserves the right P. 12 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x13.4mm) SYMBOL Dimension in inches Dimension in mm A 0.044(MAX) 1.10(MAX) A1 0.004±0.002 0.05±0.05 A2 0.041(MAX) 1.02(MAX) e 0.020(TYP.) 0.5(TYP.) y 0.002(MAX) 0.05(MAX) HD 16 17 D "A" C b e A E L L1D etail "A " Seati ng pl ane Seati ng pl ane y

TM Technology Inc. reserves the right P. 13 Publication Date: FEB. 2003 to change products or specifications without notice. Revision:E P A C K A G E D I M E N S I O N S Units : millimeters 48-pin CSP (8 row x 6 column) 48 BALL FINE PITCH BGA (0.75mm ball pitch) Bottom ViewTop View B 0.50 0.50C B/2 C1/2 #A1 A1 INDEX MARK D 0.30 E1E A Y Symbol min typ max A - 0.75 - B 5.95 6.00 6.05 B1 - 3.75 - C 7.95 8.00 8.05 C1 - 5.25 - D 0.25 0.30 0.35 E - 1.10 1.20 E1 - 0.95 - E2 0.20 0.25 0.30 Y - - 0.08 Notes : 1. Bump counts : 48 (8 row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75) typ. 3. All tolerance are ±0.050 unless otherwise specified. 4. ‘Y’ is coplanarity : 0.08(max) 5. Units : mm