T15M256B TMT | Alldatasheet

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TM Technology Inc. reserves the right P. 1 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A SRAM 32K X 8 LOW POWER CMOS STATIC RAM

FEATURES

  • High speed access time: 50/70/85/100ns
  • Low power supply current : - Operating :35mA(max) - Standby : 10uA
  • Power supply : 5V (± 10%)
  • Fully static operation – No clock or refreshing required
  • All inputs and outputs directly LVTTL compatible
  • Common I/O capability
  • Data retention voltage : 1.5V (min)
  • Available packages : 28-pin DIP(600mil),SOJ, SOP, TSOP-I (8x13.4mm forward type and reverse type).
  • Operating temperature : - 0 ~ +70 °C - -40 ~ +85 °C PART NUMBER EXAMPLES PART NO. PACKAGE CODE Operating Temperature T15M256B-70N T15M256B-70J T15M256B-70D T15M256B-85P T15M256B-85R N=DIP J=SOJ D=SOP TSOP-I(Forward) R= TSOP-I(Reverse) 0 ~ +70 °C T15M256B-70NI T15M256B-70JI T15M256B-70DI T15M256B-85PI T15M256B-85RI N=DIP J=SOJ D=SOP TSOP-I(Forward) R= TSOP-I(Reverse) -40 ~ +85 °C GENERAL DESCRIPTION The T15M256B is a low power CMOS static RAM. organized as 32,768 x 8 bits that operates on a single 5-volt power supply. Low operating and standby current . Data retention is guaranteed at a power supply voltage as low as 1.5V. This device is packaged in a standard 28-pin DIP(600mil), SOJ, SOP, TSOP-I forward and reverse type. BLOCK DIAGRAM DECODER CONTROL A0 → A14 → CS → OE → WE → ← I/O 1 ← I/O 8 Vcc → DATA I/O CORE ARRAY →Vss

TM Technology Inc. reserves the right P. 2 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A PIN CONFIGURATION A12 A14 I/O1 I/O2 I/O3 Vss Vcc A13 A11 A10 I/O8 I/O7 I/O6 I/O5 I/O4 WE OE CS DIP SOJ A12 A14 I/O1 I/O2 I/O3 Vss Vcc A13 A11 A10 I/O8 I/O7 I/O6 I/O5 I/O4 WE OE CS SOP PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A14 Address Inputs I/O1 - I/O8 Data Inputs/Outputs CS Chip Select Inputs WE Write Enable OE Output Enable Vcc Power Supply Vss Ground TSOP-I Forward OE A11 A13 WE VCC A14 A12 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 TSOP-I Reverse A12 A14 VCC WE A13 A11 OE I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10

TM Technology Inc. reserves the right P. 3 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Supply Voltage to Vss Potential -0.5 to + 7V V Inputs to Vss Potential -0.5 to Vcc +0.5 V Power Dissipation 0.7 W Storage Temperature -60 to +150 °C RECOMMENDED OPERATING CONDITIONS PARAMETER SYM MIN TYP MAX UNIT Supply Voltage Vcc 4.5 5 5.5 V Input Voltage, low VIL -0.3 - 0.8 V Input Voltage, high VIH 2.2 - Vcc+0.3 V Ambient Temperature TA 0/-40 - +70/+85 °C TRUTH TABLE CS OE WE MODE I/O1- I/O8 Power H X X Not Selected High-Z Standby L H H Output Disable High-Z Active L L H Read Data Out Active L X L Write Data In Active OPERATING CHARACTERISTICS PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Input Leakage Current ILI Vin=Vss to Vcc - - 1 uA Output Leakage Current ILO VI/O=Vss to Vcc , CS = VIH or OE= VIH or WE = VIL - - 1 uA Output Low Voltage VOL IOL = + 2.1mA - - 0.4 V Output High Voltage VOH IOH = - 1.0mA 2.4 - - V -50 - - 35 mA -70 - - 30 mA -85 - - 25 mA Operating Power Supply Current Icc CS =VIL, I/O=0mA Cycle = MIN. Duty = 100% -100 - - 20 mA ISB CS =VIH , Cycle=min, Duty=100% - - 0.3 mA Standby Power Supply Current ISB1 CS ≥ Vcc-0.2V - - 10 uA

TM Technology Inc. reserves the right P. 4 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A CAPACITANCE (Vcc = 5V / ± 10%, Ta = 25°C, f = 1 MHz) PARAMETER SYMBOL CONDITION MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/ Output Capacitance CI/O VOUT= 0V 8 pF Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels 0V to 3V Input Rise and Fall Times 3 ns Input and Output Timing Reference Level 1.5V Output Load See Fig. 1,2 AC TEST LOADS AND WAVEFORM R1 - 1928 ohm OUTPUT 30pF Including Jig and Scope 1020 ohm R1- 1928 ohm5V OUTPUT 5pF Including Jig and Scope 1020 ohm (For T CLZ , TOLZ , TCHZ , TOHZ , TWHZ , TOW ) Fig 1 Fig 2

TM Technology Inc. reserves the right P. 5 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A AC CHARACTERISTICS (Vcc= 5V / ± 10%, Vss = 0V, Ta =0 ~ +70 °C/ -40 to 85°C) (1) READ CYCLE -50ns -70ns -85ns -100ns PARAMETER SYM. UNIT Read Cycle Time tRC 50 - 70 - 85 - 100 - ns Address Access Time tAA - 50 - 70 - 85 - 100 ns Chip Select Access Time tACS - 50 - 70 - 85 - 100 ns Output Enable to Output Valid tAOE - 25 - 35 - 40 - 50 ns Chip Selection to Output in Low Z tCLZ* 7 - 10 - 10 - 10 - ns Output Enable to Output in Low Z tOLZ* 5 - 5 - 5 - 5 - ns Chip Deselection to Output in High Z tCHZ* - 20 - 25 - 30 - 30 ns Output Disable to Output in High Z tOHZ* - 20 - 25 - 30 - 30 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns * These parameters is measured with 5pF test load. (2)WRITE CYCLE -50ns -70ns -85ns -100ns PARAMETER SYM. UNIT Write Cycle Time tWC 50 - 70 - 85 - 100 - ns Chip Selection to End of Write tCW 40 - 60 - 70 - 80 - ns Address Valid to End of Write tAW 40 - 60 - 70 - 80 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 30 - 50 - 60 - 70 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Data Valid to End of Write tDW 25 - 30 - 35 - 40 - ns Data Hold from End of Write tDH 0 - 0 - 0 - 0 - ns Write to Output in High Z tWHZ* - 20 - 25 - 30 - 30 ns Output Active from End of Write tOW 5 - 5 - 5 - 5 - ns * These parameters is measured with 30pF test load.

TM Technology Inc. reserves the right P. 6 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Min Typ max unit Vcc for data retention V DR CS ≥≥≥≥ Vcc-0.2V 1.5 - - V Data retention current I DR Vcc=5.0, CS ≥≥≥≥ Vcc-0.2V - 10 uA Data retention set-up time tCDR 0 - - Recovery time tR See data retention waveform 5 - - ms DATA RETENTION WAVE FORM Data Retention Mode VDR > 1.5VVcc_typ tCDR VCC CS VIH CS >VCC-0.2V VIH Vcc_TYP tR

TM Technology Inc. reserves the right P. 7 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) tRC Address tOH tAA DOUT tOH READ CYCLE 2 (Chip Select Controlled) tACS CS tCHZtCLZ DOUT READ CYCLE 3 (Output Enable Controlled) DON'T CARE UNDEFINED tRC tCLZ tCHZ DOUT tOHZ tOH tACS tOLZ tAOE tAA Address CS OE

TM Technology Inc. reserves the right P. 8 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A WRITE CYCLE 1 ( OE CLOCK) tWC tOHZ tDW D IN tDH tWR tAS tWP tAW tCW Address CS OE WE (1,4) D OUT WRITE CYCLE 2 ( OE = VIL Fixed) DON'T CARE UNDEFINED tWC tOW tDW DIN tDH tWR tAS tWP tAW tCW Address CS WE (2 ) DOUT tOH (3) tWHZ (1,4)

TM Technology Inc. reserves the right P. 9 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured ± 500 mV from steady state with CL = 5pF. This parameter is guaranteed but not 100% tested. 5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

TM Technology Inc. reserves the right P. 10 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A PACKAGE DIMENSIONS 28-LEAD DIP SRAM (600 mil) A B CC1 D D1C2 Dimension in inches Dimension in mm Symbol

TM Technology Inc. reserves the right P. 11 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A PACKAGE DIMENSIONS 28-LEAD SOJ SRAM (300 mil) SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 0.710±0.002 18.03±0.05 y 0.004(MAX) 0.10(MAX)

TM Technology Inc. reserves the right P. 12 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A PACKAGE DIMENSIONS 28-LEAD SOP 1 14 1528 EH E b D S AA2 Seating Plane e y See Detail F LE C L Detail F Dimension in inches Dimension in mm Symbol D - 0.713 0.733 - 18.110 18.618 S - 39 - - 1.0 - Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec.

TM Technology Inc. reserves the right P. 13 Publication Date: MAY. 2002 to change products or specifications without notice. Revision:A PACKAGE DIMENSIONS 28-LEAD TSOP-I FORWARD AND REVERSE (8X13.4mm) SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 0.047(max.) 1.20(max.) A1 0.004 ±0.002 0.10 ±0.05 A2 0.039 ±0.002 1.00 ±0.05 b 0.008(typ.) 0.20(typ.) c 0.006(typ.) 0.15(typ.) Db 0.465 ±0.004 11.80 ±0.10 E 0.315 ±0.004 8.00 ±0.10 e 0.022(typ.) 0.55(typ.) D 0.528 ±0.008 13.40 ±0.20 L 0.020 ±0.004 0.50 ±0.10 L1 0.0315 ±0.004 0.80 ±0.10 y 0.004(max.) 0.10(max.) D 14 15 Db "A" C b e A E L 0.010 Detail "A" Gauge plane Seating plane Seating plane y