T15L256A TMT | Alldatasheet

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Technical content

Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: APR. 2001 to change products or specifications without notice. Revision:C SRAM 32K X 8 LOW POWER CMOS STATIC RAM

FEATURES

  • Access time: 35ns/70ns
  • Low power consumption : Active 200 mW(typ.)
  • Low operating current : 50mA
  • Single + 3.3V power supply
  • Fully static operation – No clock or refreshing required
  • All inputs and outputs directly LVTTL compatible
  • Common I/O capability
  • Available packages : 28-pin 300 mil SOJ, 28-pin SOP, TSOP-I (forward type ).
  • Output enable (OE ) available for very fast access PIN CONFIGURATION A12 A14 I/O1 I/O2 I/O3 Vss Vcc A13 A11 A10 I/O8 I/O7 I/O6 I/O5 I/O4 WE OE CS SOJ SOP GENERAL DESCRIPTION The T15L256A is a high speed, low power CMOS static RAM organized as 32,768 x 8 bits that operates on a single 3.3 -volt power supply. This device is packaged in standard 28-pin 300 mil SOJ , 28-pin SOP, TSOP-I forward. BLOCK DIAGRAM DECODER CONTROL A0 → A14 → CS → OE → WE → ← I / O 1 ← I / O8 Vcc → DATA I/O CORE ARRAY →Vss PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A14 Address Inputs I/O1 - I/O8 Data Inputs/Outputs CS Chip Select Inputs WE Write Enable OE Output Enable Vcc Power Supply Vss Ground PART NUMBER EXAMPLES PACKAGE SPEED T15L256A-35J SOJ 35ns T15L256A-70P TSOP -I 70ns T15L256A-70D SO P 70ns TSOP-I OE A11 A13 WE VCC A14 A12 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: APR. 2001 to change products or specifications without notice. Revision:C DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Supply Voltage to Vss Potential -0.5 to + 4.6 V Inputs to Vss Potential -0.5 to Vcc +0.5 V Power Dissipation 0.5 W Storage Temperature -60 to +150 °C RECOMMENDED OPERATING CONDITIONS PARAMETER SYM MIN TYP MAX UNIT Supply Voltage Vcc Typ-5% 3.3 Typ+5% V Input Voltage, low VIL -0.3 - 0.8 V Input Voltage, high VIH 2.1 - Vcc+0.3 V Ambient Temperature TA 0 - 70 °C TRUTH TABLE CS OE WE MODE I/O1- I/O8 Vcc H X X Not Selected High-Z ISB, ISB1 L H H Output Disable High-Z Icc L L H Read Data Out Icc L X L Write Data In Icc OPERATING CHARACTERISTICS (Vcc = 3.3V± 5%, Vss = 0V, Ta = 0 to 70°C) PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Input Leakage Current ILI Vin=Vss to Vcc -10 - +10 uA Output Leakage Current ILO VI/O=Vss to Vcc , CS = VIH or OE= VIH or WE = VIL -10 - +10 uA Output Low Voltage VOL IOL= + 8.0mA - - 0.4 V Output High Voltage VOH IOH= - 4.0mA 2.4 - - V -35 - - 40 mA Operating Power Supply Current Icc CS =VIL, I/O=0mA Cycle = MIN. Duty = 100% -70 - - 35 mA ISB CS =VIH , Cycle=MIN, Duty=100% - - 8 mA Standby Power Supply Current ISB1 CS ≥ Vcc-0.2V,f=0MHz - - 0.8 mA Note: Typical characteristics are at Vcc = 3.3V, Ta = 25°C

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: APR. 2001 to change products or specifications without notice. Revision:C CAPACITANCE (Vcc = 3.3V, Ta = 25°C, f = 1 MHz) PARAMETER SYMBOL CONDITION MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/ Output Capacitance CI/O VOUT= 0V 8 pF Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels 0V to 3V Input Rise and Fall Times 3 ns Input and Output Timing Reference Level 1.5V Output Load CL =30pF,IOH/IOL= -4mA/8mA AC TEST LOADS AND WAVEFORM R1 320 ohm3.3V OUTPUT 30pF Including Jig and Scope 350 ohm R1 320 ohm3.3V OUTPUT 5pF Including Jig and Scope 350 ohm 3.0V 0 V 90% 90% 10% 10% 3ns 3ns (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) DQ Fig.1 Z0 = 50 ohm 50 ohm 30 pF Vt =1.5V DQ Fig.3 Z0 = 50 ohm ohm 5 pF Vt =1.5V Fig.2 Fig.4 Fig.5

Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date: APR. 2001 to change products or specifications without notice. Revision:C AC CHARACTERISTICS (Vcc=3.3V ± 5%, Vss = 0V, Ta = 0 to 70°C) (1) READ CYCLE Read Cycle Time TRC 35 - 70 - ns Address Access Time TAA - 35 - 70 ns Chip Select Access Time TACS - 35 - 70 ns Output Enable to Output Valid TAOE - 25 - 35 ns Chip Selection to Output in Low Z TCLZ* 3 - 3 - ns Output Enable to Output in Low Z T OLZ∗ 0 - 0 - ns Chip Deselection to Output in High Z TCHZ* - 25 - 35 ns Output Disable to Output in High Z TOHZ ∗ - 25 - 35 ns Output Hold from Address Change TOH 3 - 3 - ns * These parameters are sampled but not 100% tested. (2)WRITE CYCLE Write Cycle Time TWC 35 - 70 - ns Chip Selection to End of Write TCW 30 - 60 - ns Address Valid to End of Write TAW 30 - 60 - ns Address Setup Time TAS 0 - 0 - ns Write Pulse Width TWP 25 - 50 - ns Write Recovery Time TWR 0 - 0 - ns Data Valid to End of Write TDW 20 - 30 - ns Data Hold from End of Write TDH 0 - 0 - ns Write to Output in High Z TWHZ∗ - 10 - 25 ns Output Disable to Output in High Z TOHZ∗ - 10 - 25 ns Output Active from End of Write TOW 0 - 0 - ns * These parameters are sampled but not 100% tested.

Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date: APR. 2001 to change products or specifications without notice. Revision:C TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) tR C A d d r e s s tOH t AA D O U T tOH READ CYCLE 2 (Chip Select Controlled) tA CS C S tCH ZtCLZ D O U T READ CYCLE 3 (Output Enable Controlled) DON 'T CAR E UN DEF IN ED t RC t CLZ tCH Z D O U T tOH Z t OH t ACS t OLZ t AOE t AA A d d r e s s C S O E

Taiwan Memory Technology, Inc. reserves the right P. 6 Publication Date: APR. 2001 to change products or specifications without notice. Revision: C WRITE CYCLE 1 ( OE CLOCK) tWC tOHZ tDW DI N tDH tWR tAS tWP tAW tCW A d d r e s s CS O E WE (1, 4) D OU T WRITE CYCLE 2 ( OE = VIL Fixed) D ON 'T CAR E U N DE F INE D t WC tOW tD W D I N t DH t WR tAS tWP t AW t CW A d d r e s s C S W E (2) D O U T tOH (3) t WH Z (1,4 )

Taiwan Memory Technology, Inc. reserves the right P. 7 Publication Date: APR. 2001 to change products or specifications without notice. Revision: C Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured ± 500 mV from steady state with CL = 5pF. This parameter is guaranteed but not 100% tested. 5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

Taiwan Memory Technology, Inc. reserves the right P. 8 Publication Date: APR. 2001 to change products or specifications without notice. Revision: C PACKAGE DIMENSIONS 28-LEAD SOJ SRAM (300 mil) SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 0.710±0.002 18.03±0.05 y 0.004(MAX) 0.10(MAX)

Taiwan Memory Technology, Inc. reserves the right P. 9 Publication Date: APR. 2001 to change products or specifications without notice. Revision: C PACKAGE DIMENSIONS 28-LEAD TSOP-I SRAM (8X13.4mm) SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 0.047(max.) 1.20(max.) A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 b 0.008(typ.) 0.20(typ.) c 0.006(typ.) 0.15(typ.) Db 0.465±0.004 11.80±0.10 e 0.022(typ.) 0.55(typ.) D 0.528±0.008 13.40±0.20 L1 0.0315±0.004 0.80±0.10 y 0.004(max.) 0.10(max.) θ 0°°~5°° 0°° ~5°° D 14 15 Db "A" C b e A E L 0.010 Detail "A" Gauge plane Seating plane Seating plane y

Taiwan Memory Technology, Inc. reserves the right P. 10 Publication Date: APR. 2001 to change products or specifications without notice. Revision: C PACKAGE DIMENSIONS 28-LEAD SOP 1 14 1528 E HE b D S AA2 Seating Plane e y See Detail F LE C L Detail F Dimension in inches Dimension in mm Symbol S - 39 - - 1.0 - Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec.