T14L1024A TMT | Alldatasheet

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CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 1 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F SRAM 128K X 8 HIGH SPEED CMOS STATIC RAM

FEATURES

  • Fast Address Access Times : 10/12/15ns
  • Single 3.3V ±0.3V power supply
  • Low Power Consumption : 110/105/100mA
  • TTL I/O compatible
  • 2.0V data retention mode
  • Automatic power-down when deselected
  • Available packages : 32-pin 300 mil DIP/SOJ & 32-pin SOP/TSOP-I
  • Industry Standard Pin Assignment PIN CONFIGURATION TSOP-I A15 A14 A13 A12 WE CE2 A11 VCC NC A10 OE A16 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 GENERAL DESCRIPTION The T14L1024A is a one-megabit density, fast static random access memory organized as 131,072 words by 8 bits. It is designed for use in high performance memory applications such as main memory storage and high speed communication buffers. Fabricated using high performance CMOS technology, access times down to 10ns are achieved. Memory expansion by banking is easily accomplished using the chip enable pins CE1 and CE2. This device is packaged in a standard 32-pin 300 mil DIP/SOJ and 32-pin SOP/TSOP-I. BLOCK DIAGRAM PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A16 Address Inputs I/O0 - I/O7 Data Inputs/Outputs /CE1,CE2 Chip Select Inputs /WE Write Enable /OE Output Enable Vcc Power Supply Vss Ground PART NUMBER EXAMPLES PACKAGE SPEED T14L1024A-10J SOJ 300mil 10ns T14L1024A-10P TSOP-I 8x13.4mm 10ns T14L1024A-10H TSOP-I 8x20mm 10ns T14L1024A-10N DIP 300mil 10ns T14L1024A-10D SOP 10ns I/O0 I/O1 A10 NC Vcc A12 A13 A14 A15 A16 I/O7 I/O6 I/O5 A11 CE2 WE OE CE1 I/O2 Vss I/O4 I/O3 DIP SOJ SOP DECODERA0 A16 CE2 WE OE I/O7 Vcc DATA I/O CORE ARRAY Vss CE1 I/O0 ...

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 2 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER SYM RATING UNIT Power Supply Voltage Vcc -0.5 to 4.6 V Input Voltage VIN -0.5 to Vcc+0.5 V Output Voltage VOUT -0.5 to Vcc+0.5 V Operating Temperatrue TOPR 0 to +70 °C Storage Temperature TSTG -55 to +150 °C Power Dissipation PD 1.0 W Short Circuit Output Current IOUT 50 mA TRUTH TABLE CE1 CE2 OE WE MODE I/O0- I/O7 Vcc H X X X Not Selected High-Z ISB, ISB1 X L X X Not Selected High-Z ISB, ISB1 L H H H Output Disable High-Z Icc L H L H Read Data Out Icc L H X L Write Data In Icc OPERATING CHARACTERISTICS (Vcc = 3.3V ±0.3V, Ta = 0 to 70°C) PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT Power Supply Voltage Vcc 3.0 3.6 V Input Low Voltage VIL -0.5 0.8 V Input High Voltage VIH 2.1 Vcc+0.3 V Input Leakage Current ILI V IN =Vss to Vcc - 5 uA Output Leakage Current ILO VIN=Vss to Vcc , CE1 = VIH or CE2 = VIL or OE = VIH or WE = V IL - 5 uA Output Low Voltage VOL IOL = 4.0 mA - 0.4 V Output High Voltage VOH IOH =-2.0 mA 2.4 - V Operating Power Icc CE1 =VIL 10ns - 110 mA Supply Current CE2 = VIH ;f=max 12ns - 105 mA IO = 0mA 15ns - 100 mA Standby Power ISB CE1 = VIH , CE2 = VIL, IO = 0mA - 25 mA Supply Current ISB1 Vcc = max; CE1 > Vcc-0.2V or CE2< Vss+0.2V; f=0mhz; IO = 0mA - 5 mA Note: Typical characteristics are at Vcc = 3.3V, Ta = 25°C

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 3 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F RECOMMENDED OPERATING CONDITIONS PARAMETER SYM MIN TYP MAX UNIT Supply Voltage Vcc Typ-0.3 3.3 Typ+0.3 V Input Voltage, low VIL -0.3 - 0.8 V Input Voltage, high VIH 2.1 - Vcc+0.3 V Ambient Temperature TA 0 - 70 °C CAPACITANCE PARAMETER SYMBOL CONDITION MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/ Output Capacitance CI/O VOUT= 0V 8 pF Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels 0V to 3V Input Rise and Fall Times 3.0 ns Input and Output Timing Reference Level 1.5V Output Load CL =30pF,IOH /IOL = -2mA/4mA AC TEST LOADS AND WAVEFORM RL=50 ohm OUTPUT Zo=50 ohm 30pF R1 319 ohm3.3V OUTPUT 5pF Including Jig and Scope 353 ohm (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) Vt=1.5V

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 4 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F AC CHARACTERISTICS (Vcc=3.3V ±0.3V, Vss = 0V, Ta = 0 to 70°C) (1) READ CYCLE T14L1024A-10 T14L1024A-12 T14L1024A-15 PARAMETER SYM. UNIT Read Cycle Time tRC 10 - 12 - 15 - ns Address Access Time tAA - 10 - 12 - 15 ns Chip Enable Access Time tACS - 10 - 12 - 15 ns Output Enable to Output Valid tAOE - 6 - 7 - 7 ns Chip Enable to Output in Low Z tCLZ* 3 - 3 - 3 - ns Output Enable to Output in Low Z tOLZ* 0 - 0 - 0 - ns Chip Disable to Output in High Z tCHZ* - 5 - 6 - 7 ns Output Disable to Output in High Z tOHZ* - 5 - 6 - 7 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns * These parameters are sampled but not 100% tested. (2)WRITE CYCLE T14L1024A-10 T14L1024A-12 T14L1024A-15 PARAMETER SYM. UNIT Write Cycle Time tWC 10 - 12 - 15 - ns Chip Enable to End of Write tCW 8 - 10 - 11 - ns Address Valid to End of Write tAW 8 - 10 - 11 - ns Address Setup Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 8 - 10 - 11 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Data Valid to End of Write tDW 6 - 8 - 8 - ns Data Hold from End of Write tDH 0 - 0 - 0 - ns Write to Output in High Z tWHZ* - 5 - 6 - 6 ns Output Disable to Output in High Z tOHZ* - 5 - 6 - 7 ns Output Active from End of Write tOW 0 - 0 - 0 - ns * These parameters are sampled but not 100% tested.

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 5 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) Address Dout tOH tAA tRC tOH READ CYCLE 2 (Chip Enable Controlled) CE1 Dout CE2 tCLZ tACS tOHZ DON'T CARE UNDEFINED Address tAA tRC tOH OE tCHZ tAOE tOLZ

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 6 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F WRITE CYCLE 1 ( OE CLOCK) D out CE1 Address CE2 WE D IN t WC t AW t WRt CW t AS t WP t OHZ t DHt DW OE WRITE CYCLE 2 ( OE = VIL Fixed) D out CE1 A ddress CE2 WE D IN t WC t AW t WRt CW t AS t WP t WHZ t DHt DW t OW t OH DON' T CARE UNDEFI NED (2 ) (3 )(1 ,4)

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 7 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured ± 500 mV from steady state with CL = 5pF. This parameter is guaranteed but not 100% tested. 5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 8 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F PACKAGE DIMENSIONS 32-LEAD SOJ (300 mil) SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM A 0.140(MAX) 3.556(MAX) A1 0.026(MIN) 0.660(MIN) A2 0.100±0.005 2.540±0.127 B 0.018(TYP) 0.457(TYP) B1 0.028(TYP) 0.711(TYP) C 0.008(TYP) 0.203(TYP) D 0.823±0.005 20.904±0.127 E 0.335±0.010 8.509±0.254 E1 0.300±0.005 7.620±0.127 e 0.050(TYP) 1.270(TYP) L 0.086±0.010 2.184±0.254 y 0.003(MAX) 0.076(MAX)

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 9 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x20mm) DIMENSIONS IN INCHES DIMENSIONS IN MM SYMBOL MIN NOM MAX MIN NOM MAX A1 0.002 - 0.006 0.05 - 0.15 HD 0.787 TYP 20.00 TYP D 0.724 TYP 18.40 TYP E 0.315 TYP 8.00 TYP e 0.020 TYP 0.50 TYP L1 0.032 TYP 0.813 TYP θ 0° 3 ° 5 ° 0 ° 3 ° 5 ° HD 16 17 D "A" C b e A E L L1D etail "A " Seati ng pl ane Seati ng pl ane y

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 10 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x13.4mm) DIMENSIONS IN INCHES DIMENSIONS IN MM SYMBOL MIN NOM MAX MIN NOM MAX A1 0.002 - 0.006 0.05 - 0.15 HD 0.528 TYP 13.40 TYP D 0.465 TYP 11.80 TYP E 0.315 TYP 8.00 TYP e 0.020 TYP 0.50 TYP L1 0.032TYP 0.813 TYP θ 0° 3 ° 5 ° 0 ° 3 ° 5 ° HD 16 17 D "A" C b e A E L L1D etail "A " Seati ng pl ane Seati ng pl ane y

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 11 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F PACKAGE DIMENSIONS 32-LEAD DIP (300 mil) A B CC1 D D1C2 1 16 1732 Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom Max A - 40.64 41.15 - 1.60 1.62

CHtm Preliminary T14L1024A TM Technology, Inc. reserves the right P. 12 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:0.F PACKAGE DIMENSIONS 32-LEAD SOP 1 16 1732 EH E b D S AA2 Seating Plane ey See Detail F LE C L Detail F Dimension in inches Dimension in mm Symbol D - 0.805 0.817 - 20.45 20.75 Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec.