T0514TP CITC | Alldatasheet
Document overview
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Technical content
Features
Transient protection for high-speed data lines IEC 61000-4-2 (ESD) ±25kV (Air) ±17kV (Contact) IEC 61000-4-4 (EFT) 40A (5/50 ns) Cable Discharge Event (CDE) Package optimized for high-speed lines Ultra-small package (2.5mmx1.0mmx0.55mm) Protects four data lines Low capacitance: 0.6pF for each channel Low leakage current: 0.1uA@V (Typical)RWM Low clamping voltage Each I/O pin can withstand over 1000 ESD strikes for ±8kV contact discharge
Description
T0514TP is an ultra-low capacitance Transient Voltage Suppressor (TVS) designed to provide electrostatic discharge (ESD) protection for high- speed data interfaces. With typical capacitance of 0.6 pF only, T0514TP is designed to protect parasitic-sensitive systems against over-voltage and over-current transient events. It complies with IEC 61000-4-2 (ESD), Level 4 (±15kV air, ±8kV contact discharge), IEC 61000-4-4 (electrical fast transient - EFT) (40A,5/50 ns), very fast charged device model (CDM) ESD and cable discharge event (CDE), etc. data lines The combined features of ultra-low capacitance, ultra-small size and high ESD robustness high-frequency lines (e.g.,HDMI & DVI) applications.. The low camping voltage of the T0514TP guarantees a minimum stress on the protected IC.
Applications
Desktops, Servers and Notebooks MDDI Ports Display Ports High Definition Multi-Media Interface (HDMI) Digital Visual Interfaces (DVI) Mechanical Characteristics DFN2510-10L package Flammability Rating: UL 94V-0 Marking: Part number Circuit Diagram Pin Configuration DFN2510-10L (Top View) T0514TP uses ultra-small DFN2510-10L package. Each T0514TP device can protect four high-speed make T0514TP ideal for high-speed data ports and USB 2.0/3.0/3.1 Power and Data Line Protection I/O_1 I/O_3 I/O_2 I/O_4 GND GNDI/O_1 I/O_2 I/O_3 I/O_4 1 2 3 4 5 10 9 8 7 6 RoHS compliant□ Packaging: Tape and Reel□ Document ID : DS-22V17 Revised Date : 2017/07/20 Revision : C
Symbol Parameter Value Units VESD ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) ±25 ±17 kV TOPT Operating Temperature -55/+125 o C TSTG Storage Temperature -55/+150 C Electrical Characteristics (T = 25 C) Symbol Parameter VRWM Nominal Reverse Working Voltage IR Reverse Leakage Current @VRWM VBR Reverse Breakdown Voltage @I T IT Test Current for Reverse Breakdown VC Clamping Voltage @ IPP IPP Maximum Peak Pulse Current CESD Parasitic Capacitance VR Reverse Voltage f Small Signal Frequency IF Forward Current VF Forward Voltage @IF Symbol Test Condition Minimum Typical Maximum Units VRWM 5.0 V IR V = 5V,T = 25RWM C Between I/O and GND 0.1 1.0 μA VBR IT = 1mA Between I/O and GND 6.0 8.0 10.0 V VC IPP = 1A, tp = 8/20μs Between I/O and GND 12 V CESD VR = 0V, f = 1MHz Between I/O and GND pF CESD VR = 0V, f = 1MHz Between I/O and I/O pF 0.8 0.080.05 0.6 o o Ultra-Low Capacitance ESD Protection Device T0514TP Chip Integration Technology Corporation IF vF IR IT IPP vF vBR vRWM Current Uni-Directional TVS Document ID : DS-22V17 Revised Date : 2017/07/20 Revision : C
Ultra-Low Capacitance ESD Protection Device T0514TP Chip Integration Technology Corporation Voltage Sweeping of I/O to GND Insertion Loss S21 of I/O to GND Capacitance vs. Voltage of I/O to GND (f = 1MHz) Capacitance vs. Reverse Voltage ESD Clamping of I/O to GND (+8kV Contact per IEC 61000-4-2) Normalized Capacitance vs. Reverse Voltage ESD Clamping of I/O to GND (-8kV Contact per IEC 61000-4-2) -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 Clamping Voltage (V) . 50 100 150 200 Time (ns) -50 0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0 Clamping Voltage (V) -50 0 50 100 150 200 Time (ns) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Capacitance (pF) 0 1 2 3 4 5 Reverse Voltage (V) 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Normalized Capacitance 0 1 2 3 4 5 Reverse Voltage (V) -0.12 -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.12 Current (A) -2 -1 0 1 2 3 4 5 6 7 8 Voltage (V) -30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0.0 5.0 Insertion Loss (dB) Frequency (Hz) Document ID : DS-22V17 Revised Date : 2017/07/20 Revision : C
Application Information
lines simultaneously. The pin connection is shown in the figure below. Four parallel data lines, from inner IC to I/O port connector, coule connect to T0514TP four I/O pins directly. Pin 3&8 of T0514TP is the GND pin, which should connect to the GND of PCB. The wire should be as short as possible in order to minimize the parasitic inductance. PCB Layout Guidelines For optimum ESD protection and the whole circuit performance, the following PCB layout guidelines are recommended: should be as short as possible. It could reduce the ESD transient return path to GND. The vias connecting T0514TP GND pins to the PCB GND should be wide. Place possible. It could reduce the parasitic inductance and restrict ESD coupling into adjacent traces. Avoid running critical signals near board edges. T0514TP GND pin to the PCB GND rail path T0514TP as close to the connector port as T0514TP provides ESD protection for four data I/O1 I/O2 I/O4 I/O3 F pigure 1 T0514TP in connection in PCB Ultra-Low Capacitance ESD Protection Device T0514TP Chip Integration Technology Corporation GND To I/O Port Connector Date lines To I/O Port Connector Date lines To Inner IC Date lines To Inner IC Date lines 5 4 3 2 1 6 7 8 9 10 Document ID : DS-22V17 Revised Date : 2017/07/20 Revision : C
Figure 2 Layout Top View for HDMI Interface With T0514TP & T0514TL Ultra-Low Capacitance ESD Protection Device T0514TP Chip Integration Technology Corporation TMDS_D2+ TMDS_D2- TMDS_D1+ TMDS_D1- TMDS_D0+ TMDS_D0- TMDS_CLK+ TMDS_CLK- CEC NC SCL SDA GND +5V HTP_D TMDS_D2+ TMDS_D2- TMDS_D1+ TMDS_D1- TMDS_D0+ TMDS_D0- TMDS_CLK+ TMDS_CLK- HDMI RECEIVER HDMI CONNECTOR SCL SDA HTP_D T0514TL T0514TP T0514TP CEC 5 4 3 2 1 5 4 3 2 1 6 7 8 9 106 7 8 9 10 3 2 1 4 5 6 Document ID : DS-22V17 Revised Date : 2017/07/20 Revision : C
Ultra-Low Capacitance ESD Protection Device T0514TP Chip Integration Technology Corporation Eye Diagram Measurements for 1080P HDMI Data Transmission Figure 3 Eye Diagram Measurements for 1080P HDMI TDR Measurements for HDMI The combination of low capacitance, small package, and flow-through design means it is possible to use T0514TP to meet the HDMI impedance requirements of 100 Ohms 15%. Figures 4 shows impedance test result for a TDR± rise time of 100ps, using a CitrusCOM evaluation board with 100 Ohm differential traces. Measurements Were taken using a TDR method as outlined in the HDMI Compliance Test Specification(CTS). In this case, the device meets the HDMI CTS requirement of 100 Ohm 15% with plenty of margin.± Without TVS Without T0514TP Document ID : DS-22V17 Revised Date : 2017/07/20 Revision : C
Ultra-Low Capacitance ESD Protection Device T0514TP Chip Integration Technology Corporation D E Pin1 Dot by Marking e b L Pin1 Idenification Chamfer A Symbol Dimensions (mm) Minimum A b D E e L Dimensions (inch) Package Dimensions (Controlling dimensions are in millimetes) Maximum Minimum Maximum 0.500 0.600 0.020 0.024 0.000 0.050 0.000 0.002 0.150 0.250 0.006 0.010 2.450 2.550 0.096 0.100 0.950 1.050 0.037 0.041 0.300 0.400 0.012 0.016 0.150REF. 0.006REF. 0.500 BSC 0.020 BSC Document ID : DS-22V17 Revised Date : 2017/07/20 Revision : C
Tape and Reel Specification W P P0 P2 Φ2: 1.50±0.10 E F T Top Cover Tape
5 Max
Device Orientation in Tape Φ: 0.80±0.05 Symbol W A0 B0 K0 E F P P0 P2 T Dimensions (mm) 8.00+0.3 Marking Codes Pin1 Identification Note: (1)
Ordering Information
5V 3,000 7 Inch T0514TP 6SYWW "6S" is part number, while "YWW" is date code. o Ultra-Low Capacitance ESD Protection Device T0514TP Chip Integration Technology Corporation Pin1 Identification Note: (1) 6SXXXY "6S" is part number, fixed. (2) "XXX" is the last 3 characters of the wafer's Lot No., "Y" is the internal code. Or Document ID : DS-22V17 Revised Date : 2017/07/20 Revision : C
http://www.citcorp.com.tw/ Tel:886-3-5600628 Fax:886-3-5600636 ■CITC reserves the right to make changes to this document and its products and specifications at any time without notice. Customers should obtain and confirm the latest product information and specifications before final■ design, purchase or use. CITC makes no warranty, representation or guarantee regarding the suitability of its products for any■ particular purpose, nor does CITC assume any liability for application assistance or customer product design. CITC does not warrant or accept any liability with products which are purchased or used for any■ unintended or unauthorized application. No license is granted by implication or otherwise under any intellectual property rights of CITC.■ CITC products are not authorized for use as critical components in life support devices or systems■ without express written approval of CITC. Ultra-Low Capacitance ESD Protection Device T0514TP Chip Integration Technology Corporation Document ID : DS-22V17 Revised Date : 2017/07/20 Revision : C