T0501SA

T0501SA CITC | Alldatasheet

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Features

Description

Applications

Mechanical Characteristics Circuit Diagram I/O_1 I/O_2 Pin Configuration DFN0603 (Top View) T0501SA are ultra low capacitance ESD protection devices designed to protect high speed data interfaces. They are designed to replace 0201 size mul- tilayer varistors (MLVs) in portable applications such as cell phones,notebook computers, and other portable electronics. This device offers desirable characteristics for board level protection including fast response time, low operating and clamping voltage, and no device degradation. T0501SA has a typical capacitance of only 0.25pF.This allows it to be used on circuits operating. T0501SA is in a 2-pin DFN0603 package. It measures 0.6 x 0.3 mm with a nominal height of only 0.25mm.Leads are finished with lead-free finished with lead-free NiAu. Each device will protect one line operating at 5 volts. It gives the designer the flexibility to protect single lines in applications where arrays are not practical. The combination of small size and high ESD surge capability makes them ideal for use in portable applications such as cellular phones, digital cameras, and Mp3 players. Transient protection for high-speed data lines IEC 61000-4-2 (ESD) ±22kV (Contact) Protects one high-speed data line Low reverse current:<10nA typical (VR=5V) Working voltage: 5V Low capacitance: 0.25pF typical Dynamic resistance: 0.90 Ohms (Typ) Solid-state silicon-avalanche technology HDMI 1.3/1.4 and HDMI 2.0 USB 2.0 and USB 3.0 MHL LVDS Interfaces FM Antenna PCI Express eSATA Interfaces DFN0603-2L package Pb-Free, Halogen Free, RoHS/WEEE Compliant Nominal Dimensions: 0.6 x 0.3 x 0.25 mm Lead Finish: NiAu Molding compound flammability rating: UL 94V-0 Packaging : Tape and Reel ±25kV (Air)

Electrical Characteristics (T = 25 C) Rating Symbol Value Units Peak Pulse Power (tp = 8/20μs) Ppk 100 Watts Peak Pulse Current (tp = 8/20 IPP 4.5 A 1ESD per IEC 61000-4-2 (Air) 1ESD per IEC 61000-4-2 (Contact) VESD ±25 ±22 kV Operating Temperature TJ -55 to +125 °C Storage Temperature TSTG -55 to +150 °C Parameter Symbol Conditions Minimum Typical Maximum Units Reverse Stand-Off Voltage VRWM 5 V Reverse Breakdown Voltage VBR I = 1mAt 7 9 10 V Reverse Leakage Current IR V = 5V, T=25°CRWM 0.005 0.100 μA Clamping Voltage VC I = 1A, tp = 8/20μsPP 11 V Clamping Voltage VC I = 4A, tp = 8/20μsPP 15 V 2, 3, 4Dynamic Resistance RD tp = 100ns 0.90 Ohms Junction Capacitance Cj V = 0V, f = 1MHzR 0.25 0.4 pF Notes 1) ESD gun return path connected to ESD ground reference plane. 2) Transmission Line Pulse Test (TLP) Settings: tp= 100ns, tr= 0.2ns,I and V averaging window: t1 = 70ns to t2= 90ns. 3) Dynamic resistance calculated from I = 4A to I = 16A 4) Guaranteed by design. Not production tested TLP μs) TLP TLP TLP Document ID : DS-22V02 Revised Date : 2016/08/29 Revision : C Ultra-Low Capacitance ESD Protection Device T0501SA Chip Integration Technology Corporation

Time (ns) Time (ns) Typical Capacitance vs. Reverse Voltage TLP CharacteristicTypical Insertion Loss (S21) 0.2 0.4 0.6 0.8 1.2 1.4 0 1 2 3 4 5 Cj(VR) / Cj(VR=0V) Reverse Voltage - VR (V) f = 1 MHz 35.0 30.0 25.0 20.0 15.0 10.0 5.0 5.0 0.01 0.1 1 10 Loss (dB) Frequency (GHz) Clamping Voltage vs. Peak Pulse Current 0 1 2 3 4 5 Clamping Voltage -VC (V) Peak Pulse Current - IPP (A) Waveform Parameters: tr = 8μs td = 20μs 0 10 20 30 40 50 TLP Current (A) TLP Voltage (V) Transmission LinePulseTest (TLP)Sengs: tp= 100ns, tr= 0.2ns, ITLPandV TLPaveraging window: t1 =70ns tot2 =90ns ESD Clamping (+8kV Contact per IEC 61000-4-2) ESD Clamping (-8kV Contact per IEC 61000-4-2) -10 -20 -10 0 10 20 30 40 50 60 70 80 Clamping Voltage (V) Time (ns) Measuredwith50Ohmscopeinput impedance,2GHzbandwidth.Corrected for50Ohm,40dBaenuator. ESDgun return pathconnectedtoESDgroundplane. -40 -30 -20 -10 -20 -10 0 10 20 30 40 50 60 70 80 Clamping Voltage (V) Time (ns) Measuredwith50Ohmscopeinput impedance,2GHzbandwidth.Corrected for50Ohm,40dBaenuator. ESDgun returnpathconnected toESDground plane. 0.0 Document ID : DS-22V02 Revised Date : 2016/08/29 Revision : C Ultra-Low Capacitance ESD Protection Device T0501SA Chip Integration Technology Corporation

Application Information

retemaraPylbmesAs onitadnemmoceR Recommended Mounting Pattern 0.270 0.250 0.298 0.272 0.175 Stencil Aperture Mounting Pad Package Assembly Guidelines The small size of this device means that some care must be taken during the mounting process to insure reliable solde joint. The table below provides CITC recommended assembly guidelines for Mounting this device. The figure at the right details CITC recommended aperture based on the below recommendations. Not that these are only recommendations and should serve only as a starting point for design since there are many factors that affect the assembly process. The exact manufactur- ing parameters will require some experimentation to get the desired solder application. Solder Stencil Design Laser cut, Electro-polished Aperture shape Rectangular with rounded corners Solder Stencil Thickness 0.100 mm (0.004") Solder Paste Type Type 4 size sphere or smaller Solder Reflow Profile Per JEDEC J-STD-020 PCB Solder Pad Desig Non-Solder mask defined PCB Pad Finish OSP OR NiAu Document ID : DS-22V02 Revised Date : 2016/08/29 Revision : C Ultra-Low Capacitance ESD Protection Device T0501SA Chip Integration Technology Corporation

Carries Tape Specification Device Orientation in Tape Note: All dimensions in mm unless otherwise specified 10, 000T0501SA 7 inch A0 B0 K0 Date Code Location (Towards Sprocket Holes) Document ID : DS-22V02 Revised Date : 2016/08/29 Revision : C Ultra-Low Capacitance ESD Protection Device T0501SA Chip Integration Technology Corporation

Document ID : DS-22V02 Revised Date : 2016/08/29 Revision : C Ultra-Low Capacitance ESD Protection Device T0501SA Chip Integration Technology Corporation

http://www.citcorp.com.tw/ Tel:886-3-5600628 Fax:886-3-5600636 ■CITC reserves the right to make changes to this document and its products and specifications at any time without notice. Customers should obtain and confirm the latest product information and specifications before final■ design, purchase or use. CITC makes no warranty, representation or guarantee regarding the suitability of its products for any■ particular purpose, nor does CITC assume any liability for application assistance or customer product design. CITC does not warrant or accept any liability with products which are purchased or used for any■ unintended or unauthorized application. No license is granted by implication or otherwise under any intellectual property rights of CITC.■ CITC products are not authorized for use as critical components in life support devices or systems■ without express written approval of CITC. Document ID : DS-22V02 Revised Date : 2016/08/29 Revision : C Ultra-Low Capacitance ESD Protection Device T0501SA Chip Integration Technology Corporation