VYBRIDRSERIESEC NXP | Alldatasheet
Document overview
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Technical content
Features
- Operating characteristics – Voltage range 3 V to 3.6 V – Temperature range(ambient) -40 °C to 85 °C
- ARM® Cortex® A5 Core features – Up to 400 MHz ARM® Cortex® A5 core – 32 KB/32 KB I/D L1 Cache – 1.6 DMIPS/MHz based on ARMv7 architecture – NEON™ MPE (Media Processing Engine) Co- processor – Double Precision Floating Point Unit – 512 KB L2 cache (on selected part numbers only)
- ARM Cortex M4 Core features – Up to 133 MHz ARM Cortex M4 – Integrated DSP capability – 64 KB Tightly Coupled Memory (TCM) – 16 KB/16 KB I/D L1 Cache – 1.25 DMIPS/MHz based on ARMv7 architecture
- Clocks – 24 MHz crystal oscillator – 32 kHz crystal oscillator – Internal reference clocks (128 KHz and 24 MHz) – Phase Locked Loops (PLLs) – Low Jitter Digital PLLs
- System debug, protection, and power management – Various stop, wait, and run modes to provide low power based on application needs – Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents – Low voltage warning and detect with selectable trip points – Illegal opcode and illegal address detection with programmable reset or processor exception response – Hardware CRC module to support fast cyclic redundancy checks (CRC) – 128-bit unique chip identifier – Hardware watchdog – External Watchdog Monitor (EWM) – Dual DMA controller with 32 channels (with DMAMUX)
- Debug – Standard JTAG – 16-bit Trace port
- Timers – Motor control/general purpose timer (FTM) – Periodic Interrupt Timers (PITs) – Low-power timer (LPTMR0) – IEEE 1588 Timer per MAC interface (part of Ethernet Subsystem)
- Communications – Six Universal asynchronous receivers/transmitters (UART)/Serial communications interface (SCI) with LIN, ISO7816, IrDA, and hardware flow control – Four Deserial Serial peripheral interface (DSPI) – Four Inter-Integrated Circuit (I2C) with SMBUS support – Dual USB OTG Controller + PHY – Dual 4/8 bit Secure Digital Host controller – Local Media Bus (MLB50) – Dual 10/100 Ethernet (IEEE 1588) – Dual FlexCAN3
- Security – ARM TrustZone including the TZ architecture – Secure Non-Volatile Storage (SNVS) – Real Time Clock – Real Time Integrity Checker (RTIC) – TrustZone Watchdog (TZ WDOG) – Trust Zone Address Space Controller – Random Number Generator – Hashing – Secure JTAG
- Memory Interfaces – 8/16-bit DRAM Controller with support for LPDDR2/DDR3 - Up to 400 MHz (ECC supported for 8-bit only and not 16-bit) – 8/16-bit NAND Flash controller with ECC (ECC supported for 8-bit only and not 16-bit) – Dual Quad SPI with XIP (Execute-In-Place) – 8/16/32-bit External bus (Flexbus) NXP Semiconductors Document Number VYBRIDRSERIESEC Data Sheet: Technical Data Rev. 8, 01/2018 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
- Display and Video – Dual Display Control Unit (DCU) with support for color TFT display up to WVGA – Segmented LCD (3V Glass only) configurable as 40x4, 38x8, and 36x6 – Video Interface Unit (VIU) for camera – Open VG Graphics Processing Unit (GPU) – VideoADC
- Analog – Dual 12-bit SAR ADC with 1MS/s – Dual 12-bit DAC
- Audio – Four Synchronous Audio Interface (SAI) – Enhanced Serial Audio Interface (ESAI) – Sony Philips Digital Interface (SPDIF), Rx and Tx – Asynchronous Sample Rate Converter (ASRC)
- Human-Machine Interface (HMI) – GPIO pins with interrupt support, DMA request capability, digital glitch filter. – Hysteresis and configurable pull up/down device on all input pins – Configurable slew rate and drive strength on all output pins
- On-Chip Memory – 512 KB On-chip SRAM with ECC – 1 MB On-chip graphics SRAM (no ECC). This depends on the part selected. Alternate configuration could be 512 KB graphics and 512 KB L2 cache. – 96 KB Boot ROM VF3xxR, VF5xxR, Rev. 8, 01/2018
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6.2.2.1 Main Supply electrical characteristics 17
6.2.7 EMC Radiated Emissions Web Search Procedure
8.5 Recommended Connections for Unused Analog Interfaces... 33
9.2.1.2 Interface to TFT LCD Panels—Pixel
9.2.1.3 Interface to TFT LCD panels—access
9.3.2 Receive and Transmit signal timing specifications 50
9.3.3 Receive and Transmit signal timing specifications
VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 3
9.4.1 Enhanced Serial Audio Interface (ESAI) Timing
9.6.2 MediaLB (MLB) Controller AC Timing Electrical
9.7.3 Fast internal RC oscillator (24 MHz) electrical
9.7.4 Slow internal RC oscillator (128 KHz) electrical
9.7.5 PLL1 and PLL2 (528 MHz System PLL)
9.7.6 PLL3 and PLL7 (480 MHz USB PLL) Electrical
VF3xxR, VF5xxR, Rev. 8, 01/2018
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1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. 1. To determine the orderable part numbers for this device, go to www.nxp.com and search the required part number. The part numbering format is described in the section that follows. Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Part Number Format
The figure below represents the format of part number of this device. Ordering parts VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 5
Figure 1. Part Number Format
2.3 Part Numbers
This table lists the part numbers on the device. Table continues on the next page...
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Part Number Mask VADC Package Description SVF531R3K2CMK4 3N02G YES MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, 364BG SVF532R2K2CMK4 3N02G YES MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, L2 Cache OpenVG GPU, 364BGA SVF532R3K2CMK4 3N02G YES MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, OpenVG GPU, 364BGA SVF311R3N2CKU2 3N02G NO LQFP-EP 176 24*24*1.6 A5-266, 176LQFP-EP SVF312R3N2CKU2 3N02G NO LQFP-EP 176 24*24*1.6 A5-266, OpenVG GPU, 176LQFP-EP SVF321R3N2CKU2 3N02G NO LQFP-EP 176 24*24*1.6 A5-266, M4, 176LQFP-EP SVF322R3N2CKU2 3N02G NO LQFP-EP 176 24*24*1.6 A5-266, M4, OpenVG GPU, 176LQFP SVF331R3N2CKU2 3N02G NO LQFP-EP 176 24*24*1.6 A5-266, M4 Primary, 176LQFP-EP SVF332R3N2CKU2 3N02G NO LQFP-EP 176 24*24*1.6 A5-266, M4 Primary, OpenVG GPU, 176LQFP-EP SVF511R3N2CMK4 3N02G NO MAP 364 17*17*1.5 P0.8 A5-400, 364BGA SVF512R3N2CMK4 3N02G NO MAP 364 17*17*1.5 P0.8 A5-400, OpenVG GPU, 364BGA SVF521R3N2CMK4 3N02G NO MAP 364 17*17*1.5 P0.8 A5-400, M4, 364BGA SVF522R2N2CMK4 3N02G NO MAP 364 17*17*1.5 P0.8 A5-400, M4, L2 Cache, OpenVG GPU, 364BGA SVF522R3N2CMK4 3N02G NO MAP 364 17*17*1.5 P0.8 A5-400, M4, OpenVG GPU, 364BG SVF531R3N2CMK4 3N02G NO MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, 364BG SVF532R2N2CMK4 3N02G NO MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, L2 Cache OpenVG GPU, 364BGA SVF532R3N2CMK4 3N02G NO MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, OpenVG GPU, 364BGA Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V Terminology and guidelines VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 7
3.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered. Terminology and guidelines VF3xxR, VF5xxR, Rev. 8, 01/2018
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3.4.1 Example
This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V
3.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.
3.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation Terminology and guidelines VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 9
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: Terminology and guidelines VF3xxR, VF5xxR, Rev. 8, 01/2018
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150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
3.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Handling ratings
4.1 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 500 V 2 ILAT Latch-up Current at ambient temperature of 85 °C -100 100 mA 1. Determined according to the AEC spec AEC-Q100-002 for HBM 2. Determined according to AEC spec AEC-Q100-011 Handling ratings VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 11
4.2 Thermal handling ratings
- Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 Moisture handling ratings
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.1 Thermal operating requirements
Table 1. Thermal operating requirements
6.1 AC electrical characteristics
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Figure 2. Input signal measurement reference
6.2.1.1 HPREG electrical characteristics
Table 2. HPREG electrical characteristics
- This is peak and not continuous maximum value.
6.2.1.2 LPREG electrical characteristics
Table 3. LPREG electrical characteristics
6.2.1.3 ULPREG electrical characteristics
Table 4. ULPREG electrical characteristics
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6.2.1.4 WBREG electrical characteristics
Table 5. WBREG electrical characteristics
6.2.1.5 External NPN Ballast
allows for collector voltage lower than VDDREG value. See AN4807 at www.nxp.com . no later than VDDREG / VDD33 (3.3V).
Figure 3. External NPN Ballast connections Table 6. BCTRL OUTPUT specification Table 7. Assumptions For calculations Table 8. General guidelines for selection of NPN ballast
42.5 As BCTRL pin can not drive more than
Table continues on the next page...
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Table 8. General guidelines for selection of NPN ballast (continued) V or lower, it is suitable for application.
50 MHz
- By introducing series resistor or diode(s) between the collector and VDDREG
- By connecting the collector to a separate lower-voltage supply
6.2.2.1 Main Supply electrical characteristics
Table 9. LVD_MAIN supply electrical characteristics
6.2.2.2 LVD DIG characteristics
Table 10. LVD DIG electrical specifications [HPREG(RUN MODE) and LPREG(STOP Table 11. LVD DIG electrical specifications [ULPREG(STANDBY
6.2.3.1 LDO_1P1
Table 12. LDO_1P1 parameters
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For additional information, see the device reference manual.
6.2.3.2 LDO_2P5
Table 13. LDO_2P5 parameters For additional information, see the reference manual.
6.2.3.3 LDO_3P0
Table 14. LDO_3P0 parameters
to set these values before using USB.
6.2.4 Power consumption operating behaviors
Table 15. Power consumption operating behaviors 24MHz operation, PLL Bypass.
- The Typ numbers represent the average value taken from a matrix lot of parts across normal process variation at ambient
- The Max numbers represent the single worst case value taken from a matrix lot of parts across normal process variation at
- 24MHz operation, PLL Bypass
- 32 kHz /128 kHz operation, PLL Off
- Lowest power mode with all power retained, RAM retention and LVD protection.
- All supplies OFF, SRTC, 32kXOSC ON, tampers and monitors ON. 128k IRC optionally ON.
6.2.5 USB PHY current consumption
6.2.5.1 Power Down Mode
Everything powered down, including the VBUS valid detectors, typ condition. Table 16. USB PHY Current Consumption in Normal Mode
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USB-specific level shifters.
6.2.6 EMC radiated emissions operating behaviors
Table 17. EMC radiated emissions operating behaviors
150 KHz –
50 MHz –
150 MHz
150 MHz –
500 MHz
- Measurements were made per IEC 61967-2 while the device was running basic application code.
- Measurements were performed on the BGA364 version of the device
- The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from
among the measured orientations in each frequency range.
- IEC Level Maximums: N ≤ 12dBmV, M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV
6.2.7 EMC Radiated Emissions Web Search Procedure boilerplate
- Perform a keyword search for “EMC design.”
6.2.8 Capacitance attributes
Table 18. Capacitance attributes
7.1 GPIO parameters
Table 19. GPIO DC operating conditions
- This is internally controlled.
Table 20. GPIO DC Electrical characteristics Table continues on the next page...
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Table 20. GPIO DC Electrical characteristics (continued)
- For details about Software MUX Pad Control Register DSE bit, see IOMUX Controller chapter of the device reference
- To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current
apply when hysteresis is enabled.
- Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
85 °C. These values are for digital IO buffer cells. Table 21. GPIO AC Electrical Characteristics (3.3V power mode) Table continues on the next page...
Table 21. GPIO AC Electrical Characteristics (3.3V power mode) (continued)
- The drive strengths are controlled by the DSE bit of the Software MUX Pad Control Register. For details, see IOMUX
Controller chapter of the device reference manual.
7.1.1 Output Buffer Impedance measurement
Table 22. Output Buffer Average Impedance (3.3V power mode)
- The drive strengths are controlled by the DSE bit of the Software MUX Pad Control Register. For details, see IOMUX
Controller chapter of the device reference manual.
7.2 DDR parameters
Table 23. DDR operating conditions
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Table 24. LPDDR2 mode DC Electrical characteristics
0.26 Note1 V
- The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well
as the limitations for overshoot and undershoot. Table 25. DDR3 mode DC Electrical characteristics Table continues on the next page...
Table 25. DDR3 mode DC Electrical characteristics (continued)
0.2 Note1 V
- The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well
as the limitations for overshoot and undershoot.
- Vtt is expected to track ovdd/2.
Table 26. LPDDR2 mode AC Electrical characteristics Table continues on the next page...
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Table 26. LPDDR2 mode AC Electrical characteristics (continued)
0.3 V*ns
- Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac)-Vil(ac).
- The typical value of Vix(ac) is expected to be about 0.5*ovdd, and Vix(ac) is expected to track variation of ovdd. Vix(ac)
indicates the voltage at which differential input signal must cross. Table 27. DDR3 mode AC Electrical characteristics
0.5 V*ns
Table continues on the next page...
Table 27. DDR3 mode AC Electrical characteristics (continued)
- Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac)-Vil(ac).
- The typical value of Vix(ac) is expected to be about 0.5*ovdd, and Vix(ac) is expected to track variation of ovdd. Vix(ac)
indicates the voltage at which differential input signal must cross.
8.1 Power sequencing
Table 28. Power sequencing
1 VDD33_LDOIN,VDDREG and
- Power sequencing of USB0_VBUS is independent of any other power supply.
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- Power sequencing of USB1_VBUS is independent of any other power supply. NOTE NA stands for no sequencing needs, for example, the supply can come in any order. NOTE All supplies grouped together e.g. 1,2, others. These have no power sequencing restriction in between them. NOTE If none of the SDRAMC pins are connected on the board, the SDRAMC supply could be left floating. NOTE At power up, 1.2V supply will follow 3.3V supply. At power down, it should be checked that 1.2V falls before 3.3V. NOTE The standby current on USBx_VBUS is 300 - 500 uA. This is well below the 2.5 mA limit set by the USB 2.0 specification. This supply will be ON for applications that need to monitor the USB bus during standby. This supply can be turned-off during standby in applications that cannot tolerate the standby current and do not monitor the USB bus.
8.2 Power supply
Power supplies and sequencing VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 29
Figure 4. Power supply
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8.3 Absolute maximum ratings
These are the values above which device can get damaged. Table 29. Absolute maximum ratings
8.4 Recommended operating conditions
Table 30. Recommended operating conditions Table continues on the next page...
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Table 30. Recommended operating conditions (continued)
- For customer applications, this is governed by ballast output which is controlled by the device and appropriate voltage
8.5 Recommended Connections for Unused Analog Interfaces
- Connect all unused supplies to their respective voltage. To
enable clock gate to the module.
- Keep all unused supplies floating.
pins are floating. Keep unused output signals floating. Table continues on the next page...
Table 31. 12-bit ADC Operating Conditions Table continues on the next page...
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Table 31. 12-bit ADC Operating Conditions (continued)
- Typical values assume VDDAD = 3.3 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production. Figure 5. 12-bit ADC Input Impedance Equivalency Diagram
Table 32. 12-bit ADC Characteristics (V REFH = VDDAD, VREFL = VSSAD) Table continues on the next page...
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Table 32. 12-bit ADC Characteristics (V REFH = VDDAD, VREFL = VSSAD) (continued)
- All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
- Typical values assume VDDAD = 3.3 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- 1 LSB = (VREFH - VREFL)/2N
Figure 6. Minimum Sample Time Vs Ras (Cas = 2pF) Figure 7. Minimum Sample Time Vs Ras (Cas = 5pF)
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Figure 8. Minimum Sample Time Vs Ras (Cas = 10pF) Table 33. 12-bit DAC operating requirements
- User will need to set up DACx_STATCTRL [DACRFS]=1 to select the valid VREFH_ADC reference. When
- A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
Table 34. 12-bit DAC operating behaviors Table continues on the next page...
Table 34. 12-bit DAC operating behaviors (continued)
- The INL is measured for 0+100mV to VDACR−100 mV
- The DNL is measured for 0+100mV to VDACR−100 mV
- Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV
- VDDA = 3.3 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
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Figure 9. INL error vs. digital code
Figure 10. DNL error vs. digital code
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Figure 11. Offset at half scale vs. temperature
9.1.3 VideoADC Specifications
Table 35. VideoADC Specifications capacitance cannot be too large. Table continues on the next page...
Table 35. VideoADC Specifications (continued) Figure 12. VideoADC supply scheme Figure 13. VideoADC supply decoupling
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power domains. Use linear voltage regulators instead.
9.2.1.1 Interface to TFT panels (DCU0/1)
- PCLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, PCLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type.
- HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
- VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
- DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off.
Figure 14. TFT LCD interface timing overview1
- In the figure, LD[23:0]” signal is “line data,” an aggregation of the DCU’s RGB signals—R[0:7], G[0:7] and B[0:7].
9.2.1.2 Interface to TFT LCD Panels—Pixel Level Timings
Table 36. LCD interface timing parameters—horizontal and vertical
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Figure 15. Horizontal sync timing Figure 16. Vertical sync pulse
9.2.1.3 Interface to TFT LCD panels—access level
This section provides the access level timing parameters of the LCD interface. Table 37. LCD Interface Timing Parameters 1, 2, 3—Access Level
- The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data on -ve
- Intra bit skew is less than 2 ns
Figure 17. LCD Interface Timing Parameters—Access Level
9.2.2 Video Input Unit timing
This section provides the timing parameters of the Video Input Unit (VIU) interface.
- The platform bus clock must be 2.5x pixel clock
- If the VIU3 does 2x horizontal upscaling, the ratio must be 3x DCU Switching Specifications VF3xxR, VF5xxR, Rev. 8, 01/2018
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Figure 18. VIU Timing Parameters Table 38. VIU Timing Parameters
9.2.3 LCD driver electrical characteristics
This section provides LCD driver electrical specification at VDD33 = 3.3 V ± 10%. Table 39. LCD driver specifications
0 VDD33 +
- With PWR=10, BSTEN=0, and BSTAO=0
9.3.1 Ethernet Switching Specifications
pad slew rate setting of 11 and a load of 50 pF2.
9.3.2 Receive and Transmit signal timing specifications
range of transceiver devices. Table 40. Receive signal timing for RMII interfaces Figure 19. RMII receive signal timing diagram
- These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11).
edge rise and fall times, thus reducing EMI.
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Figure 20. RMII transmit signal timing diagram internally generated RXCLK and TXCLK clocks. Figure 21. MII receive signal timing diagram Table 41. Receive signal timing for MII interfaces
9.3.3 Receive and Transmit signal timing specifications for MII
range of transceiver devices.
Figure 22. MII receive signal timing diagram Table 42. Receive signal timing for MII interfaces and operates at 50 MHz reference clock. Figure 23. MII transmit signal timing diagram Table 43. Transmit signal timing for MII interfaces
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9.4.1 Enhanced Serial Audio Interface (ESAI) Timing Parameters
own clock generator. The following table shows the interface timing values. Table 44. Enhanced Serial Audio Interface (ESAI) Timing
2 Clock high period:
- master
- slave (2 × Tc − 9.0) (2 × Tc) ns
3 Clock low period:
- master
- slave 6 (2 × Tc − 9.0) 15 (2 × Tc) ns
4 FSR Input and Data Input setup time before SCKR
5 FSR Input and Data Input hold time after SCKR
6 SCKT rising edge to FST out and Data out valid —
7 SCKT rising edge to FST out and Data out hold —
8 FST input setup time before SCKT falling edge —
9 FST input hold time after SCKT falling edge —
10 HCKR/HCKT clock cycle — 15
- SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) =
- For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
Figure 24. ESAI Transmitter Timing Figure 25. ESAI Receiver Timing
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9.4.2 SPDIF Timing Parameters
modulating Tx clock (STCLK) for SPDIF in Tx mode. Table 45. SPDIF Timing Parameters
- Skew
- Transition rising
- Transition falling
- 1.5
- 24.2
- 31.3 ns SPDIFOUT1 output (Load = 30pf) - Skew 1.5 ns
- Transition rising
- Transition falling Refer Table 21 Modulating Rx clock (SRCK) period srckp 40 ns SRCK high period srckph 16 ns SRCK low period srckpl 16 ns Modulating Tx clock (STCLK) period stclkp 40 ns STCLK high period stclkph 16 ns STCLK low period stclkpl 16 ns
Figure 26. SRCK Timing Diagram
Figure 27. STCLK Timing Diagram
9.4.3 SAI/I2S Switching Specifications
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below. Table 46. Master Mode SAI Timing
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9.5.1 QuadSPI timing
- All data is based on a negative edge data launch from the device and a negative edge data capture, as shown in the timing diagrams in this section. This corresponds to the N/1 sample point as shown in the reference manual QSPI section "Internal Sampling of Serial Flash Input Data."
- Measurements are with a load of 35 pF on output pins. I/P Slew : 1ns
- Timings assume a setting of 0x0000_000x for QSPI_SMPR register (see the reference manual for details). SDR mode Tck Tcss Tcsh Tis Tih SCK CS Data in
Figure 30. QuadSPI Input/Read timing (SDR mode) Table 48. QuadSPI Input/Read timing (SDR mode)
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Figure 31. QuadSPI Output/Write timing (SDR mode) Table 49. QuadSPI Output/Write timing (SDR mode)
- Tcss and Tcsh are set by QuadSPI_FLSCH register, the minimum values of 3 shown are the register default values, refer to Reference Manual for further details.
- The timing in the datasheet is based on default values for the QuadSPI-SMPR register and is the recommended setting for highest SCK frequency in SDR mode.
- A negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad.
- Frequency calculator guideline (Max read frequency): Tck > (Flash access time)max + (Tis)max
- A negative input hold time has no bearing on the maximum achievable operating frequency. DDR Mode Memory interfaces VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 59
Figure 32. QuadSPI Input/Read timing (DDR mode)
- The numbers are for a setting of 0x1 in register QuadSPI_SMPR[DDRSMP]
- Read frequency calculations should be: Tck/2 > (flash access time) + Setup (Tis) - (QuadSPI_SMPR[DDRSMP])x Tck/4
- Frequency calculator guideline (Max read frequency): Tck/2 > (Flash access time)max + (Tis)max - (QuadSPI_SMPR[DDRSMP]) x Tck/4
- Hold timing: flash_access (min) + flash_data_valid (min) > Tck/2 + HOLD(Tih) + (QuadSPI_SMPR[DDRSMP])Tck/4
Table 50. QuadSPI Input/Read timing (DDR mode)
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Figure 33. QuadSPI Output/Write timing (DDR mode) Table 51. QuadSPI Output/Write timing (DDR mode)
9.5.2 NAND flash controller specifications
memory devices. This section describes the timing parameters of the NFC.
- T H is the flash clock high time and
- T L is flash clock low time, which are defined as: TNFC = TH + TL NOTE See the CCM section of the product reference manual for further details on setting up the NFC clocks (CCM_CSCDR2[NFC_FRAC_DIV_EN + NFC_FRAC_DIV] and CCM_CSCDR3[NFC_PRE_DIV]). Memory interfaces VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 61
Table 52. NFC specifications Figure 34. Command latch cycle timing
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Figure 38. Read data latch cycle timing in Fast mode and EDO mode
9.5.3 FlexBus timing specifications
Table 53. FlexBus timing specifications
- Freq = 1000/(11+ access time of external memory+ trace delay for clk and data)
- Freq = 1000/(17+access time of external memory)
- These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11).
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9.5.4.1 DDR3 Timing Parameters
Figure 41. DDR3 Command and Address Timing Parameters
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CKE pin has a external weak pull down requirement. Table 54. DDR3 Timing Parameter All measurements are in reference to Vref level. resistor from outputs to VDD_REF.
9.5.4.2 DDR3 Read Cycle
Figure 42. DDR3 Read Cycle Table 55. DDR3 Read Cycle All measurements are in reference to Vref level.
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9.5.4.3 DDR3 Write cycle
Figure 43. DDR3 Write cycle Table 56. DDR3 Write cycle All measurements are in reference to Vref level. resistor from outputs to VDD_REF.
9.5.4.4 LPDDR2 Timing Parameter
Figure 44. LPDDR2 Command and Address timing parameter CKE pin has a external weak pull down requirement. Table 57. LPDDR2 Timing Parameter All measurements are in reference to Vref level.
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resistor from outputs to VDD_REF.
9.5.4.5 LPDDR2 Read Cycle
Figure 45. LPDDR2 Read cycle Table 58. LPDDR2 Read Cycle All measurements are in reference to Vref level.
9.5.4.6 LPDDR2 Write Cycle
Figure 46. LPDDR3 Write Cycle Table 59. LPDDR2 Write Cycle All measurements are in reference to Vref level. resistor from outputs to VDD_REF.
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9.6.1 MediaLB (MLB) DC Characteristics
The section lists the MediaLB 3-pin interface electrical characteristics. Table 60. MediaLB 3-Pin Interface Electrical DC Specifications
- Higher VIH thresholds can be used; however, the risks associated with less noise margin in the system must be evaluated
and assumed by the customer.
9.6.2 MediaLB (MLB) Controller AC Timing Electrical Specifications
This section describes the timing electrical information of the MediaLB module.
Figure 47. MediaLB 3-PinTiming as listed below; unless otherwise noted. Table 61. MLB 256/512 Fs Timing Parameters
- MLBCLK low/high time includes the pluse width variation.
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- The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final
maximum load capacitance listed. Table 62. MLB 1024 Fs Timing Parameters
- The controller can shut off MLBCLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLBCLK.
- MLBCLK low/high time includes the pluse width variation.
- The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final
maximum load capacitance listed.
9.6.3 DSPI timing specifications
Table 63. DSPI timing Table continues on the next page...
Table 63. DSPI timing (continued) Figure 48. DSPI classic SPI timing master, CPHA=0
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Figure 51. DSPI classic SPI timing slave, CPHA=1
9.6.4 I2C timing
Table 64. I2C input timing specifications — SCL and SDA 1
1 Start condition hold time 2 — PER_CLK
2 Clock low time 8 — PER_CLK
5 Clock high time 4 — PER_CLK
7 Start condition setup time (for repeated start condition only) 2 — PER_CLK
8 Stop condition setup time 2 — PER_CLKCyc
- I2C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than 1
- PER_CLK is the IPG Clock which drives the I2C BIU and module clock inputs. Typically this is 66 MHz. See the Clocking
Overview chapter in the device reference manual for more details. Table 65. I2C output timing specifications — SCL and SDA 1, 2, 3, 4
1 Start condition hold
Table continues on the next page...
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Table 65. I2C output timing specifications — SCL and SDA 1, 2, 3, 4 (continued)
2 Clock low time 10 — PER_CLK Cycle
3 Bus free time between
4 Data hold time 7 — PER_CLK Cycle
5 Clock high time 10 — PER_CLK Cycle
6 Data setup time 2 — PER_CLK Cycle
7 Start condition setup
8 Stop condition setup
- All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
- Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
- Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speedsand may
- Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output
timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register.
- PER_CLK is the IPG Clock which drives the I2C BIU and module clock inputs. Typically this is 66 MHz. See the Clocking
Overview chapter in the device reference manual for more details. Figure 52. I2C input/output timing
9.6.5 SDHC specifications
Table 66. SDHC switching specifications Figure 53. SDHC timing
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9.6.6 USB PHY specifications
This section describes the USB-OTG PHY and the USB Host port PHY parameters.
- USB ENGINEERING CHANGE NOTICE
- Title: 5V Short Circuit Withstand Requirement Change
- Applies to: Universal Serial Bus Specification, Revision 2.0
- Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
- USB ENGINEERING CHANGE NOTICE
- Title: Pull-up/Pull-down resistors
- Applies to: Universal Serial Bus Specification, Revision 2.0
- USB ENGINEERING CHANGE NOTICE
- Title: Suspend Current Limit Changes
- Applies to: Universal Serial Bus Specification, Revision 2.0
- On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
- Revision 2.0 plus errata and ecn June 4, 2010
- Battery Charging Specification (available from USB-IF)
- Revision 1.2, December 7, 2010 Clocks and PLL Specifications 9.7.1 24 MHz Oscillator Specifications The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight forward biased-inverter implementation is used. The crystal must be rated for a drive level of 250 μW or higher. An ESR (equivalent series resistance) of 80 Ω or less is recommended to achieve a gain margin of 5.
Table 67. 24MHz external oscillator electrical characteristics Table continues on the next page...
Table 67. 24MHz external oscillator electrical characteristics (continued)
- VDD =1.1 V ± 10%, TA = -40 to +85 °C, unless otherwise specified.
transitions to the back up battery when VDDIO is lost. the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell.
- Average Discharge Voltage is 2.5 V
- Maximum Charge Current is 0.6 mA
Table 68. OSC32K Main Characteristics crystal selected. 32.0 K would work as well.
32.768 KHz
The 4 μA is the consumption of the oscillator alone (OSC32k). Table continues on the next page...
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Table 68. OSC32K Main Characteristics (continued) vdd_rtc when the ring oscillator is not running. ability to start up and maintain oscillations. Cload Usually crystals can be purchased tuned for different Cloads. with a higher value will decrease the oscillating margin.
9.7.3 Fast internal RC oscillator (24 MHz) electrical characteristics
clock at the power-up of the device. Table 69. Fast internal oscillator electrical characteristics
- VDD = 1.2 V , TA = -40 to +85 °C, unless otherwise specified.
9.7.4 Slow internal RC oscillator (128 KHz) electrical characteristics
reference clock for the RTC module. Table 70. Slow internal RC oscillator electrical characteristics
- VDD = 1.2 V , TA = -40 to +85 °C, unless otherwise specified.
9.7.5 PLL1 and PLL2 (528 MHz System PLL) Electrical Parameters
Table 71. PLL1 and PLL2 Electrical Parameters
9.7.6 PLL3 and PLL7 (480 MHz USB PLL) Electrical Parameters
Table 72. PLL3 and PLL7 Electrical Parameters
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9.7.7 PLL5 (Ethernet PLL) Electrical Parameters
Table 73. PLL5 Electrical Parameters
- Jitter numbers are measured at divided PLL clock because high frequency cannot be brought-out IO pad.
9.7.8 PLL4 (Audio PLL) Electrical Parameters
Table 74. PLL4 Electrical Parameters
- Jitter numbers are measured at divided PLL clock because high frequency cannot be brought-out on IO pad.
9.7.9 PLL6 (Video PLL) Electrical Parameters
Table 75. PLL6 Electrical Parameters
- Jitter numbers are measured at divided PLL clock because high frequency cannot be brought-out on IO pad & at use case
9.8.1 JTAG electricals
Table 76. JTAG limited voltage range electricals
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug ns ns ns J4 TCLK rise and fall times Refer Table 21 ns J5 Boundary scan input data setup time to TCLK rise 8 — ns J6 Boundary scan input data hold time after TCLK rise 1.3 — ns J7 TCLK low to boundary scan output data valid — 17 ns J8 TCLK low to boundary scan output high-Z — 17 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.3 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns NOTE Input transition (1ns), output load (25 pf) and SRE (000), DSE (111), FSEL(011). J3 J3 J4 J4 TCLK (input)
Figure 54. Test clock input timing
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9.8.2 Debug trace timing specifications
Table 77. Debug trace operating behaviors Figure 57. TRACE_CLKOUT specifications Figure 58. Trace data specifications
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10.1 Thermal attributes
This table shows the thermal attributes for the 176 LQFP package. Board type Symbol Description 176 LQFP Unit Notes Single-layer (1s) RθJA Thermal resistance, junction to ambient (natural convection) 50 °C/W 1, 2 Four-layer (2s2p) RθJA Thermal resistance, junction to ambient (natural convection) 32 °C/W 1,3 Single-layer (1s) RθJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 40 °C/W 1, 3 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 25 °C/W 1, 3 — RθJB Thermal resistance, junction to board 21 °C/W 4 — RθJCtop Thermal resistance, junction to case top 12 °C/W 5 — ΨJT Thermal characterization parameter, junction to package top (natural convection) 3 °C/W 6 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance 2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal 3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. This table shows the thermal attributes for the 364 MAPBGA package. Thermal attributes VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 89
Board type Symbol Description 364 MAPBGA Unit Notes Single-layer (1s) RθJA Thermal resistance, junction to ambient (natural convection) 45 °C/W 1, 2 Four-layer (2s2p) RθJA Thermal resistance, junction to ambient (natural convection) 28 °C/W 1, 3 Single-layer (1s) RθJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 37 °C/W 1,3 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 24 °C/W 1,3 — RθJB Thermal resistance, junction to board 17 °C/W 4 — RθJC Thermal resistance, junction to case 10 °C/W 5 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 2 °C/W 6 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Dimensions
11.1 Obtaining package dimensions
Package dimensions are provided in package drawing. To find a package drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number: Dimensions VF3xxR, VF5xxR, Rev. 8, 01/2018
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364 MAPBGA 98ASA00418D
12.1 Pinouts
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The IOMUX Controller Module is responsible for selecting which ALT functionality is available on each pin. 364 MAP BGA 176 LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort Y2 — ADC0SE8N/ A ADC0_SE8 W2 — ADC0SE9 ADC0_SE9 W3 — ADC1SE8 ADC1_SE8 Y3 — ADC1SE9 ADC1_SE9 W1 34 VREFH_ADC VREFH_ADC U3 33 VREFL_ADC VREFL_ADC V1 31 VDDA33_ ADC VDDA33_ ADC V2 32 VSSA33_ ADC VSSA33_ ADC U1 29 DACO0 DACO0 U2 30 DACO1 DACO1 Y4 35 VADCSE0 VADCSE0 U4 37 VADCSE1 VADCSE1 W4 — VADCSE2 VADCSE2 V5 — VADCSE3 VADCSE3 V3 40 VDDA33_ AFE VDDA33_ AFE V4 39 VSSA33_AFE VSSA33_AFE T5 36 VDD12_AFE VDD12_AFE R5 38 VSS12_AFE VSS12_AFE U5 41 VADC_AFE_ BANDGAP VADC_AFE_ BANDGAP Y13 73 EXTAL EXTAL W13 72 XTAL XTAL Y12 70 EXTAL32 EXTAL32 Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 91
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort W12 71 XTAL32 XTAL32 T4 28 RESETB/ RESET_OUT RESETB/ RESET_OUT RESETB/ RESET_OUT N5 19 PTA6 PTA6 RMII_ CLKOUT RMII_CLKIN/ MII0_TXCLK DCU1_ TCON11 DCU1_R2 T3 27 TEST TEST T1 23 Ext_POR TEST2 V12 69 DECAP_ V11_LDO_ OUT DECAP_ V11_LDO_ OUT T11 65 DECAP_ V25_LDO_ OUT DECAP_ V25_LDO_ OUT T2 26 BCTRL BCTRL P5 24 VDDREG VDDREG T12 68 VDD33_ LDOIN VDD33_ LDOIN V11 67 VSS VSS U11 66 VSS_KEL0 VSS_KEL0 W14 — LVDS0P LVDS0P Y14 — LVDS0N LVDS0N K4 3 JTCLK/ SWCLK JTCLK/ SWCLK PTA8 JTCLK/ SWCLK DCU0_R0 MLBCLK K2 4 JTDI JTDI PTA9 JTDI RMII_ CLKOUT RMII_CLKIN/ MII0_TXCLK DCU0_R1 WDOG_b K1 5 JTDO JTDO/ TRACESWO PTA10 JTDO EXT_AUDIO_ MCLK DCU0_G0 ENET_TS_ CLKIN MLBSIGNAL L1 6 JTMS/ SWDIO JTMS/ SWDIO PTA11 JTMS/ SWDIO DCU0_G1 MLBDATA L3 7 PTA12 PTA12 TRACECKEXT_AUDIO_ MCLK VIU_DATA13I2C0_SCL Y5 43 PTA16 PTA16 TRACED0USB0_ VBUS_EN ADC1_SE0LCD29 SAI2_TX_ BCLK VIU_DATA14I2C0_SDA Y6 44 PTA17 PTA17 TRACED1USB0_ VBUS_OC ADC1_SE1LCD30 USB0_SOF_ PULSE VIU_DATA15I2C1_SCL V6 46 PTA18 PTA18 TRACED2ADC0_SE0FTM1_QD_ PHA LCD31 SAI2_TX_ DATA VIU_DATA16I2C1_SDA U6 47 PTA19 PTA19 TRACED3ADC0_SE1FTM1_QD_ PHB LCD32 SAI2_TX_ SYNC VIU_DATA17QSPI1_A_ SCK B18 143 PTA20 PTA20 TRACED4 LCD33 SCI3_TX DCU1_ HSYNC/ DCU1_ TCON1 D18 145 PTA21 PTA21/ MII0_RXCLK TRACED5 SAI2_RX_ BCLK SCI3_RX DCU1_ VSYNC/ DCU1_ TCON2 Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018
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Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort E17 147 PTA22 PTA22 TRACED6 SAI2_RX_ DATA I2C2_SCLDCU1_TAG/ DCU1_ TCON0 C17 148 PTA23 PTA23 TRACED7 SAI2_RX_ SYNC I2C2_SDADCU1_DE/ DCU1_ TCON3 R16 — PTA24 PTA24 TRACED8USB1_ VBUS_EN SDHC1_CLKDCU1_ TCON4 R17 — PTA25 PTA25 TRACED9USB1_ VBUS_OC SDHC1_CMDDCU1_ TCON5 R19 — PTA26 PTA26 TRACED10SAI3_TX_ BCLK SDHC1_ DAT0 DCU1_ TCON6 R20 — PTA27 PTA27 TRACED11SAI3_RX_ BCLK SDHC1_ DAT1 DCU1_ TCON7 P20 — PTA28 PTA28 TRACED12SAI3_RX_ DATA ENET1_ 1588_TMR0 SCI4_TX SDHC1_ DAT2 DCU1_ TCON8 P18 — PTA29 PTA29 TRACED13SAI3_TX_ DATA ENET1_ 1588_TMR1 SCI4_RX SDHC1_ DAT3 DCU1_ TCON9 P17 — PTA30 PTA30 TRACED14SAI3_RX_ SYNC ENET1_ 1588_TMR2 SCI4_RTSI2C3_SCL SCI3_TX P16 — PTA31 PTA31 TRACED15SAI3_TX_ SYNC ENET1_ 1588_TMR3 SCI4_CTSI2C3_SDA SCI3_RX T6 49 PTB0 PTB0 FTM0_CH0ADC0_SE2TRACECTLLCD34 SAI2_RX_ BCLK VIU_DATA18QSPI1_A_ CS0 T7 50 PTB1 RCON30 PTB1 FTM0_CH1ADC0_SE3RCON30 LCD35 SAI2_RX_ DATA VIU_DATA19QSPI1_A_ DATA3 V7 51 PTB2 RCON31 PTB2 FTM0_CH2ADC1_SE2RCON31 LCD36 SAI2_RX_ SYNC VIU_DATA20QSPI1_A_ DATA2 W7 53 PTB3 PTB3 FTM0_CH3ADC1_SE3EXTRIG LCD37 VIU_DATA21QSPI1_A_ DATA1 Y7 54 PTB4 PTB4 FTM0_CH4SCI1_TX ADC0_SE4LCD38 VIU_FID VIU_DATA22QSPI1_A_ DATA0 Y8 55 PTB5 PTB5 FTM0_CH5SCI1_RX ADC1_SE4LCD39 VIU_DE VIU_DATA23QSPI1_A_ DQS W8 56 PTB6 PTB6 FTM0_CH6SCI1_RTSQSPI0_A_ CS1 LCD40 FB_CLKOUTVIU_HSYNCSCI2_TX D13 166 PTB7 PTB7 FTM0_CH7SCI1_CTSQSPI0_B_ CS1 LCD41 VIU_VSYNCSCI2_RX J16 121 PTB8 PTB8 FTM1CH0 FTM1_QD_ PHA VIU_DE DCU1_R6 J19 123 PTB9 PTB9 FTM1CH1 FTM1_QD_ PHB DCU1_R7 B15 159 PTB10 PTB10 SCI0_TX DCU0_ TCON4 VIU_DE CKO1 ENET_TS_ CLKIN D14 164 PTB11 PTB11 SCI0_RX DCU0_ TCON5 SNVS_ ALARM_ OUT_B CKO2 ENET0_ 1588_TMR0 Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 93
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort E13 165 PTB12 NMI PTB12 SCI0_RTS SPI0_PCS5DCU0_ TCON6 FB_AD1 NMI ENET0_ 1588_TMR1 D15 156 PTB13 PTB13 SCI0_CTS SPI0_PCS4DCU0_ TCON7 FB_AD0 TRACECTL B14 162 PTB14 PTB14 CAN0_RXI2C0_SCL DCU0_ TCON8 DCU1_PCLK A14 161 PTB15 PTB15 CAN0_TX I2C0_SDA DCU0_ TCON9 VIU_PIX_ CLK C14 163 PTB16 PTB16 CAN1_RXI2C1_SCL DCU0_ TCON10 A15 160 PTB17 PTB17 CAN1_TX I2C1_SDA DCU0_ TCON11 B12 171 PTB18 PTB18 SPI0_PCS1EXT_AUDIO_ MCLK VIU_DATA9CCM_OBS0 C13 167 PTB19 PTB19 SPI0_PCS0 VIU_DATA10CCM_OBS1 A13 169 PTB20 PTB20 SPI0_SIN LCD42 VIU_DATA11CCM_OBS2 E12 173 PTB21 PTB21 SPI0_SOUT LCD43 VIU_DATA12DCU1_PCLK D12 172 PTB22 PTB22 SPI0_SCK VIU_FID V10 61 USB0_GND USB0_GND T10 63 USB0_DP USB0_DP T9 62 USB0_DM USB0_DM W11 60 USB0_VBUS USB0_VBUS Y10 59 USB_DCAP USB_DCAP Y11 64 USB0_ VBUS_ DETECT USB0_ VBUS_ DETECT Y9 — USB1_GND USB1_GND W9 — USB1_DP USB1_DP V9 — USB1_DM USB1_DM W10 — USB1_VBUS USB1_VBUS U9 — USB1_ VBUS_ DETECT USB1_ VBUS_ DETECT L4 8 PTC0 PTC0 RMII0_MDC/ MII0_MDC FTM1CH0SPI0_PCS3ESAI_SCKTSDHC0_CLKVIU_DATA0RCON18 L5 9 PTC1 PTC1 RMII0_MDIO/ MII0_MDIO FTM1CH1SPI0_PCS2ESAI_FSTSDHC0_CMDVIU_DATA1RCON19 M5 11 PTC2 PTC2 RMII0_CRS_ DV SCI1_TX ESAI_SDO0SDHC0_ DAT0 VIU_DATA2RCON20 M3 12 PTC3 PTC3 RMII0_RXD1/ MII0_RXD[1] SCI1_RX ESAI_SDO1SDHC0_ DAT1 VIU_DATA3DCU0_R0 L2 14 PTC4 PTC4 RMII0_RXD0/ MII0_RXD[0] SCI1_RTSSPI1_PCS1ESAI_SDO2/ ESAI_SDI3 SDHC0_ DAT2 VIU_DATA4DCU0_R1 M1 15 PTC5 PTC5 RMII0_RXER/ MII0_RXER SCI1_CTSSPI1_PCS0ESAI_SDO3/ ESAI_SDI2 SDHC0_ DAT3 VIU_DATA5DCU0_G0 Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018
94 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort N1 16 PTC6 PTC6 RMII0_TXD1/ MII0_TXD[1] SPI1_SIN ESAI_SDO5/ ESAI_SDI0 SDHC0_WPVIU_DATA6DCU0_G1 N2 17 PTC7 PTC7 RMII0_TXD0/ MII0_TXD[0] SPI1_SOUTESAI_SDO4/ ESAI_SDI1 VIU_DATA7DCU0_B0 N4 18 PTC8 PTC8 RMII0_TXEN/ MII0_TXEN SPI1_SCK VIU_DATA8DCU0_B1 T15 — PTC9 PTC9 RMII1_MDC ESAI_SCKT MLBCLK U15 — PTC10 PTC10 RMII1_MDIO ESAI_FST MLBSIGNAL P4 — PTC11 PTC11 RMII1_CRS_ DV ESAI_SDO0 MLBDATA P3 — PTC12 PTC12 RMII1_RXD1 ESAI_SDO1 SAI2_TX_ BCLK P1 — PTC13 PTC13 RMII1_RXD0 ESAI_SDO2/ ESAI_SDI3 SAI2_RX_ BCLK R1 — PTC14 PTC14 RMII1_RXER ESAI_SDO3/ ESAI_SDI2 SCI5_TX SAI2_RX_ DATA ADC0_SE6 P2 — PTC15 PTC15 RMII1_TXD1 ESAI_SDO5/ ESAI_SDI0 SCI5_RX SAI2_TX_ DATA ADC0_SE7 R3 — PTC16 PTC16 RMII1_TXD0 ESAI_SDO4/ ESAI_SDI1 SCI5_RTSSAI2_RX_ SYNC ADC1_SE6 R4 — PTC17 PTC17 RMII1_TXEN ADC1_SE7SCI5_CTSSAI2_TX_ SYNC USB1_SOF_ PULSE B10 — DDR_A[15] DDR_A15 D9 — DDR_A[14] DDR_A14 A10 — DDR_A[13] DDR_A13 C10 — DDR_A[12] DDR_A12 D10 — DDR_A[11] DDR_A11 D7 — DDR_A[10] DDR_A10 B9 — DDR_A[9] DDR_A9 A11 — DDR_A[8] DDR_A8 A7 — DDR_A[7] DDR_A7 A9 — DDR_A[6] DDR_A6 B6 — DDR_A[5] DDR_A5 A6 — DDR_A[4] DDR_A4 B7 — DDR_A[3] DDR_A3 A8 — DDR_A[2] DDR_A2 C11 — DDR_A[1] DDR_A1 C7 — DDR_A[0] DDR_A0 D8 — DDR_BA[2] DDR_BA2 C9 — DDR_BA[1] DDR_BA1 C8 — DDR_BA[0] DDR_BA0 A5 — DDR_CKE[0] DDR_CKE0 Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 95
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort A2 — DDR_CLK[0] DDR_CLK0 B2 — DDR_CLK_ b[0] DDR_CLK_ C5 — DDR_CS_ b[0] DDR_CS_b0 D2 — DDR_D[15] DDR_D15 H2 — DDR_D[14] DDR_D14 C1 — DDR_D[13] DDR_D13 G1 — DDR_D[12] DDR_D12 E2 — DDR_D[11] DDR_D11 H1 — DDR_D[10] DDR_D10 D1 — DDR_D[9] DDR_D9 J1 — DDR_D[8] DDR_D8 G3 — DDR_D[7] DDR_D7 C3 — DDR_D[6] DDR_D6 J3 — DDR_D[5] DDR_D5 F3 — DDR_D[4] DDR_D4 G4 — DDR_D[3] DDR_D3 D4 — DDR_D[2] DDR_D2 H3 — DDR_D[1] DDR_D1 F4 — DDR_D[0] DDR_D0 G2 — DDR_DQM[1] DDR_DQM1 J4 — DDR_DQM[0] DDR_DQM0 E1 — DDR_DQS[1] DDR_DQS1 D3 — DDR_DQS[0] DDR_DQS0 F1 — DDR_DQS_ b[1] DDR_DQS_ E3 — DDR_DQS_ b[0] DDR_DQS_ C4 — DDR_ODT[0] DDR_ODT0 B1 — DDR_ODT[1] DDR_ODT1 G5 — DDR_VREF DDR_VREF A3 — DDR_ZQ DDR_ZQ D6 — DDR_RESET DDR_RESET J20 — PTD31 PTD31 FB_AD31 NF_IO15 FTM3_CH0SPI2_PCS1 H20 — PTD30 PTD30 FB_AD30 NF_IO14 FTM3_CH1SPI2_PCS0 H18 — PTD29 PTD29 FB_AD29 NF_IO13 FTM3_CH2SPI2_SIN H17 — PTD28 PTD28 FB_AD28 NF_IO12 I2C2_SCLFTM3_CH3SPI2_SOUT H16 — PTD27 PTD27 FB_AD27 NF_IO11 I2C2_SDAFTM3_CH4SPI2_SCK Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018
96 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort G16 — PTD26 PTD26 FB_AD26 NF_IO10 FTM3_CH5SDHC1_WP G18 — PTD25 PTD25 FB_AD25 NF_IO9 FTM3_CH6 G19 — PTD24 PTD24 FB_AD24 NF_IO8 FTM3_CH7 G20 124 PTD23 PTD23/ MII0_ RXDATA[3] FB_AD23 NF_IO7 FTM2CH0ENET0_ 1588_TMR0 SDHC0_ DAT4 SCI2_TX DCU1_R3 F20 126 PTD22 PTD22/ MII0_ RXDATA[2] FB_AD22 NF_IO6 FTM2CH1ENET0_ 1588_TMR1 SDHC0_ DAT5 SCI2_RX DCU1_R4 F19 128 PTD21 PTD21/ MII0_CRS FB_AD21 NF_IO5 ENET0_ 1588_TMR2 SDHC0_ DAT6 SCI2_RTSDCU1_R5 F17 129 PTD20 PTD20/ MII0_COL FB_AD20 NF_IO4 ENET0_ 1588_TMR3 SDHC0_ DAT7 SCI2_CTSDCU1_R0 F16 130 PTD19 PTD19 FB_AD19 NF_IO3 ESAI_SCKRI2C0_SCLFTM2_QD_ PHA MII0_ TXDATA[3] DCU1_R1 E18 131 PTD18 PTD18 FB_AD18 NF_IO2 ESAI_FSRI2C0_SDAFTM2_QD_ PHB MII0_ TXDATA[2] DCU1_G0 E20 132 PTD17 PTD17 FB_AD17 NF_IO1 ESAI_HCKRI2C1_SCL MII0_TXERRDCU1_G1 D20 133 PTD16 PTD16 FB_AD16 NF_IO0 ESAI_HCKTI2C1_SDA DCU1_G2 Y17 86 PTD0 PTD0 QSPI0_A_ SCK SCI2_TX FB_AD15 SPDIF_ EXTCLK Y18 87 PTD1 PTD1 QSPI0_A_ CS0 SCI2_RX FB_AD14 SPDIF_IN1 V18 88 PTD2 PTD2 QSPI0_A_ DATA3 SCI2_RTSSPI1_PCS3FB_AD13 SPDIF_OUT1 Y19 89 PTD3 PTD3 QSPI0_A_ DATA2 SCI2_CTSSPI1_PCS2FB_AD12 SPDIF_ PLOCK W19 90 PTD4 PTD4 QSPI0_A_ DATA1 SPI1_PCS1FB_AD11 SPDIF_ SRCLK W20 91 PTD5 PTD5 QSPI0_A_ DATA0 SPI1_PCS0FB_AD10 V20 92 PTD6 PTD6 QSPI0_A_ DQS SPI1_SIN FB_AD9 V19 93 PTD7 PTD7 QSPI0_B_ SCK SPI1_SOUTFB_AD8 U17 94 PTD8 PTD8 QSPI0_B_ CS0 FB_CLKOUTSPI1_SCKFB_AD7 U18 97 PTD9 PTD9 QSPI0_B_ DATA3 SPI3_PCS1 FB_AD6 SAI1_TX_ SYNC DCU1_B0 U20 98 PTD10 PTD10 QSPI0_B_ DATA2 SPI3_PCS0 FB_AD5 DCU1_B1 T20 99 PTD11 PTD11 QSPI0_B_ DATA1 SPI3_SIN FB_AD4 T19 100 PTD12 PTD12 QSPI0_B_ DATA0 SPI3_SOUT FB_AD3 T18 101 PTD13 PTD13 QSPI0_B_ DQS SPI3_SCK FB_AD2 Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 97
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort A19 141 PTB23 PTB23 SAI0_TX_ BCLK SCI1_TX FB_MUXED_ ALE FB_TS_b SCI3_RTSDCU1_G3 A18 142 PTB24 PTB24 SAI0_RX_ BCLK SCI1_RX FB_MUXED_ TSIZ0 NF_WE_bSCI3_CTSDCU1_G4 B17 149 PTB25 PTB25 SAI0_RX_ DATA SCI1_RTS FB_CS1_bNF_CE0_b DCU1_G5 A17 150 PTB26 RCON21 PTB26 SAI0_TX_ DATA SCI1_CTSRCON21 FB_CS0_bNF_CE1_b DCU1_G6 U8 57 PTB27 RCON22 PTB27 SAI0_RX_ SYNC RCON22 FB_OE_b FB_MUXED_ TBST_b NF_RE_b DCU1_G7 A16 151 PTB28 RCON23 PTB28 SAI0_TX_ SYNC RCON23 FB_RW_b DCU1_B6 D16 153 PTC26 RCON24 PTC26 SAI1_TX_ BCLK SPI0_PCS5RCON24 FB_TA_b NF_RB_b DCU1_B7 E16 154 PTC27 RCON25 PTC27 SAI1_RX_ BCLK SPI0_PCS4RCON25 FB_BE3_bFB_CS3_bNF_ALE DCU1_B2 E15 155 PTC28 RCON26 PTC28 SAI1_RX_ DATA SPI0_PCS3RCON26 FB_BE2_bFB_CS2_bNF_CLE DCU1_B3 C16 152 PTC29 RCON27 PTC29 SAI1_TX_ DATA SPI0_PCS2RCON27 FB_BE1_bFB_MUXED_ TSIZ1 DCU1_B4 T8 58 PTC30 RCON28 PTC30 SAI1_RX_ SYNC SPI1_PCS2RCON28 FB_MUXED_ BE0_b FB_TSIZ0ADC0_SE5DCU1_B5 W5 42 PTC31 RCON29 PTC31 SAI1_TX_ SYNC RCON29 ADC1_SE5DCU1_B6 N16 103 PTE0 BOOTMOD1PTE0 DCU0_ HSYNC/ DCU0_ TCON1 BOOTMOD1 LCD0 N18 104 PTE1 BOOTMOD0PTE1 DCU0_ VSYNC/ DCU0_ TCON2 BOOTMOD0 LCD1 N19 105 PTE2 PTE2 DCU0_PCLK LCD2 Y15 77 PTE3 PTE3 DCU0_TAG/ DCU0_ TCON0 LCD3 N20 106 PTE4 PTE4 DCU0_DE/ DCU0_ TCON3 LCD4 T16 80 PTE5 PTE5 DCU0_R0 LCD5 W16 81 PTE6 PTE6 DCU0_R1 LCD6 M20 109 PTE7 RCON0 PTE7 DCU0_R2 RCON0 LCD7 M19 110 PTE8 RCON1 PTE8 DCU0_R3 RCON1 LCD8 M17 111 PTE9 RCON2 PTE9 DCU0_R4 RCON2 LCD9 M16 112 PTE10 RCON3 PTE10 DCU0_R5 RCON3 LCD10 L16 113 PTE11 RCON4 PTE11 DCU0_R6 RCON4 LCD11 L17 114 PTE12 RCON5 PTE12 DCU0_R7SPI1_PCS3RCON5 LCD12 LPT_ALT0 Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018
98 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort Y16 78 PTE13 PTE13 DCU0_G0 LCD13 W15 76 PTE14 PTE14 DCU0_G1 LCD14 L18 115 PTE15 RCON6 PTE15 DCU0_G2 RCON6 LCD15 L20 116 PTE16 RCON7 PTE16 DCU0_G3 RCON7 LCD16 K20 117 PTE17 RCON8 PTE17 DCU0_G4 RCON8 LCD17 K19 118 PTE18 RCON9 PTE18 DCU0_G5 RCON9 LCD18 K18 119 PTE19 RCON10 PTE19 DCU0_G6 RCON10 LCD19 I2C0_SCL A12 170 PTE20 RCON11 PTE20 DCU0_G7 RCON11 LCD20 I2C0_SDA EWM_in V16 79 PTE21 PTE21 DCU0_B0 LCD21 W17 84 PTE22 PTE22 DCU0_B1 LCD22 J17 122 PTE23 RCON12 PTE23 DCU0_B2 RCON12 LCD23 D19 134 PTE24 RCON13 PTE24 DCU0_B3 RCON13 LCD24 C19 135 PTE25 RCON14 PTE25 DCU0_B4 RCON14 LCD25 C20 137 PTE26 RCON15 PTE26 DCU0_B5 RCON15 LCD26 B20 138 PTE27 RCON16 PTE27 DCU0_B6 RCON16 LCD27 I2C1_SCL K16 120 PTE28 RCON17 PTE28 DCU0_B7 RCON17 LCD28 I2C1_SDA EWM_out V15 75 PTA7 PTA7 VIU_PIX_ CLK T14 — EXT_ TAMPER0 EXT_ TAMPER0 U14 — EXT_ TAMPER1 EXT_ TAMPER1 T13 — EXT_ TAMPER2/ EXT_WM0_ TAMPER_IN EXT_ TAMPER2/ EXT_WM0_ TAMPER_IN U13 — EXT_ TAMPER3/ EXT_WM0_ TAMPER_ OUT EXT_ TAMPER3/ EXT_WM0_ TAMPER_ OUT U12 — EXT_ TAMPER4/ EXT_WM1_ TAMPER_IN EXT_ TAMPER4/ EXT_WM1_ TAMPER_IN U10 — EXT_ TAMPER5/ EXT_WM1_ TAMPER_ OUT EXT_ TAMPER5/ EXT_WM1_ TAMPER_ OUT G7 2 VDD VDD J7 22 VDD VDD L7 48 VDD VDD H8 — VDD VDD K8 85 VDD VDD Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 99
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort M8 102 VDD VDD P8 125 VDD VDD G9 136 VDD VDD N9 174 VDD VDD H10 — VDD VDD P10 — VDD VDD G11 — VDD VDD N11 — VDD VDD H12 — VDD VDD P12 — VDD VDD G13 — VDD VDD J13 — VDD VDD L13 — VDD VDD N13 — VDD VDD H14 — VDD VDD K14 — VDD VDD M14 — VDD VDD P14 — VDD VDD A1 1 VSS VSS A20 13 VSS VSS B3 20 VSS VSS B5 25 VSS VSS B8 45 VSS VSS B11 — VSS VSS B13 — VSS VSS B16 — VSS VSS B19 — VSS VSS C2 — VSS VSS D17 — VSS VSS E5 — VSS VSS E8 — VSS VSS E11 — VSS VSS E14 — VSS VSS E19 — VSS VSS F2 — VSS VSS G17 — VSS VSS H4 — VSS VSS J2 — VSS VSS J18 — VSS VSS M2 — VSS VSS Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018
100 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort M4 — VSS VSS M18 — VSS VSS R2 — VSS VSS R18 — VSS VSS U7 — VSS VSS U19 — VSS VSS V13 — VSS VSS W6 — VSS VSS V17 — VSS VSS Y1 — VSS VSS Y20 — VSS VSS H19 — VSS VSS L19 — VSS VSS P19 — VSS VSS J5 — SDRAMC_ VDD2P5 SDRAMC_ VDD2P5 E6 — SDRAMC_ VDD2P5 SDRAMC_ VDD2P5 E10 — SDRAMC_ VDD2P5 SDRAMC_ VDD2P5 E4 — SDRAMC_ VDD1P5 SDRAMC_ VDD1P5 D5 — SDRAMC_ VDD1P5 SDRAMC_ VDD1P5 F5 — SDRAMC_ VDD1P5 SDRAMC_ VDD1P5 H5 — SDRAMC_ VDD1P5 SDRAMC_ VDD1P5 K5 — SDRAMC_ VDD1P5 SDRAMC_ VDD1P5 E7 — SDRAMC_ VDD1P5 SDRAMC_ VDD1P5 E9 — SDRAMC_ VDD1P5 SDRAMC_ VDD1P5 D11 — SDRAMC_ VDD1P5 SDRAMC_ VDD1P5 K3 10 VDD33 VDD33 N3 21 VDD33 VDD33 V8 52 VDD33 VDD33 C12 — VDD33 VDD33 C15 83 VDD33 VDD33 U16 95 VDD33 VDD33 K17 108 VDD33 VDD33 Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 101
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort N17 127 VDD33 VDD33 T17 140 VDD33 VDD33 C18 146 VDD33 VDD33 F18 158 VDD33 VDD33 W18 168 VDD33 VDD33 H7 — VSS VSS K7 74 VSS VSS M7 82 VSS VSS P7 96 VSS VSS G8 107 VSS VSS J8 — VSS VSS L8 139 VSS VSS N8 — VSS VSS H9 157 VSS VSS J9 175 VSS VSS K9 176 VSS VSS L9 — VSS VSS M9 — VSS VSS P9 — VSS VSS G10 — VSS VSS J10 — VSS VSS K10 — VSS VSS L10 — VSS VSS M10 — VSS VSS N10 — VSS VSS H11 — VSS VSS J11 — VSS VSS K11 — VSS VSS L11 — VSS VSS M11 — VSS VSS P11 — VSS VSS G12 — VSS VSS J12 — VSS VSS K12 — VSS VSS L12 — VSS VSS M12 — VSS VSS N12 — VSS VSS H13 — VSS VSS K13 — VSS VSS M13 — VSS VSS Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018
102 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort P13 — VSS VSS G14 — VSS VSS J14 — VSS VSS L14 — VSS VSS N14 — VSS VSS N7 — FA_VDD FA_VDD V14 — VBAT VBAT — FLG VSS VSS
12.2 Pinout diagrams
The 176 LQFP parts are not pin compatible between the F and R series families devices. NOTE If tamper detection is not required, the tamper pins must be tied to ground. Pinouts VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 103
89 PTD3
90 PTD4
91 PTD5
92 PTD6
93 PTD7
94 PTD8
95 VDD33
96 VSS
97 PTD9
98 PTD10
99 PTD11
100 PTD12
101 PTD13
102 VDD
103 PTE0
104 PTE1
105 PTE2
106 PTE4
107 VSS
108 VDD33
109 PTE7
110 PTE8
111 PTE9
112 PTE10
113 PTE11
114 PTE12
115 PTE15
116 PTE16
117 PTE17
118 PTE18
119 PTE19
120 PTE28
121 PTB8
122 PTE23
123 PTB9
124 PTD23
125 VDD
126 PTD22
127 VDD33
128 PTD21
129 PTD20
130 PTD19
131 PTD18
132 PTD17
133 PTD16
134 PTE24
135 PTE25
136 VDD
137 PTE26
138 PTE27
139 VSS
140 VDD33
141 PTB23
142 PTB24
143 PTA20
144 VSS
145 PTA21
146 VDD33
147 PTA22
148 PTA23
149 PTB25
150 PTB26
151 PTB28
152 PTC29
153 PTC26
154 PTC27
155 PTC28
156 PTB13
157 VSS
158 VDD33
159 PTB10
160 PTB17
161 PTB15
162 PTB14
163 PTB16
164 PTB11
165 PTB12
166 PTB7
167 PTB19
168 VDD33
169 PTB20
170 PTE20
171 PTB18
172 PTB22
173 PTB21
174 VDD
175 VSS
176 VSS
Figure 59. 176 LQFP Pinout Diagram
104 NXP Semiconductors
Figure 60. 364-pin BGA package ballmap
12.2.1 GPIO Mapping
Table 78. RGPIO versus Pins Table continues on the next page...
Table 78. RGPIO versus Pins (continued) Table continues on the next page...
106 NXP Semiconductors
Table continues on the next page...
Table continues on the next page...
108 NXP Semiconductors
12.2.2 Special Signal
Table 79. Special Signal Considerations provide the predriver supply for the DDR I/O segment. EXT_POR, TEST Factory use only, tie to ground.. FA_VDD Factory use only, tie to VDD. Table continues on the next page...
Table 79. Special Signal Considerations (continued) JTCLK, JTDI, JTDO, JTMS For JTAG the use of external resistors is unnecessary. detrimental and should be avoided. observation purposes during debug only. required to guarantee a reset is detected. must swing from ~0.8 x DECAP_V11_ LDO_OUT to ~0.2 V. load) should be connected between XTAL32 and EXTAL32. XTAL32 and EXTAL32 to either power or ground (>100 MΩ).
110 NXP Semiconductors
13.1 Power Supply Pins
Table 80. Power Supply Pins Table continues on the next page...
Table 80. Power Supply Pins (continued)
14.1 Functional Assignment Pins
Table 81. Functional Assignment Pins
364 MAP
176 LQFP
Table continues on the next page...
112 NXP Semiconductors
Table continues on the next page...
Table continues on the next page...
114 NXP Semiconductors
Table continues on the next page...
Table continues on the next page...
116 NXP Semiconductors
Table continues on the next page...
Table continues on the next page...
118 NXP Semiconductors
Table continues on the next page...
120 NXP Semiconductors
The following table provides a revision history for this document. Table 82. Revision History Table continues on the next page...
Revision History
VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 121
Table 82. Revision History (continued) Added notes in DDR3 Timing Parameters and LPDD2 Timing Parameters sections.
- Replaced references to Auto and IMM by R-series and F-series respectively
- In the feature list, the ARM Core frequency changed to 500 MHz for F-series
- In the feature list, changed the DRAM controller frequency
- Updated Part Nummbering format
- Clarified the Fields table as per Marketing
- Sample numbers updated
- From the VREG electrical specifications tables, deleted pre-trimming rows and comments
- .In the HPREG electrical characteristics table, add footnote on maximum Output Current Capacity
- In the ULPREG electrical characteristics table, clarified max value of Output voltage @ no load and min value of Output voltage @ full load
- In the WBREG electrical characteristics table, clarified max value of Output voltage @ no load and min value of Output voltage @ full load
- In the LVD electrical specifications table, added typ. values of Upper voltage threshold (value @27oC) and Lower voltage threshold (value @27oC)
- In the LVD DIG electrical specifications table, removed pretrimming values and clarified other values
- Updated LVD DIG electrical specifications values
- Updated LDO_1P1 tables Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
122 NXP Semiconductors
- Updated LDO_2P5 table
- Updated Power consumption operating behaviors tables
- Updated Absolute maximum ratings table
- Removed Temperature Voltage Monitor section to security RM
- Updated VideoADC Specifications table Rev 6 1/2014 • Added QuadSPI electricals
- Changed VBB references to VBAT
- In the feature list, clarified that ECC supported for 8-bit mode only, not 16-bit.
- Revised the part number format
- Revised the field table
- Added Absolute Maximum Rating table, which was madde non_cust in the previous version
- In the Power Consumption Operating Behavior table, Revised min and max value of IDD_LPS3 and IDD_LPS2. Removed IDD_LPS1 row
- In the USB PHY Current Consumption table, removed the Normal Mode
- In the Power Sequence table, revised the Power UP/ Down Order column for USB0_VBUs and USB1_VBUS
- In the Recommended operating conditions table, revised the min value of VBAT. Revised the min value of VREFH_ADC Revised the min and max values of SDRAMC_VDD1P5
- In the Recommended Connections for Unused Analog Interfaces section, added the notes. Revised the Recommendation if Unused column
- In the 12-bit ADC operating conditions, revised Conditions for Ground voltage. Revised min Ref High Voltage
- In the 12-bit DAC operating requirements, revised the min and max value of VREFH_ADC
- In the SDHC switching specifications, revised the max value of SD6
- In the 24MHz external oscillator electrical characteristics table, revised the min value of VIH and max value of VIL Rev 7 11/2014 • Updated list of security features on page 1.
- In "Part number format" figure, updated explanation for '1'.
- In "Fields" table, updated definition of 'R'.
- In "Part Numbers" table, added parts SVF331R3K1CKU2, SVF531R3K1CMK4, and SVF532R2K1CMK4.
- In "External NPN ballast" section, updated recommendations for transistor selection.
- In "DDR parameters" section, updated table footnotes regarding typical condition.
- In "Power sequencing" table, added comment regarding SDRAMC_VDD1P5: "In case the Ballast transistor’s collector is connected to the 1.5 V DRAM supply (instead of the 3.3 V supply), turn this 1.5 V supply on before turning on the 3.3V."
- In "VideoADC specifications" table, added supply current values.
- In "Receive and Transmit signal timing specifications," added the following note: "See the most current errata document when using the internally generated RXCLK and TXCLK clocks."
- Updated "QuadSPI timing" section, presenting data based on a negative edge data launch from the device and a negative edge data capture; updated the figure, "QuadSPI Input/Read timing (SDR mode)"; updated the table, "QuadSPI Input/Read timing (SDR mode)."
- For the "SDHC switching specifcations" table, added the statement, "A load of 50 pF is assumed"; updated max value for SD6, SDHC output delay (output valid).
- In the "24 MHz oscillator specifications" section, added the statement, "The crystal must be rated for a drive level of 250 μW or higher. An ESR (equivalent series resistance) of 80 Ω or less is recommended to achieve a gain margin of 5."
- In "Pinouts" section, for the 176LQFP package, added information about exposed pad on the bottom side.
- In "Special Signal Considerations" table, added that a "fundamental-mode" crystal should be connected between XTAL and EXTAL; updated maximum drive level of crystal rating to 250 μW. Rev 8 01/2018 • Throughout: Updated references to company website
- In the "Part number format" figure, updated the "Option" box with mask options
VF3xxR, VF5xxR, Rev. 8, 01/2018 NXP Semiconductors 123
- Deleted the "Fields" section
- Updated part numbers in "Part numbers" section
- In "Power consumption operating behaviors" section, updated descriptions and footnotes for IDD_LPS3 and IDD_LPS2
- In "Absolute maximum ratings" table, added rows for USB0_DP, USB0_DN, USB1_DP, and USB1_DN
- In the table, "12-bit ADC characteristics (V REFH = VDDAD, VREFL = VSSAD)":
- Changed mentions of "Temp Sensor" to "Temperature Sensor"
- Added footnotes 2 and 3
- In the table, "12-bit DAC operating behaviors," in footnote 5, changed "V DDA = 3.0 V" to "VDDA = 3.3 V"
- In "Video Input Unit timing" section, added clocking requirements after introduction
- Updated "QuadSPI timing" section
- For "NFC specifications" section:
- Changed title to "NAND flash controller specifications"
- In the note, specified that the reader should see the CCM section of the product reference manual for more information
- Changed title of the figure "Read data latch cycle timing in non-fast mode" to "Read data latch cycle timing in Slow mode"
- Changed title of the figure "Read data latch cycle timing in fast mode" to "Read data latch cycle timing in Fast mode and EDO mode"
- In the table footnotes in the "I2C timing" section, updated the frequency of the PER_CLK, from 83 MHz to 66 MHz
- In the "Pinouts" table, for L5, changed RMII0_MDIO/MII0_MDC to RMII0_MDIO/ MII0_MDIO
VF3xxR, VF5xxR, Rev. 8, 01/2018
124 NXP Semiconductors
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