STY60NM50

STY60NM50 STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 500V - 0.045Ω - 60A Max247 Zener-Protected MDmesh™Power MOSFET /c110 TYPICAL R DS (on) = 0.045Ω /c110 HIGH dv/dt AND AVALANCHE CAPABILITIES /c110 IMPROVED ESD CAPABILITY /c110 LOW INPUT CAPACITANCE AND GATE CHARGE /c110 LOW GATE INPUT RESISTANCE /c110 TIGHT PROCESS CONTROL /c110 INDUSTRY’S LOWEST ON-RESISTANCE

DESCRIPTION

The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain pro- cess with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products.

APPLICATIONS

The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. ABSOLUTE MAXIMUM RATINGS (•)Pulse width limited by safe operating area TYPE V DSS R DS(on) ID STY60NM50 500V < 0.05 Ω 60 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 500 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 500 V VGS Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 60 A ID Drain Current (continuous) at TC = 100°C 37.8 A IDM (/c108 ) Drain Current (pulsed) 240 A PTOT Total Dissipation at TC = 25°C 560 W VESD(G-S) Gate source ESD(HBM-C=100pF, R=15KΩ) 6K V Derating Factor 4.5 W/°C dv/dt (1) Peak Diode Recovery voltage slope 15 V/ns Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (1)ISD ≤60A, di/dt ≤400A/µs, VDD ≤ V(BR)DSS , Tj ≤ TJMAX Max247 INTERNAL SCHEMATIC DIAGRAM

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. Rthj-case Thermal Resistance Junction-case Max 0.22 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 30 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR , VDD = 35 V) 1.4 J Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 500 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 10 µA VDS = Max Rating, TC = 125 °C 100 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ± 10 µA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250µA 345V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 30A 0.045 0.05 Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance V DS > ID(on) x RDS(on)max, ID = 30A 35 S C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 7500 pF C oss Output Capacitance 980 pF C rss Reverse Transfer Capacitance 200 pF R G Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 1.5 Ω

ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 250V, ID = 30A R G = 4.7Ω VGS = 10V (see test circuit, Figure 3) 51 ns tr Rise Time 58 ns Q g Total Gate Charge VDD = 400V, ID = 60A, VGS = 10V 190 266 nC Q gs Gate-Source Charge 53 nC Q gd Gate-Drain Charge 97 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit tr(Voff) Off-voltage Rise Time VDD = 400V, ID = 60A, R G = 4.7Ω, VGS = 10V (see test circuit, Figure 5) 51 ns tf Fall Time 46 ns tc Cross-over Time 108 ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 60 A ISDM (2) Source-drain Current (pulsed) 240 A VSD (1) Forward On Voltage ISD = 60A, VGS = 0 1.5 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 60A, di/dt = 100A/µs, VDD = 100 V, Tj = 25°C (see test circuit, Figure 5) 532 9.9 ns µC A trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60A, di/dt = 100A/µs, VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 636 13.4 ns µC A Safe Operating Area Thermal Impedance

Static Drain-source On Resistance Transfer Characteristics Gate Charge vs Gate-source Voltage Capacitance Variations

Normalized Gate Threshold Voltage vs Temp. Source-drain Diode Forward Characteristics Normalized On Resistance vs Temperature

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm inch A 4.70 5.30 A1 2.20 2.60 b 1.00 1.40 b1 2.00 2.40 b2 3.00 3.40 c 0.40 0.80 D 19.70 20.30 e 5.35 5.55 E 15.30 15.90 L 14.20 15.20 L1 3.70 4.30 P025Q Max247 MECHANICAL DATA

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